wip
This commit is contained in:
Miodrag Milanovic
parent
81bb944e2b
commit
718b8e7766
210
gatemate/die.py
210
gatemate/die.py
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@ -513,14 +513,25 @@ RAM_HALF_PINS = [
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PRIMITIVES_PINS = {
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"CPE_LT_U": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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# LUT2 first level
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Pin("D0_00" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D1_00" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D0_01" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D1_01" ,PinType.INPUT, "CPE_WIRE", True),
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# LUT2 2nd level
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Pin("D0_10" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D1_10" ,PinType.INPUT, "CPE_WIRE", True),
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# MX4 inputs
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Pin("M1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("M2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("M3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("M4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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],
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"CPE_FF_U": [
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Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True),
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@ -536,26 +547,40 @@ PRIMITIVES_PINS = {
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_LT_L": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COMBIN" ,PinType.INPUT, "CPE_WIRE", True),
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# LUT2 first level
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Pin("D0_00" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D1_00" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D0_01" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D1_01" ,PinType.INPUT, "CPE_WIRE", True),
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# LUT2 2nd level
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Pin("D0_10" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("D1_10" ,PinType.INPUT, "CPE_WIRE", True),
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# LUT2 3rd level input
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Pin("COMBIN" ,PinType.INPUT, "CPE_WIRE", True),
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# MX4 inputs
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Pin("M1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("M2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("M3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("M4" ,PinType.INPUT, "CPE_WIRE", True),
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# outputs
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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#Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True),
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#Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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#Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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#Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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#Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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#Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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#Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_FF_L": [
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Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True),
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@ -2960,14 +2985,26 @@ def get_pin_connection_name(prim, pin):
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return "CPE.COMBOUT2_int"
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case "CPOUT":
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return "CPE.CPOUT2_int"
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case "IN1":
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return "CPE.IN1_int"
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case "IN2":
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return "CPE.IN2_int"
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case "IN3":
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return "CPE.IN3_int"
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case "IN4":
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return "CPE.IN4_int"
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case "D0_00":
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return "CPE.D0_00_int"
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case "D1_00":
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return "CPE.D1_00_int"
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case "D0_01":
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return "CPE.D0_01_int"
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case "D1_01":
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return "CPE.D1_01_int"
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case "D0_10":
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return "CPE.D0_10_int"
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case "D1_10":
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return "CPE.D1_10_int"
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case "M1":
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return "CPE.IN1"
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case "M2":
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return "CPE.IN2"
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case "M3":
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return "CPE.IN3"
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case "M4":
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return "CPE.IN4"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_FF_U":
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@ -2996,14 +3033,26 @@ def get_pin_connection_name(prim, pin):
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return "CPE.COMBOUT1_int"
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case "CPOUT":
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return "CPE.CPOUT1_int"
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case "IN1":
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return "CPE.IN5_int"
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case "IN2":
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return "CPE.IN6_int"
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case "IN3":
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return "CPE.IN7_int"
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case "IN4":
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return "CPE.IN8_int"
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case "D0_00":
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return "CPE.D0_02_int"
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case "D1_00":
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return "CPE.D1_02_int"
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case "D0_01":
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return "CPE.D0_03_int"
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case "D1_01":
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return "CPE.D1_03_int"
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case "D0_10":
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return "CPE.D0_11_int"
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case "D1_10":
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return "CPE.D1_11_int"
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case "M1":
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return "CPE.IN5"
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case "M2":
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return "CPE.IN6"
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case "M3":
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return "CPE.IN7"
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case "M4":
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return "CPE.IN8"
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case "COMBIN":
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return "CPE.COMBIN_int"
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case _:
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@ -3021,21 +3070,21 @@ def get_pin_connection_name(prim, pin):
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case "MUXOUT":
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return "CPE.MUXOUT_int"
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case "IN1":
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return "CPE.IN1_int"
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return "CPE.IN1"
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case "IN2":
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return "CPE.IN2_int"
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return "CPE.IN2"
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case "IN3":
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return "CPE.IN3_int"
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return "CPE.IN3"
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case "IN4":
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return "CPE.IN4_int"
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return "CPE.IN4"
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case "IN5":
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return "CPE.IN5_int"
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return "CPE.IN5"
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case "IN6":
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return "CPE.IN6_int"
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return "CPE.IN6"
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case "IN7":
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return "CPE.IN7_int"
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return "CPE.IN7"
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case "IN8":
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return "CPE.IN8_int"
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return "CPE.IN8"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_BRIDGE":
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@ -3043,21 +3092,21 @@ def get_pin_connection_name(prim, pin):
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case "MUXOUT":
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return "CPE.MUXOUT_int"
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case "IN1":
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return "CPE.IN1_int"
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return "CPE.IN1"
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case "IN2":
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return "CPE.IN2_int"
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return "CPE.IN2"
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case "IN3":
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return "CPE.IN3_int"
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return "CPE.IN3"
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case "IN4":
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return "CPE.IN4_int"
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return "CPE.IN4"
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case "IN5":
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return "CPE.IN5_int"
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return "CPE.IN5"
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case "IN6":
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return "CPE.IN6_int"
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return "CPE.IN6"
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case "IN7":
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return "CPE.IN7_int"
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return "CPE.IN7"
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case "IN8":
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return "CPE.IN8_int"
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return "CPE.IN8"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_FF_L":
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@ -3141,6 +3190,21 @@ def get_endpoints_for_type(type):
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create_wire("CPE.IN6" , type="CPE_WIRE_L")
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create_wire("CPE.IN7" , type="CPE_WIRE_L")
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create_wire("CPE.IN8" , type="CPE_WIRE_L")
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create_wire("CPE.D0_00_int", type="CPE_WIRE_INT")
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create_wire("CPE.D1_00_int", type="CPE_WIRE_INT")
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create_wire("CPE.D0_01_int", type="CPE_WIRE_INT")
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create_wire("CPE.D1_01_int", type="CPE_WIRE_INT")
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create_wire("CPE.D0_10_int", type="CPE_WIRE_INT")
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create_wire("CPE.D1_10_int", type="CPE_WIRE_INT")
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create_wire("CPE.D0_02_int", type="CPE_WIRE_INT")
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create_wire("CPE.D1_02_int", type="CPE_WIRE_INT")
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create_wire("CPE.D0_03_int", type="CPE_WIRE_INT")
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create_wire("CPE.D1_03_int", type="CPE_WIRE_INT")
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create_wire("CPE.D0_11_int", type="CPE_WIRE_INT")
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create_wire("CPE.D1_11_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN1_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN2_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN3_int", type="CPE_WIRE_INT")
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@ -3149,6 +3213,7 @@ def get_endpoints_for_type(type):
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create_wire("CPE.IN6_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN7_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN8_int", type="CPE_WIRE_INT")
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create_wire("CPE.OUT1_int", type="CPE_WIRE_INT")
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create_wire("CPE.OUT2_int", type="CPE_WIRE_INT")
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create_wire("CPE.COMBOUT1_int", type="CPE_WIRE_INT")
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@ -3371,6 +3436,39 @@ def get_mux_connections_for_type(type):
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# CPE
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for i in range(1,9):
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create_direct(f"CPE.IN{i}", f"CPE.IN{i}_int", delay="del_dummy")
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create_mux("CPE.IN1_int", "CPE.D0_00_int", 1, 0, False, "CPE.D0_00", True, delay="del_dummy")
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create_mux("CPE.IN2_int", "CPE.D1_00_int", 1, 0, False, "CPE.D1_00", True, delay="del_dummy")
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create_mux("CPE.IN2_int", "CPE.D0_00_int", 1, 1, False, "CPE.D0_00", True, delay="del_dummy")
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create_mux("CPE.IN1_int", "CPE.D1_00_int", 1, 1, False, "CPE.D1_00", True, delay="del_dummy")
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create_mux("CPE.IN3_int", "CPE.D0_01_int", 1, 0, False, "CPE.D0_01", True, delay="del_dummy")
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create_mux("CPE.IN4_int", "CPE.D1_01_int", 1, 0, False, "CPE.D1_01", True, delay="del_dummy")
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create_mux("CPE.IN4_int", "CPE.D0_01_int", 1, 1, False, "CPE.D0_01", True, delay="del_dummy")
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create_mux("CPE.IN3_int", "CPE.D1_01_int", 1, 1, False, "CPE.D1_01", True, delay="del_dummy")
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create_mux("CPE.D0_00_int", "CPE.D0_10_int", 1, 0, False, "CPE.D0_10", True, delay="del_dummy")
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create_mux("CPE.D0_01_int", "CPE.D1_10_int", 1, 0, False, "CPE.D1_10", True, delay="del_dummy")
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create_mux("CPE.D0_01_int", "CPE.D0_10_int", 1, 1, False, "CPE.D0_10", True, delay="del_dummy")
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create_mux("CPE.D0_00_int", "CPE.D1_10_int", 1, 1, False, "CPE.D1_10", True, delay="del_dummy")
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create_mux("CPE.IN5_int", "CPE.D0_02_int", 1, 0, False, "CPE.D0_02", True, delay="del_dummy")
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create_mux("CPE.IN6_int", "CPE.D1_02_int", 1, 0, False, "CPE.D1_02", True, delay="del_dummy")
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create_mux("CPE.IN6_int", "CPE.D0_02_int", 1, 1, False, "CPE.D0_02", True, delay="del_dummy")
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create_mux("CPE.IN5_int", "CPE.D1_02_int", 1, 1, False, "CPE.D1_02", True, delay="del_dummy")
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create_mux("CPE.IN7_int", "CPE.D0_03_int", 1, 0, False, "CPE.D0_03", True, delay="del_dummy")
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create_mux("CPE.IN8_int", "CPE.D1_03_int", 1, 0, False, "CPE.D1_03", True, delay="del_dummy")
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create_mux("CPE.IN8_int", "CPE.D0_03_int", 1, 1, False, "CPE.D0_03", True, delay="del_dummy")
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create_mux("CPE.IN7_int", "CPE.D1_03_int", 1, 1, False, "CPE.D1_03", True, delay="del_dummy")
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create_mux("CPE.D0_02_int", "CPE.D0_11_int", 1, 0, False, "CPE.D0_11", True, delay="del_dummy")
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create_mux("CPE.D0_03_int", "CPE.D1_11_int", 1, 0, False, "CPE.D1_11", True, delay="del_dummy")
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create_mux("CPE.D0_03_int", "CPE.D0_11_int", 1, 1, False, "CPE.D0_11", True, delay="del_dummy")
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create_mux("CPE.D0_02_int", "CPE.D1_11_int", 1, 1, False, "CPE.D1_11", True, delay="del_dummy")
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for p in range(1,13):
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plane = f"{p:02d}"
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for i in range(8):
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