Commit Graph

217 Commits

Author SHA1 Message Date
Miodrag Milanovic ed5f85b371 wip 2025-12-17 08:32:34 +01:00
Miodrag Milanovic 443f249b84 disable these for now 2025-12-15 09:16:17 +01:00
Miodrag Milanovic a23d438ac4 fix pips 2025-12-12 09:18:38 +01:00
Miodrag Milanovic ab505c765d Fix wrong name and select proper timing 2025-12-12 09:18:38 +01:00
Miodrag Milanovic b878741e28 Enable clock CP lines 2025-12-12 09:18:38 +01:00
Miodrag Milanovic 6495c1f1bc do not use CP lines for now 2025-12-12 09:18:38 +01:00
Miodrag Milanovic 6d633ea23b need to use _int 2025-12-12 09:18:38 +01:00
Miodrag Milanovic 3d2699ffbf Enable pins 2025-12-12 09:18:38 +01:00
Miodrag Milanovic 014a237783 wip 2025-12-12 09:18:37 +01:00
Miodrag Milanovic 24aace0b30 wip 2025-12-12 09:18:37 +01:00
Miodrag Milanovic c529ceec32 wip 2025-12-12 09:18:37 +01:00
Miodrag Milanovic 718b8e7766 wip 2025-12-12 09:18:37 +01:00
Miodrag Milanovic 81bb944e2b Remove duplicated pips 2025-12-12 08:05:12 +01:00
Lofty 5a43fa5fc0 fix C_CLKSEL/C_ENSEL input 2025-11-10 16:18:00 +00:00
Miodrag Milanovic 1901f4b833 Bump chip database version 2025-11-10 12:00:22 +01:00
Miodrag Milanovic 6f9f132d55 Make bridge pips not visible 2025-11-10 11:59:39 +01:00
Miodrag Milanovic 632b223ce1 Add missing timings for IM 2025-11-10 11:59:31 +01:00
Lofty 41d9fd80f4 update schematics to include switchboxes 2025-11-01 11:07:28 +00:00
Miodrag Milanović 7782c1c450
Merge pull request #13 from pu-cc/gatemate-fix-serdes-cdr
TileBitDatabase: fix SERDES CDR parameters
2025-10-28 09:49:40 +01:00
Patrick Urban d6a8239d55 TileBitDatabase: fix SERDES CDR parameters 2025-10-27 15:47:19 +01:00
Miodrag Milanovic fffdc6610c Remove most of boost usage 2025-10-22 15:27:22 +02:00
Miodrag Milanovic e5df2fd309 add write_cmd_spll for designs without PLLs 2025-10-22 09:14:51 +02:00
Miodrag Milanović 1ab0612d22
Merge pull request #12 from pu-cc/bootaddr
Secondary bitstream and scrubber features
2025-10-21 08:01:01 +02:00
Patrick Urban 4d60ba5d78
Merge branch 'YosysHQ:main' into bootaddr 2025-10-21 07:07:08 +02:00
Patrick Urban 8d1018796d gmpack: reset config latches before bootaddr jump 2025-10-20 17:25:26 +02:00
Patrick Urban ac547baf3b gmpack: set `CMD_CHG_STATUS` config mode byte in bootaddr and background modes 2025-10-20 16:28:26 +02:00
Patrick Urban 9aa2711958 gmunpack: unpack `CMD_CFGRST` and `CMD_JUMP` 2025-10-20 13:58:12 +02:00
Miodrag Milanovic f081ba87cb Bump version to 1.9 2025-10-17 11:56:29 +02:00
Patrick Urban 0283a03d82 gmpack: add background reconfiguration feature 2025-10-15 23:19:50 +02:00
Patrick Urban f9183e4e2a docs: update `CMD_CHG_STATUS` PLL control register bits 2025-10-15 19:40:40 +02:00
Patrick Urban 1f3f9aad85 gmpack: enable config clock for reconfiguration 2025-10-15 19:37:33 +02:00
Patrick Urban 05d8ef6a43 gmpack: revert `CFG_RECONFIG` and `CFG_CPE_CFG` separation 2025-10-15 17:35:20 +02:00
Patrick Urban c74d0860d3 docs: update CMD_JUMP command 2025-10-15 17:24:56 +02:00
Patrick Urban 4597d1de96 gmpack: add bootaddr parameter for secondary bitstreams 2025-10-15 17:24:12 +02:00
Patrick Urban 72bc122449 gmpack: add option to clear config latches 2025-10-15 12:41:01 +02:00
Miodrag Milanovic 5d37e3a18f Add reconfig option 2025-10-07 13:43:51 +02:00
Miodrag Milanovic b4a3a82578 set stop and done only for die 0 2025-10-07 13:43:10 +02:00
Miodrag Milanovic 867835f7bb Better naming for D2D and pass trough TES as on hardware 2025-10-07 13:11:27 +02:00
Miodrag Milanovic 781780f017 Fix TES and RES 2025-10-07 12:24:43 +02:00
Miodrag Milanovic 89a4bd03d7 log iteration 2025-10-03 18:03:44 +02:00
Miodrag Milanovic 14e478fca5 Fix multi die unpack 2025-10-02 16:03:30 +02:00
Miodrag Milanovic 62bdd38fb0 Add delay blobs, fixes #9 2025-09-30 12:49:35 +02:00
Miodrag Milanović 0bbad32bc5
Merge pull request #11 from YosysHQ/pips
Include and use connection timing data
2025-09-30 09:13:12 +02:00
Miodrag Milanovic 36f6b5eec4 Bump version to 1.8 2025-09-23 08:08:07 +02:00
Miodrag Milanovic dda08d7bcd Use proper timing info 2025-09-12 10:02:38 +02:00
Miodrag Milanovic 8dfe05b5c5 put back old delay values 2025-09-11 16:45:42 +02:00
Miodrag Milanovic 5bae9cae91 del_dummy is default delay 2025-09-11 15:21:09 +02:00
Miodrag Milanovic 5a03c49c49 sortout multidie connections 2025-09-11 15:07:57 +02:00
Miodrag Milanovic 81bb1c5cb8 additional wires for IO and CLK for SB_BIG/SML 2025-09-11 14:58:21 +02:00
Miodrag Milanovic 3aec20a773 use sam delay 2025-09-11 14:11:47 +02:00