a385719765
doc: tangnano1k doesn't have external flash
2022-01-29 17:50:45 +02:00
a133be582d
board: add tangnano1k
2022-01-27 23:10:20 +02:00
977900954e
part: add GW1NZ-1
2022-01-27 22:55:21 +02:00
dc5eedfdde
adding constraints AC701
2022-01-27 09:32:59 +01:00
db407a4263
adding xilinx AC701 development kit
2022-01-26 16:42:03 +01:00
99df282905
alphabetical order
2022-01-26 16:27:16 +01:00
ed390f468a
Adding dev kit Xilinx Zynq-7000 SoC ZC702 Evaluation Kit
2022-01-26 16:14:00 +01:00
b91cd00688
doc/boards: tang Nano s/4k/9k/g
2022-01-22 16:01:16 +01:00
acf677dd46
tangnano9k: new board, with the same cable w/ tangnano4k
...
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 20:51:05 +08:00
dc4a454b94
gowin: add support for GW1NR-9C
...
GW1NR-9C has a different idcode with GW1NR-9.
Add support for it by adding the idcode.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 20:49:35 +08:00
fb2aadadad
cable: adding Olimex ARM-USB-OCD-H
2022-01-20 19:37:50 +01:00
a90ac3db7b
doc/boards: complete contraints
2022-01-19 18:59:24 +01:00
2d4c634b80
doc/FPGAs: ice40 memory support
2022-01-19 18:59:02 +01:00
70d17f2cc5
doc: cross-reference FPGA compatibility table and vendor notes
2022-01-17 23:28:18 +01:00
7fcc9b7d2c
doc: declare FPGA compatibility list through YAML file
2022-01-17 23:21:23 +01:00
dbc6551a3c
part: add Kintex 160T
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-01-14 09:01:23 +01:00
ecc76baa97
board: alinx AXU2CGA
2022-01-13 08:55:26 +01:00
904bf46315
part: adding zynqmp xczu2cg idcode
2022-01-13 08:48:53 +01:00
632767dee3
doc: add field 'Constraints' to 'boards.yml'
2022-01-12 12:55:03 +01:00
02ba4dfe83
doc/conf: add intersphinx mapping 'constraints'
2022-01-12 12:16:06 +01:00
8f4dd8850e
Merge pull request #160 from umarcor/doc-yaml
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doc: declare board compatibility through a YAML file
2022-01-12 08:41:42 +01:00
57e9860b43
doc: move 'board.inc' generation 'boards.py'
2022-01-12 03:00:55 +01:00
4be407a379
doc: declare board compatibility through a YAML file
2022-01-12 03:00:55 +01:00
71409d0b02
doc/compatibility/fpga: fix ref
2022-01-11 23:59:45 +01:00
ce7f4566c3
board: ulx3s_dfu
2021-12-24 18:10:22 +01:00
03c7d7faad
arty A7 100t support
2021-12-21 07:02:48 +01:00
f3e9a9fa6d
digilent_arty_z7 10/20 support
2021-12-20 18:10:17 +01:00
ee7570b251
zynq xc7z010 support
2021-12-20 18:09:52 +01:00
e026aa28c7
Digilent arty s7 25
2021-12-19 17:35:23 +01:00
a83fcf81f1
Merge pull request #151 from fjullien/efinix_titanium
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efinix: add support for Titanium Ti60 f225 dev kit
2021-12-14 20:27:10 +01:00
060ea129ec
doc/guide/install: archlinux: list required libraries to build from source
2021-12-14 07:51:49 +01:00
18349fb6e8
efinix: add support for Titanium Ti60 f225 dev kit
2021-12-13 22:13:29 +01:00
9f530227c4
colognechip integration: fix fpga.rst entry
2021-12-13 10:20:20 +01:00
1c91928175
Merge branch 'master' into colognechip/gatemate
2021-12-13 10:18:41 +01:00
5e0262a7db
colognechip integration: fix typo
2021-12-12 19:10:17 +01:00
c78aef0d07
colognechip integration: fix broken documentation
2021-12-12 18:31:05 +01:00
d4f17481d5
colognechip integration: update documentation
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* compatibility/board.rst, compatibility/cable.rst, compatibility/fpga.rst
* README.md and doc/index.rst to add new doc/vendors/colognechip.rst entry
2021-12-12 18:26:14 +01:00
42fbbd190c
Merge branch 'master' into elf2
2021-12-11 08:03:10 +01:00
dc657d8696
doc: fpga: fix anlogic AS -> OK
2021-12-11 07:31:30 +01:00
bc610383cd
part: add support for Anlogic ELF2 EF2M45
...
Anlogic EF2M45 is a FPGA with a co-packaged 4Mbit SPI Flash, and the
JTAG interface is the same with EG4S20.
Add support for it by adding it to the part database.
SPI Flash programming and SRAM programming are both tested.
The support of EF2M45 is also documented in this commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-11 02:12:32 +08:00
49e6602b9f
colognechip integration: update vendor documentation
2021-12-10 12:41:33 +01:00
d09e5da0ba
colognechip integration: initial commit
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This commit adds support for the Cologne Chip GateMate FPGA series. Both
Evaluation Board and Programmer Cable are supported. Configurations can be
loaded into the FPGA with both devices via JTAG or SPI. In addition to
reading/writing data from/to flashes directly via SPI, this can also be done
via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware
and flash is no longer necessary in this case.
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-12-10 12:12:32 +01:00
7ceaab0126
spiOverJtag: add bitstream for ECP4CE15F23
2021-11-28 16:51:42 +01:00
85d4bdb950
doc: convert TODO from md to rst
2021-11-28 10:24:07 +01:00
d125ce0ea1
doc: update index
2021-11-28 10:24:07 +01:00
50c395bef3
doc: convert compatibility lists from md to rst
2021-11-28 10:24:06 +01:00
bfa1167892
doc: convert guide from md to rst
2021-11-28 10:20:43 +01:00
2cb92af70f
doc: convert vendor notes from md to rst
2021-11-28 10:20:43 +01:00
53b3121c53
doc: add Sphinx site
2021-11-28 10:20:43 +01:00
b2e6c1dd07
doc/fpga-compatibility-list: with ice40 mem -> NA, flash -> AS
2021-11-28 09:35:50 +01:00
Verneri Hirvonen
Fabien Marteau
Gwenhael Goavec-Merou
Icenowy Zheng
umarcor
Karol Gugala
Franck Jullien
Patrick Urban