colognechip integration: initial commit

This commit adds support for the Cologne Chip GateMate FPGA series. Both Evaluation Board and Programmer Cable are supported. Configurations can be loaded into the FPGA with both devices via JTAG or SPI. In addition to reading/writing data from/to flashes directly via SPI, this can also be done via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware and flash is no longer necessary in this case. Signed-off-by: Patrick Urban <[email protected]>
2026-08-30 01:48:50 +02:00 · 2021-12-10 12:12:32 +01:00
parent e182a53659
commit d09e5da0ba
13 changed files with 672 additions and 3 deletions
@@ -0,0 +1,75 @@
+.. _colognechip:
+
+Cologne Chip notes
+##################
+
+Supported Boards/Cables
+=======================
+
+* GateMate Evaluation Board using board parameters `-b gatemate_evb_jtag` or `-b gatemate_evb_spi`
+* GateMate Programmer using cable parameter `-c gatemate_pgm`
+
+Programming Modes
+=================
+
+Supported configuration files are bitfiles `*.bit` and it's ASCII equivalents `*.cfg`.
+
+JTAG Configuration
+------------------
+
+Performs an active hardware reset and writes the configuration into the FPGA latches via JTAG. The configuration mode pins CFG_MD[3:0] must be set to 0xF0 (JTAG).
+
+* Program using Evaluation Board:
+
+    openFPGALoader -b gatemate_evb_jtag <bitfile>.cfg.bit
+
+* Program using Programmer Cable:
+
+    openFPGALoader -c gatemate_pgm <bitfile>.cfg.bit
+
+SPI Configuration
+-----------------
+
+Performs an active hardware reset and writes the configuration into the FPGA latches via SPI. The configuration mode pins CFG_MD[3:0] must be set to 0x40 (SPI passive).
+
+* Program using Evaluation Board:
+
+    openFPGALoader -b gatemate_evb_spi <bitfile>.cfg.bit
+
+* Program using Programmer Cable:
+
+    openFPGALoader -b gatemate_pgm_spi <bitfile>.cfg.bit
+
+JTAG Flash Access
+-----------------
+
+It is possible to access external flashes via the internal JTAG-SPI-bypass. The configuration mode pins CFG_MD[3:0] must be set to 0xF0 (JTAG). Note that the FPGA will not start automatically.
+
+* Write to flash using Evaluation Board:
+
+    openFPGALoader -b gatemate_evb_jtag <bitfile>.cfg.bit
+
+* Write to flash using Programmer Cable:
+
+    openFPGALoader -c gatemate_pgm -f <bitfile>.cfg.bit
+
+The `offset` parameter can be used to store data at any point in the flash, e.g.:
+
+    openFPGALoader -b gatemate_evb_jtag -o <offset> <bitfile>.cfg.bit
+
+SPI Flash Access
+----------------
+
+If the programming device and FPGA share the same SPI signals, it is possible to hold the FPGA in reset and write data to the flash. The configuration mode can be set as desired. If the FPGA should start from the external memory after reset, the configuration mode pins CFG_MD[3:0] set to 0x00 (SPI active).
+
+* Write to flash using Evaluation Board:
+
+    openFPGALoader -b gatemate_evb_spi -f <bitfile>.cfg.bit
+
+* Write to flash using Programmer Cable:
+
+    openFPGALoader -b gatemate_pgm_spi -f <bitfile>.cfg.bit
+
+The `offset` parameter can be used to store data at any point in the flash, e.g.:
+
+    openFPGALoader -b gatemate_evb_spi -o <offset> <bitfile>.cfg.bit