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5184 Commits

Author SHA1 Message Date
aWZHY0yQH81uOYvH f9352eef10
Merge 8f3adb7aed into 68c1acd80a 2026-07-30 11:37:02 -04:00
Jonas K. 68c1acd80a fabulous: move timing-arc helpers to bel_timing.cc 
Extract TimingPredicate/BelTimingArc and the parse/eval/apply timing
helpers out of fabulous.cc into bel_timing.cc/h.
 2026-07-29 15:20:52 +02:00
Jonas K. ef6931f440 fabulous: add generic way to set BEL timings and placer/router tunables 
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).

Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).

A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing

bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.

A few cosmetics and comments added.
 2026-07-29 15:20:52 +02:00
Lunaphied 00376b6b0d qt: remove qt5 as it's no longer relevant and clean up some warnings 2026-07-28 19:09:50 +02:00
Miodrag Milanovic 77e1f19f21 gatemate: fixed test assert 2026-07-27 14:52:21 +02:00
gatecat bf63271fe7 ice40: Allow disablement of CE global promotion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-27 11:32:18 +02:00
gatecat a6a6afa827 ice40: Add noglobal attribute and raise promotion threshold 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-27 11:32:18 +02:00
gitRaiku 498f0422cd himbaechel: Merge all test entrypoints into one 
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.

Signed-off-by: gitRaiku <raraiku@proton.me>
 2026-07-27 11:01:32 +02:00
gatecat bf80306e97 nexus: Fix OSHX primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-27 10:52:12 +02:00
Jasper Homann fb95bb8ea1
gatemate: Fix DFF pin names when packing mult p registers (#1755) 2026-07-24 14:06:38 +01:00
gatecat a7b62d7cb8 nexus: Fix memory corruption due to rehash 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-24 13:52:18 +02:00
gatecat da46844ca6 nexus: Fix slow routing around DQSBUFs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-22 14:03:42 +02:00
gatecat f8097c3127 nexus: Initial improvements to edge clock routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-22 13:55:15 +02:00
gatecat c2cbdc7efa nexus: Initial support for DDR3 memory interfaces 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-21 17:58:52 +02:00
gatecat ddc6c8c8b9 nexus: Place ECLK bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-19 10:46:49 +02:00
gatecat 5eddc52881 nexus: Add other IODDR modes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 14:11:24 +02:00
gatecat 02d57cfaa1 nexus: Add mapping for IDDRX2 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 13:50:27 +02:00
gatecat 452e75bad6 nexus: Add a mapping for ODDRX2 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 13:35:13 +02:00
gatecat ab65039755 nexus: Add ECLK bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 13:09:37 +02:00
gatecat 60ee033cca ci: Bump prjoxide version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 12:24:36 +02:00
gatecat 1831ce9510 nexus: Add DQS routing to BBA 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 11:45:24 +02:00
gatecat 7c667eeba3 ecp5: Prioritise ECLK usage when placing PLLs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-17 12:27:24 +02:00
gatecat 8624a48bcf ecp5: Make fabric routed ECLK an error 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-17 12:27:24 +02:00
gatecat 261152be8a ecp5: IDDRX2F has ALIGNWD too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-14 14:53:17 +02:00
Lofty 4c72cee9ee
gatemate, ng-ultra: add micko and I as code owners (#1747) 2026-07-12 12:43:35 +02:00
gatecat fc9e96a6e6 python: Fix binding for getNetinfoRouteDelay 
Fixes #1744

Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-12 11:39:41 +02:00
Michael Offel 9f441ba455
fix association of BRAM port to clock in SDP mode (#1746) 
Co-authored-by: MiO <mio@synogate.com>
 2026-07-12 11:29:43 +02:00
gatecat 2b560ad0cc clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-06-19 09:13:08 +02:00
mrcmry fae2fb4dac
gatemate: improve PLL->BUFG error message (#1739) 
When a PLL output is connected to a BUFG, it can only be connected to it.

The message is improved in mentioning it and listing all ports connected and the pll name.

This simplify debug.
 2026-06-19 08:45:32 +02:00
gatecat 57682fe537 static: Respect region constraints 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-06-17 13:19:51 +02:00
YRabbit 175787b2f0
Gowin. BUGFIX. Alu optimization. (#1736) 
Adding freeing of the addition/subtraction mode switch PIP.

We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.

LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.

Addresses https://github.com/YosysHQ/apicula/issues/514

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-06-17 08:48:25 +02:00
mrcmry 2dfdba6efc
gatemate: add default values to vopt descriptions (#1733) 2026-06-13 10:57:03 +02:00
Rowan Goemans 32324500c4
gatemate: Fix blockram edge inversion lookup (#1731) 2026-06-05 12:26:25 +02:00
gatecat 885b71e53d gatemate: Extra error check for CLK1 strategy 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-06-02 12:13:09 +02:00
William D. Jones 3a3b273f06
Explicitly use ANSI versions of Windows functions, due to changes in Qt6 Unicode behavior. (#1727) 2026-05-22 16:21:51 +02:00
William D. Jones ee605e2b18
Fix windows.h being included from within a namespace, which is UB. (#1726) 2026-05-21 10:55:24 +02:00
gatecat 48c70978b3 static: Fix crash when no placeable cells 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-20 10:51:55 +02:00
gatecat d5b1068b29 ice40: Static config tweaks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-20 10:48:59 +02:00
Michael Offel 2894e53934
fix visual studio build (#1722) 
* fix visual studio build
add natural share path after build on visual studio

* fix cmake syntax

---------

Co-authored-by: MiO <mio@synogate.com>
 2026-05-15 10:27:07 +02:00
Patrick Urban 2669f0d932 gatemate: fix OUT3/GPIO_EN inversion 2026-05-12 17:54:49 +02:00
gatecat 8b7dbbedd1 static: Lower start penalty 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-11 13:17:44 +02:00
gatecat 36595c5486 static: Disable dark nodes for now 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-11 12:28:44 +02:00
gatecat 68fb8c0d4c static: Fix spacer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-11 12:28:44 +02:00
Catherine 2622bbfcda WASI: fix thread presence detection. 2026-05-10 13:49:45 +01:00
gatecat 9cb5fc6428 static: Use centroid as position 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-06 12:32:24 +02:00
gatecat 516f6874a6 static: Compute a 'dense' placement grid to avoid excess dark nodes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-06 11:55:36 +02:00
gatecat ec87cdcc80 xilinx: Better model how LUTs pack for static 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-06 11:27:52 +02:00
gatecat fc18d9c1e8 xilinx: Tweaks to static config 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-06 11:19:25 +02:00
gatecat c4cbc3ff88 static: Log legalisation displacement per group 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-06 08:29:47 +02:00
gatecat 6fffc4d2c7 static: Fix offset when aligning macros 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-05-06 07:59:27 +02:00