* Add bridge support
* Use bridge only if CPE is unused
* do not use CPE_MULT for MUX routing
* Fixed and documented
* delay for CPE_BRIDGE
* Convert bridge pips into bels
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
* recursively reassign bridges
* reconnect cell ports to new nets
* handle inversion bits
* sort data in output for easier compare
* one to be removed after testing
* debug message
* Remove need for notifyPipChange
* use same logic for detecting bridge pips
* make sure that the pip used is the one assigned
* one wire may feed multiple ports
* remove #if
* clean up wire binding
* add debugging
* fix
* clangformat
* put back to error
* use tile instead of getting name out of bel/pip
* bump chipdb
* adressing review comments
* Addressed last one
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Very rarely (about once a year), the dedicated clock router would
malfunction, issuing an incorrect route.
The reason turned out to be the so-called gate wires to the global clock
wire system from the logic. Among the PIPs for which these wires are
sinks, there are PIPs where the sources are also clock wires.
This leads to the possibility of feeding the clock signal back into the
gate and again into the global clock MUX.
If handled carelessly, this can lead to a complete loop.
But the loop option itself is particularly useful in the case of DCS
(dynamic clock selection) - the fact is that because these primitives
have four clock inputs and each of them could theoretically address all
56 clock sources, but in practice there are not enough wires and the DCS
inputs cannot serve as sinks for all clock sources.
The simplest solution (and the one that currently works) is to use the
gate to re-enter the clock system, but this time changing the clock
source.
This commit explicitly marks wires as gates and removes the possibility
of looping (however unlikely it may be) where a loop is not needed.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A programmable on-chip crystal oscillator has been implemented for the
GW5A series.
A critical innovation in this series was the change in the nature of the
OSC output pin—it now belongs to the clock wires, and therefore the
routes must be made with a special global router, as there is no
possibility of using routing through general-purpose PIPs.
At the same time, we are transferring the outputs of all previous
generations of OSC to potential clock wires. At the moment, this will
not affect the way they are routed - they will still end up as segments
as before, but in the future we may optimize the mechanism.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Optimize ALU wiring
Interestingly, although VCC and GND sources are present in each cell,
they cannot be connected directly to all LUT inputs. Instead, additional
PIPs are used.
A very simple ALU optimization: once we detect that one of the inputs is
a constant, we modify the main LUT that describes the ALU function so
that this primitive input is ignored, and then disconnect it from the
network, freeing up the PIP.
For example (unrealistic, since a real ALU LUT has a larger size and
service bits in the middle, etc.), the addition function of A and B when
A = 1 is converted from the general case (A isn't a constant and B isn't a
constant) to a special case:
0110 -> 0011
The renaming of ALU ports for ADD and SUB modes has also been
removed—this has already been done in the chip database as a fixed
change to the ALU LUT.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix the style.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The LUTRAM mode is added to all supported chips at once.
This is essentially an alias for LUT4, so the packaging is also moved
before searching for LUT-DFF pairs for possible optimization.
In addition to being the only LUTRAM mode in the GW5A series, the
addition of ROM16 eliminates the need to manually rename the primitive
and its pins when working with files generated by Gowin IDE - a similar
situation occurred with INV, which is essentially LUT1.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The ALUs in the GW5A series have undergone changes compared to previous
chips.
The most significant change is the appearance of an input MUX for
carry — it is now possible to switch between VCC, GND, and COUT of the
previous ALU, as well as generate carry in logic.
The granularity of resource allocation for ALUs has also changed — it is
now possible to use each half of a slice independently for ALUs.
Not all new features are reflected in this commit:
- since there is one CIN MUX for every six ALUs and it only works for
ALUs with index 0, the new granularity is not very useful: the head of
the chain can only be placed in the zero ALU. It is possible to gain one
LUT by allocating ALUs in odd numbers, but we will leave that for the
future.
- using CIN MUX to generate carry in logic is interesting, but we have
not yet been able to get the vendor IDE to generate such a
configuration to figure out which wires are used, so for now we are
leaving the old behavior in logic with the allocation of a specialized
head ALU.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Lofty
Miodrag Milanovic
myrtle
YRabbit