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add PLL delays

This commit is contained in:
Miodrag Milanovic 2025-09-12 10:52:54 +02:00
parent f24630c02b
commit 2823ea385a
1 changed files with 4 additions and 0 deletions
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4
himbaechel/uarch/gatemate/delay.cc
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@ -157,6 +157,10 @@ bool GateMateImpl::getCellDelay(const CellInfo *cell, IdString fromPort, IdStrin
return get_delay_from_tmg_db(ctx->idf("timing_glbout_%s_%s", fromPort.c_str(ctx), toPort.c_str(ctx)), delay);
} else if (cell->type.in(id_RAM, id_RAM_HALF)) {
return false;
} else if (cell->type.in(id_PLL)) {
if (fromPort.in(id_CLK_REF, id_USR_CLK_REF) && toPort.in(id_CLK0, id_CLK90, id_CLK180, id_CLK270))
return get_delay_from_tmg_db(ctx->id("timing_pll_clk_ref_i_clk_core0_o"), delay);
return false;
}
return false;
}