mirror of https://github.com/YosysHQ/nextpnr.git
gatemate: add missing RAM port mapping
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parent
52254dca35
commit
2b203d21ae
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@ -221,6 +221,15 @@ void GateMatePacker::pack_ram_cell(CellInfo &ci, CellInfo *cell, int num, bool i
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rename_or_move(cell, &ci, id_B_EN, ctx->idf("ENB[%d]", index));
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rename_or_move(cell, &ci, id_A_WE, ctx->idf("GLWEA[%d]", index));
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rename_or_move(cell, &ci, id_B_WE, ctx->idf("GLWEB[%d]", index));
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if (is_split) {
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rename_or_move(cell, &ci, id_ECC_1B_ERR, ctx->idf("ECC1B_ERRA[%d]", index));
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rename_or_move(cell, &ci, id_ECC_2B_ERR, ctx->idf("ECC2B_ERRA[%d]", index));
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} else {
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rename_or_move(cell, &ci, id_A_ECC_1B_ERR, ctx->idf("ECC1B_ERRA[%d]", index));
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rename_or_move(cell, &ci, id_B_ECC_1B_ERR, ctx->idf("ECC1B_ERRB[%d]", index));
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rename_or_move(cell, &ci, id_A_ECC_2B_ERR, ctx->idf("ECC2B_ERRA[%d]", index));
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rename_or_move(cell, &ci, id_B_ECC_2B_ERR, ctx->idf("ECC2B_ERRB[%d]", index));
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}
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int items = is_split ? 20 : 40;
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for (int i = 0; i < items; i++) {
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rename_or_move(cell, &ci, ctx->idf("A_BM[%d]", i), ctx->idf("WEA[%d]", i + num * 20));
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@ -415,6 +424,8 @@ void GateMatePacker::pack_ram()
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log_error("DYN_STAT_SELECT must be 0 or 1.\n");
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if (dyn_stat_select != 0 && ram_mode == 1)
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log_error("Dynamic FIFO offset configuration is not supported in SDP mode.\n");
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if (dyn_stat_select != 0)
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log_error("Dynamic FIFO offset configuration is currently not supported.\n");
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ci.params[id_RAM_cfg_dyn_stat_select] = Property(dyn_stat_select << 1, 2);
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ci.params[id_RAM_cfg_almost_empty_offset] =
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Property(int_or_default(ci.params, id_F_ALMOST_EMPTY_OFFSET, 0), 15);
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@ -453,9 +464,12 @@ void GateMatePacker::pack_ram()
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}
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if (is_fifo) {
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for (int i = 0; i < 15; i++) {
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ci.disconnectPort(ctx->idf("F_ALMOST_EMPTY_OFFSET[%d]", i));
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ci.disconnectPort(ctx->idf("F_ALMOST_FULL_OFFSET[%d]", i));
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int dyn_stat_select = int_or_default(ci.params, id_DYN_STAT_SELECT, 0);
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if (dyn_stat_select == 0) {
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for (int i = 0; i < 15; i++) {
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ci.disconnectPort(ctx->idf("F_ALMOST_EMPTY_OFFSET[%d]", i));
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ci.disconnectPort(ctx->idf("F_ALMOST_FULL_OFFSET[%d]", i));
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}
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}
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ci.renamePort(id_F_EMPTY, ctx->id("F_EMPTY[0]"));
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move_ram_i(&ci, ctx->id("F_EMPTY[0]"));
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@ -473,6 +487,14 @@ void GateMatePacker::pack_ram()
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ci.renamePort(id_F_RST_N, ctx->id("F_RSTN"));
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move_ram_o(&ci, ctx->id("F_RSTN"));
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for (int i = 0; i < 15; i++) {
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ci.renamePort(ctx->idf("F_RD_PTR[%d]", i), ctx->idf("FRD_ADDR[%d]", i));
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move_ram_i(&ci, ctx->idf("FRD_ADDR[%d]", i));
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ci.renamePort(ctx->idf("F_WR_PTR[%d]", i), ctx->idf("FWR_ADDR[%d]", i));
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move_ram_i(&ci, ctx->idf("FWR_ADDR[%d]", i));
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}
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}
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}
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flush_cells();
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