mirror of https://github.com/YosysHQ/nextpnr.git
proper parameter check
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parent
485def603a
commit
0412ef7144
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@ -303,7 +303,7 @@ void GateMatePacker::remove_clocking()
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flush_cells();
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}
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static const char *fpga_mode_to_str(int mode)
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static const char *timing_mode_to_str(int mode)
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{
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switch (mode) {
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case 1:
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@ -444,9 +444,9 @@ void GateMatePacker::pack_pll()
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log_error("Unknown PERF_MD parameter value '%s' for cell %s.\n", mode.c_str(), ci.name.c_str(ctx));
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}
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if (perf_md != uarch->fpga_mode)
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log_warning("PLL '%s' mode is '%s' but FPGA mode is '%s'.\n", ci.name.c_str(ctx),
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fpga_mode_to_str(perf_md), fpga_mode_to_str(uarch->fpga_mode));
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if (perf_md != uarch->timing_mode)
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log_warning("PLL '%s' timing mode is '%s' but FPGA timing mode is '%s'.\n", ci.name.c_str(ctx),
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timing_mode_to_str(perf_md), timing_mode_to_str(uarch->timing_mode));
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double ref_clk = double_or_default(ci.params, id_REF_CLK, 0.0);
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if (ref_clk <= 0 || ref_clk > 125)
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