pack_lutffs constrains an FF into the same slice position as the LUT
driving its D input. When that driver is an SRL or LUTRAM cell it has
a CLK of its own: the slice write clock. A slice has a single CLK
input per half, so the placement validity check
(xc7_logic_tile_valid) rejects any slice where the FF clock and the
memory write clock differ in net or polarity.
Pairing such an FF anyway creates a relatively-constrained cluster
that is invalid at every bel on the device; the placer's strict
legalisation phase then spins forever trying to place it (observed as
a static-placer hang on a design clocking an SRL and its capture FF
from different clocks).
Only pair the FF when the driving cell either has no CLK or shares
the FF's clock net and IS_CLK_INVERTED polarity.
Hardware-verified on xc7a100t as part of a MEGA65 core port that
previously hung in placement.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).
Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).
A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing
bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.
A few cosmetics and comments added.
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.
Signed-off-by: gitRaiku <raraiku@proton.me>
When a PLL output is connected to a BUFG, it can only be connected to it.
The message is improved in mentioning it and listing all ports connected and the pll name.
This simplify debug.
Adding freeing of the addition/subtraction mode switch PIP.
We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.
LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.
Addresses https://github.com/YosysHQ/apicula/issues/514
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Joris van Zwieten
Jonas K.
Lunaphied
Miodrag Milanovic
gatecat
gitRaiku
Jasper Homann
Lofty
Michael Offel
mrcmry
YRabbit
Rowan Goemans
William D. Jones
Patrick Urban
Catherine