* fabulous: report port as unconstrained unless BEL attr set
Signed-off-by: Leo Moser <leomoser99@gmail.com>
* fabulous: only create global clock if needed
Signed-off-by: Leo Moser <leomoser99@gmail.com>
---------
Signed-off-by: Leo Moser <leomoser99@gmail.com>
This primitive occupies one DSP block entirely and can be connected into
complex chains both by arguments (shifting operands from SOA to SIA) and
by results (CASO->CASI cascades).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: add CCF floorplanning parser
* apply constraints
* cleanup
* print detected region and error if not found
* Add wildcard matching
* Validate placebox and use official coordinate system
* Fix some messages
* gatemate: improve mode arg error message
* gatemate: fix initial capitals and periods in log_*() messages
* gatemate: replace operation -> performance for mode in help and log_*()
This is the term used both in the datasheet and the primitive library PDF.
* gatemate: add alternate clock routes
* use additional pins
* Fix clock router and timings
* Fix DDR nets
* Test passtrough concept
* remove not used variable
* wip
* handle pip masks
* Cleanup
* create CPE_CPLINES cells and set properties on them
* Fix pip masking
* rough code to break cplines into subnets
* add ports to cell
* mux bridges need cell bel pins too
* fix multiplier output register packing
* remove empty if
* Fix ODDR
* Add options to disable some pips
* Use resources info
* mask field to resource field
* produce valid netlist with propagation netlist at least
* adapt reassign_cplines for internal resource pips
* Handle block and resources
* fix formatting
* It is required to set all mandatory properties now
* arch API for resources
* current progress
* Add option to skip bridges
* perform per-wire resource congestion costing
* Added no-cpe-cp option
* resource bugfix
* comment out spammy debug message
* Fix routing conflicts issues
* allow only some pass trough for clock router
* handle inversion bits for pass signals
* verify inversion before/after assigning bridges
* we care only if there is net
* Revert "we care only if there is net"
This reverts commit 3da2769e31.
* Revert "verify inversion before/after assigning bridges"
This reverts commit 8613ee17c8.
* chipdb version bump
* clangformat
* cleanup
* cleanup
* Initial conversion to GroupId
* Keep group info in pip extra
* Cleanup headers
* Initialize resource efficiently
* Addressing review comments
* improve resource docs
* Make CP lines not use as clocks as default
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
* Gowin. DSP. Implement MULT12x12.
The 5A series DSP differs from previous ones. Many things have been
greatly simplified: there are only two control signals of one type per
cell (2 CLK, 2 CE and 2 RESET), and these signals are now explicitly
specified in the DSP attributes, which makes the automatic assignment
mechanism unnecessary for them.
The DSP occupies 3 cells instead of nine due to the exclusion of 4
low-bit multipliers - now there are only two 12x12. There will naturally
be clusters, but they will be simpler and consist of other primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement MULTADDALU12X12.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
chore: seems like working pcf
feat: add reg support and clean up
chore: add clean up
delay io check and add cell timing min-max delay
fix rebase error
better pcf syntax
add regex support for prohibit command
fix regex and repeat create
fix cell can potentially have no bel
fix IO
chore: clean up
chore: review comment
feat: set pseudo cell loc by wire info
yosys based IO insert
finalise
final finalise
* gowin: Update arch gen to use msgspec chipdb format
Apycula now uses msgspec MessagePack serialization instead of pickle
for the chipdb files. This change:
- Replaces pickle with msgspec via load_chipdb()
- Changes file extension from .pickle to .msgpack.gz
- Updates grid access patterns for new Device structure where
db.grid[y][x] returns ttyp (int) directly, use db[y, x] for Tile
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* Update chipdb extension to .msgpack.xz
Apicula switched from gzip to lzma compression for chipdb files.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
---------
Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>
Only one bit per macro is responsible for the bit width of operands. We
add operand width tracking and do not allow different operands to be
combined in a single macro.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Add GW5AST-138C chip.
The ability to perform P&R for the largest GW5A series chip currently
available has been added, which has its own characteristics:
- the need to invert pin function configuration signals - these
signals are not part of the design, but are nextpnr command line
keys for specifying the activation of alternative pin functions such as
I2C;
- some clock PIPs are encoded not by fuses, but by applying VCC/GND to
special inputs. This is also not part of the design and is not a
dynamic clock selection primitive - it is simply an addition to the
fuses.
- added check for DFF and SSRAM placement in upper slots - prior to
this chip, SSRAM was not supported and there was no need for this
check.
- since the chip is divided into two parts in terms of the global
clock network, a flag is introduced to indicate which part the wire
belongs to. This is only requested for clock wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix style.
Use C++ type cast.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. BUGFIX. BSRAM SP separation.
The new SP cell must inherit the byte size - 8 or 9 bits.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Byte Enables processing in SP.
Single Port with a data width of 32/36 is internally configured as Dual
Port with 16/18. Even and odd words are processed separately by ports A
and B.
With the advent of byte enable support, it became necessary to switch
these signals differently.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Lofty
myrtle
Leo Moser
YRabbit
Miodrag Milanović
mrcmry
Kelvin Chung
Pepijn de Vos
bwisn
Patrick Urban
Darren Kulp
Robert Ward