mirror of https://github.com/YosysHQ/nextpnr.git
Msgspec serialization (#1640)
* gowin: Update arch gen to use msgspec chipdb format Apycula now uses msgspec MessagePack serialization instead of pickle for the chipdb files. This change: - Replaces pickle with msgspec via load_chipdb() - Changes file extension from .pickle to .msgpack.gz - Updates grid access patterns for new Device structure where db.grid[y][x] returns ttyp (int) directly, use db[y, x] for Tile Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com> * Update chipdb extension to .msgpack.xz Apicula switched from gzip to lzma compression for chipdb files. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> --------- Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>
This commit is contained in:
Pepijn de Vos
GitHub
parent
2a8bab976d
commit
06ae973aa8
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@ -2,7 +2,6 @@ from os import path
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import sys
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import importlib.resources
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import pickle
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import gzip
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import re
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import argparse
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@ -10,6 +9,7 @@ import argparse
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sys.path.append(path.join(path.dirname(__file__), "../.."))
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from himbaechel_dbgen.chip import *
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from apycula import chipdb
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from apycula.chipdb import load_chipdb
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# Bel flags
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BEL_FLAG_SIMPLE_IO = 0x100
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@ -547,7 +547,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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return "LW_TAP"
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return ""
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for dst, srcs in db.grid[y][x].pips.items():
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for dst, srcs in db[y, x].pips.items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, get_wire_type(dst))
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for src in srcs.keys():
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@ -561,7 +561,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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# clock wires
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# always mark clock wires with location flag
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for dst, srcs in db.grid[y][x].clock_pips.items():
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for dst, srcs in db[y, x].clock_pips.items():
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if not tt.has_wire(dst):
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wire = tt.create_wire(dst, "GLOBAL_CLK")
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if hasattr(db, "last_top_row") and y > db.last_top_row:
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@ -597,7 +597,7 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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"CLKDIV_HCLK1_SECT1": CLKDIV_3_Z
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}
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for bel_name, bel_props in db.grid[y][x].bels.items():
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for bel_name, bel_props in db[y, x].bels.items():
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if (bel_name not in hclk_bel_zs):
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continue
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this_portmap = bel_props.portmap
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@ -644,7 +644,7 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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for func, desc in db.extra_func[(y, x)].items():
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if func == 'osc':
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osc_type = desc['type']
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portmap = db.grid[y][x].bels[osc_type].portmap
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portmap = db[y, x].bels[osc_type].portmap
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for port, wire in portmap.items():
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if not tt.has_wire(wire):
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tt.create_wire(wire, port)
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@ -743,7 +743,7 @@ def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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for io_type, z in {('IDES16', IDES16_Z), ('OSER16', OSER16_Z)}:
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bel = tt.create_bel(io_type, io_type, z = z)
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portmap = db.grid[y][x].bels[io_type].portmap
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portmap = db[y, x].bels[io_type].portmap
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for port, wire in portmap.items():
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if port == 'FCLK': # XXX compatibility
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wire = 'FCLKA'
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@ -949,10 +949,10 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
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for i in range(rng):
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name = 'IOB' + 'ABCDEFGHIJ'[i]
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# XXX some IOBs excluded from generic chipdb for some reason
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if name not in db.grid[y][x].bels:
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if name not in db[y, x].bels:
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continue
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# wires
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portmap = db.grid[y][x].bels[name].portmap
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portmap = db[y, x].bels[name].portmap
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tt.create_wire(portmap['I'], "IO_I")
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tt.create_wire(portmap['O'], "IO_O")
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tt.create_wire(portmap['OE'], "IO_OE")
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@ -976,11 +976,11 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc:
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tt.add_bel_pin(io, "BOTTOM_IO_PORT_B", portmap['BOTTOM_IO_PORT_B'], PinType.INPUT)
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# create IOLOGIC bels if any
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for idx, name in {(IOLOGICA_Z, 'IOLOGICA'), (IOLOGICA_Z + 1, 'IOLOGICB')}:
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if name not in db.grid[y][x].bels:
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if name not in db[y, x].bels:
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continue
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for off, io_type in {(0, 'O'), (2, 'I')}:
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iol = tt.create_bel(f"{name}{io_type}", f"IOLOGIC{io_type}", z = idx + off)
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for port, wire in db.grid[y][x].bels[name].portmap.items():
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for port, wire in db[y, x].bels[name].portmap.items():
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if port == 'FCLK': # XXX compatibility
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wire = f'FCLK{name[-1]}'
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if not tt.has_wire(wire):
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@ -1133,7 +1133,7 @@ def create_bsram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
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tt = chip.create_tile_type(tiletype)
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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portmap = db.grid[y][x].bels['BSRAM'].portmap
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portmap = db[y, x].bels['BSRAM'].portmap
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bsram = tt.create_bel("BSRAM", "BSRAM", z = BSRAM_Z)
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@ -1167,21 +1167,21 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# create big DSP
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belname = f'DSP'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "DSP", DSP_Z)
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dsp.flags = BEL_FLAG_HIDDEN
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# create DSP macros
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for idx in range(2):
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belname = f'DSP{idx}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "DSP", eval(f'DSP_{idx}_Z'))
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dsp.flags = BEL_FLAG_HIDDEN
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# create pre-adders
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for mac, idx in [(mac, idx) for mac in range(2) for idx in range(4)]:
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belname = f'PADD9{mac}{idx}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "PADD9", eval(f'PADD9_{mac}_{idx}_Z'))
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add_port_wire(tt, dsp, portmap, "ADDSUB", "DSP_I", PinType.INPUT)
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@ -1200,7 +1200,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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for mac, idx in [(mac, idx) for mac in range(2) for idx in range(2)]:
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belname = f'PADD18{mac}{idx}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "PADD18", eval(f'PADD18_{mac}_{idx}_Z'))
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add_port_wire(tt, dsp, portmap, "ADDSUB", "DSP_I", PinType.INPUT)
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@ -1221,7 +1221,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# mult 9x9
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for mac, idx in [(mac, idx) for mac in range(2) for idx in range(4)]:
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belname = f'MULT9X9{mac}{idx}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "MULT9X9", eval(f'MULT9X9_{mac}_{idx}_Z'))
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for sfx in {'A', 'B'}:
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@ -1239,7 +1239,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# mult 18x18
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for mac, idx in [(mac, idx) for mac in range(2) for idx in range(2)]:
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belname = f'MULT18X18{mac}{idx}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "MULT18X18", eval(f'MULT18X18_{mac}_{idx}_Z'))
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for sfx in {'A', 'B'}:
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@ -1256,14 +1256,14 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# mult 36x36
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belname = 'MULT36X36'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "MULT36X36", MULT36X36_Z)
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# LSB 18x18 multipliers sign ports must be zero
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add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1800'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN0')
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add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1800'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN0')
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add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1801'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN1')
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add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1810'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN1')
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add_port_wire(tt, dsp, db[y, x].bels['MULT18X1800'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN0')
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add_port_wire(tt, dsp, db[y, x].bels['MULT18X1800'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN0')
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add_port_wire(tt, dsp, db[y, x].bels['MULT18X1801'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN1')
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add_port_wire(tt, dsp, db[y, x].bels['MULT18X1810'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN1')
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for i in range(2):
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for sfx in {'A', 'B'}:
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for inp in range(36):
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@ -1280,7 +1280,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# create alus
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for mac in range(2):
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belname = f'ALU54D{mac}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "ALU54D", eval(f'ALU54D_{mac}_Z'))
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for sfx in {'A', 'B'}:
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@ -1301,7 +1301,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# MULTALU18X18
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for mac in range(2):
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belname = f'MULTALU18X18{mac}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "MULTALU18X18", eval(f'MULTALU18X18_{mac}_Z'))
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for i in range(2):
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@ -1326,7 +1326,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# MULTALU36X18
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for mac in range(2):
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belname = f'MULTALU36X18{mac}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "MULTALU36X18", eval(f'MULTALU36X18_{mac}_Z'))
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for i in range(2):
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@ -1350,7 +1350,7 @@ def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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# MULTADDALU18X18
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for mac in range(2):
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belname = f'MULTADDALU18X18{mac}'
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portmap = db.grid[y][x].bels[belname].portmap
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portmap = db[y, x].bels[belname].portmap
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dsp = tt.create_bel(belname, "MULTADDALU18X18", eval(f'MULTADDALU18X18_{mac}_Z'))
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for i in range(2):
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@ -1398,7 +1398,7 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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else:
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pll_name = 'RPLLA'
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bel_type = 'rPLL'
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portmap = db.grid[y][x].bels[pll_name].portmap
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portmap = db[y, x].bels[pll_name].portmap
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pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
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pll.flags = BEL_FLAG_GLOBAL
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for pin, wire in portmap.items():
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@ -1652,8 +1652,8 @@ def main():
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args = parser.parse_args()
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device = args.device
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with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f:
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db = pickle.load(f)
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with importlib.resources.as_file(importlib.resources.files("apycula").joinpath(f"{device}.msgpack.xz")) as chipdb_path:
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db = load_chipdb(chipdb_path)
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chip_flags = 0;
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# XXX compatibility
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@ -1718,7 +1718,7 @@ def main():
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# Setup tile grid
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for x in range(X):
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for y in range(Y):
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ttyp = db.grid[y][x].ttyp
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ttyp = db.grid[y][x]
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if ttyp in logic_tiletypes:
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create_tiletype(create_logic_tiletype, ch, db, x, y, ttyp)
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elif ttyp in ssram_tiletypes:
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