mirror of https://github.com/YosysHQ/nextpnr.git
fabulous: improve pcf implementation, create global clock only if necessary (#1654)
* fabulous: report port as unconstrained unless BEL attr set Signed-off-by: Leo Moser <leomoser99@gmail.com> * fabulous: only create global clock if needed Signed-off-by: Leo Moser <leomoser99@gmail.com> --------- Signed-off-by: Leo Moser <leomoser99@gmail.com>
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Leo Moser
GitHub
parent
eba9764645
commit
50c2ca21a3
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@ -163,8 +163,6 @@ struct FabulousImpl : ViaductAPI
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FabricConfig cfg; // TODO: non-default config
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ViaductHelpers h;
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WireId global_clk_wire;
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std::string fasm_file;
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std::string pcf_file;
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@ -222,6 +220,7 @@ struct FabulousImpl : ViaductAPI
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} else if (bel_type.in(id_InPass4_frame_config, id_OutPass4_frame_config)) {
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WireId clk_wire = get_wire(tile, id_CLK, id_REG_CLK);
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if (ctx->wires.at(clk_wire.index).uphill.empty()) {
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WireId global_clk_wire = get_wire(ctx->id("X0Y0"), id_CLK, id_CLK);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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}
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ctx->addBelInput(bel, id_CLK, clk_wire);
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@ -234,6 +233,7 @@ struct FabulousImpl : ViaductAPI
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} else if (bel_type == id_RegFile_32x4) {
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WireId clk_wire = get_wire(tile, id_CLK, id_REG_CLK);
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ctx->addBelInput(bel, id_CLK, clk_wire);
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WireId global_clk_wire = get_wire(ctx->id("X0Y0"), id_CLK, id_CLK);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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for (parser_view p : ports) {
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IdString port_id = p.to_id(ctx);
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@ -270,6 +270,7 @@ struct FabulousImpl : ViaductAPI
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// TODO: split LC mode, LUT permutation pseudo-switchbox, LUT thru pseudo-pips
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WireId clk_wire = get_wire(tile, ctx->idf("L%s_CLK", idx.c_str(ctx)), id_LUT_CLK);
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ctx->addBelInput(bel, id_CLK, clk_wire);
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WireId global_clk_wire = get_wire(ctx->id("X0Y0"), id_CLK, id_CLK);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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blk_trk->set_bel_type(bel, BelFlags::BLOCK_CLB, BelFlags::FUNC_LC_COMB, loc.z);
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for (parser_view p : ports) {
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@ -303,10 +304,13 @@ struct FabulousImpl : ViaductAPI
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void init_global_clock()
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{
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// TODO: how do we extend this to more complex clocking topologies?
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BelId global_clk_bel =
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ctx->addBel(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_Global_Clock, Loc(0, 0, 0), true, false);
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global_clk_wire = ctx->addWire(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_CLK, 0, 0);
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ctx->addBelOutput(global_clk_bel, id_CLK, global_clk_wire);
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auto found = ctx->wire_by_name.find(IdStringList::concat(ctx->id("X0Y0"), id_CLK));
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if (found != ctx->wire_by_name.end()) {
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BelId global_clk_bel = ctx->addBel(IdStringList::concat(ctx->id("X0Y0"), id_CLK), id_Global_Clock,
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Loc(0, 0, 0), true, false);
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WireId global_clk_wire = get_wire(ctx->id("X0Y0"), id_CLK, id_CLK);
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ctx->addBelOutput(global_clk_bel, id_CLK, global_clk_wire);
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}
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}
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// TODO: this is for legacy fabulous only, the new code path can be a lot simpler
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@ -314,7 +318,6 @@ struct FabulousImpl : ViaductAPI
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{
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std::ifstream in = open_data_rel("/npnroutput/bel.txt");
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CsvParser csv(in);
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init_global_clock();
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while (csv.fetch_next_line()) {
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IdString tile = csv.next_field().to_id(ctx);
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int bel_x = csv.next_field().substr(1).to_int();
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@ -345,6 +348,7 @@ struct FabulousImpl : ViaductAPI
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BelId bel = ctx->addBel(IdStringList::concat(tile, bel_name), bel_type, loc, false, false);
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handle_bel_ports(bel, tile, bel_type, ports);
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}
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init_global_clock();
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postprocess_bels();
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}
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@ -352,7 +356,6 @@ struct FabulousImpl : ViaductAPI
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{
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std::ifstream in = open_data_rel("/.FABulous/bel.v2.txt");
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CsvParser csv(in);
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init_global_clock();
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BelId curr_bel;
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while (csv.fetch_next_line()) {
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IdString cmd = csv.next_field().to_id(ctx);
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@ -386,6 +389,7 @@ struct FabulousImpl : ViaductAPI
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IdStringList bel_name = ctx->getBelName(curr_bel);
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WireId clk_wire = get_wire(bel_name[0], ctx->idf("%s_CLK", bel_name[1].c_str(ctx)), id_REG_CLK);
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ctx->addBelInput(curr_bel, id_CLK, clk_wire);
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WireId global_clk_wire = get_wire(ctx->id("X0Y0"), id_CLK, id_CLK);
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add_pseudo_pip(global_clk_wire, clk_wire, id_global_clock);
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} else if (cmd == id_CFG) {
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// TODO...
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@ -396,6 +400,7 @@ struct FabulousImpl : ViaductAPI
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curr_bel == BelId() ? "<none>" : ctx->nameOfBel(curr_bel));
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}
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}
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init_global_clock();
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postprocess_bels();
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}
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@ -334,8 +334,8 @@ struct FabulousPacker
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auto &ci = *cell.second;
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if (!ci.type.in(ibuf, obuf, iobuf))
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continue;
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log_info("port is unconstrained: %s This pin will be assigned randomly\n", ctx->nameOf(&ci));
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bool found_pad = false;
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bool constrained = false;
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for (auto &port : ci.ports) {
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NetInfo *net = port.second.net;
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if (!net)
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@ -347,6 +347,8 @@ struct FabulousPacker
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if (usr.port != id_PAD)
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log_error("Top-level port '%s' connected to illegal port %s.%s (must be PAD)\n",
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ctx->nameOf(&ci), ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
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if (usr.cell->attrs.count(id_BEL))
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constrained = true;
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if (found_pad)
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log_error("Top-level port '%s' connected to multiple PAD ports (at least %s.%s and %s.%s)\n",
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ctx->nameOf(&ci), ctx->nameOf(usr.cell), ctx->nameOf(usr.port),
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@ -362,6 +364,8 @@ struct FabulousPacker
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if (drv.port != id_PAD)
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log_error("Top-level port '%s' connected to illegal port %s.%s (must be PAD)\n",
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ctx->nameOf(&ci), ctx->nameOf(drv.cell), ctx->nameOf(drv.port));
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if (drv.cell->attrs.count(id_BEL))
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constrained = true;
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if (found_pad)
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log_error("Top-level port '%s' connected to multiple PAD ports (at least %s.%s and %s.%s)\n",
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ctx->nameOf(&ci), ctx->nameOf(drv.cell), ctx->nameOf(drv.port),
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@ -372,6 +376,8 @@ struct FabulousPacker
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if (!found_pad)
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log_error("No IO cell found connected to '%s' via PAD port. Was iopadmap run in Yosys?\n",
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ctx->nameOf(&ci));
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if (!constrained)
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log_info("port is unconstrained: %s This pin will be assigned randomly\n", ctx->nameOf(&ci));
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ci.disconnectPort(id_I);
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ci.disconnectPort(id_O);
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to_remove.push_back(ci.name);
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@ -619,4 +619,4 @@ void fabulous_pcf(Context *ctx, const std::string &filename)
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log_info("Finished applying constraints from '%s'\n", filename.c_str());
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}
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NEXTPNR_NAMESPACE_END
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NEXTPNR_NAMESPACE_END
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