Distributed RAM primitives (RAM32M/RAM64M etc.) carry their per-port
initialisation in parameters named INIT_A..INIT_D, but pack_dram
looked up INITA..INITD. The lookup never matched, so all LUTRAM was
configured with INIT=0 regardless of the design's initial contents.
Fixing the name exposed a second, previously unreachable bug in the
wide (dbits>1) path: the 64-bit INIT slice was converted with
as_bits(), which yields raw bool values rather than the '0'/'1'
characters a Property string requires, producing a corrupt property.
De-interleave the canonical bit string directly (bit k*2+j of the
64-bit INIT is bit j of entry k) and rebuild the Property with
update_intval().
Repro: a RAM32M with a nonzero INIT_A..D readback (WE held low /
driven by a live net); before this change the read data is all-zero.
Hardware-verified on xc7a100t (QMTech Wukong): LUTRAM-based tables in
a MEGA65 core port now read back their initial contents correctly.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).
Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).
A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing
bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.
A few cosmetics and comments added.
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.
Signed-off-by: gitRaiku <raraiku@proton.me>
When a PLL output is connected to a BUFG, it can only be connected to it.
The message is improved in mentioning it and listing all ports connected and the pll name.
This simplify debug.
Adding freeing of the addition/subtraction mode switch PIP.
We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.
LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.
Addresses https://github.com/YosysHQ/apicula/issues/514
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Joris van Zwieten
Jonas K.
Lunaphied
Miodrag Milanovic
gatecat
gitRaiku
Jasper Homann
Lofty
Michael Offel
mrcmry
YRabbit
Rowan Goemans
William D. Jones
Patrick Urban
Catherine