* gatemate: removing recursion in GateMateImpl::reassign_bridges
* gatemate: improving comments in GateMateImpl:reassign_bridges
* gatemate: making naming more consistent, adding comments about the need for recursion removal
Add CLKDIV — a frequency divider with ratios of 1, 2, 3, 3.5, 4,
5, 6, 7, and 8.
A direct, non-switchable connection to CLKDIV2 makes placement more
difficult — we have to account for CLKDIV2’s occupancy for IOLOGIC and,
if necessary, duplicate the cell, as well as create clusters of CLKDIV
and CLKDIV2.
Signed-off-by: YRabbit <[email protected]>
* nix: fix issue with latest apycula being needed and it not being in Nixpkgs stable
* nix: we really should be using the latest version unless a regression happens tbh
* Gowin. Implement GW5A HCLK and CLKDIV2.
HCLK pins have been added for the GW5A series, and the placement of
CLKDIV2 primitives has been updated to account for the specific
characteristics of this chip series.
Signed-off-by: YRabbit <[email protected]>
* Gowin. Fix style.
* Gowin. Fix style.
---------
Signed-off-by: YRabbit <[email protected]>
This fixes a memory issue. When you assign to base_iodelay_rules from itself, the LHS when you do `base_iodelay_rules[id_DELAYA] = base_iodelay_rules[id_DELAYB]`, can cause a heap allocation which possibly invalidates the memory of the RHS.
This was found while running nextpnr under ASAN. It might be useful to add testing under libasan into CI.
* GOWIN. BUGFIX. BSRAM port renaming.
The renumbering of the BSRAM pins has been corrected.
Signed-off-by: YRabbit <[email protected]>
* GOWIN. Comment BSRAM port renaming
Signed-off-by: YRabbit <[email protected]>
---------
Signed-off-by: YRabbit <[email protected]>
* gowin: add DL-series latch cell support
Teach the himbaechel Gowin backend to recognize and place all 12
DL-series latch primitives onto DFF BEL sites. Latches use the CLK
pin for the gate signal and share placement resources with DFFs.
* gowin: convert latches to DFFs with LATCH attribute during packing
Instead of teaching all DFF infrastructure about 12 DL latch types,
pack_latches() converts them to corresponding DFF types early and sets
a LATCH attribute. This attribute is picked up by gowin_pack to set
REGMODE=LATCH instead of FF.
* gowin: exclude latch gate signals from clock buffer promotion
Latch cells are mapped to DFFs with a LATCH attribute, so their gate
signal drives the CLK port. This caused pack_buffered_nets to promote
the gate signal onto a global clock buffer (BUFG), which has different
timing/initialization behavior and caused the first gate transition
to be lost. Skip CLK pins on cells with the LATCH attribute when
checking for clock users.
* gowin: update latch message to be user friendly.
* fix: handle string DRIVE property in pack_io without crashing
The XDC parser stores all set_property values as string Properties,
but pack_io.cc called as_int64() on DRIVE which asserts !is_string.
Rather than converting numeric values to integer Properties in the
XDC parser (which risks breaking properties like LOC that downstream
code reads via to_string()/as_string()), fix the consumption site
in pack_io.cc to convert string values to integers when needed.
* refactor: use int_or_default for DRIVE property parsing
Replace manual is_string/as_int64 branching with int_or_default(),
which already handles both Property types with proper error reporting.
When splitting a carry chain the original COUT -> carry -> CIN
was preserved. This was not routable if the carry chain is split.
Instead now the COUT is wired to a feed out CC2C whose `S0` port
is the start of the new carry chain.
Dual Port has a defective output register. This only manifests itself at
small data widths and only on -C chips.
That is, Tangprimer20k (GW2A-18) works perfectly, while Tangnano20k
(GW2A-18C) stutters. The same story with GW1N-9 and GW1N-9C.
Fortunately, the fix has long been included in nextpnr for SDP memory,
so all that remains is to call the same function for Dual Port.
Signed-off-by: YRabbit <[email protected]>
We are fixing a hardware error - in BYPASS mode, dual port bsram
requires synchronization of CE and OCE signals for some data widths.
We are also getting rid of port renaming in the loop, but not all of
them yet.
Signed-off-by: YRabbit <[email protected]>
The new multiplier is made from two 27x18 units by switching inputs and
creating a cluster connected via CASO->CASI.
A second pass was required to process the multipliers created on the
fly—the processing of DSP cells was separated into a separate function,
which resulted in a large diff, but in reality there were very few
changes.
An important point is that in the 5A series, there is a gap between
adjacent DSPs in one row. There are still SIA/CASI wires, so the DSPs on
either side of the gap are connected, but the distance between them is
greater than usual. We take this fact into account based on the gap
coordinates from the chip database.
Signed-off-by: YRabbit <[email protected]>
* fabulous: report port as unconstrained unless BEL attr set
Signed-off-by: Leo Moser <[email protected]>
* fabulous: only create global clock if needed
Signed-off-by: Leo Moser <[email protected]>
---------
Signed-off-by: Leo Moser <[email protected]>
gatecat
sylefeb
Leo Moser
YRabbit
Lunaphied
jdavidberger
Balint Cristian
mrcmry
Marcel Jung
Miodrag Milanovic
Justin
Marcel Jung
Rowan Goemans