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xilinx: Prohibit IDELMUXE3 route throughs 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2026-03-17 10:34:59 +00:00
parent cd36c9f0d5
commit e652226630
1 changed files with 3 additions and 1 deletions
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4
himbaechel/uarch/xilinx/gen/xilinx_gen.py
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@ -228,7 +228,9 @@ def import_tiletype(ch: Chip, tile: xilinx_device.Tile):
(bel_name == "BDI1MUX" and bel_pin == "DI") or \
(bel_name == "CDI1MUX" and bel_pin == "DI") or \
(bel_name.startswith("TFBUSED")) or \
(bel_name == "OMUX"):
(bel_name == "OMUX") or \
(bel_name == "IDELMUXE3"):
continue
add_pip(lookup_site_wire(site_pip.src_wire()),
lookup_site_wire(site_pip.dst_wire()),