mirror of https://github.com/YosysHQ/nextpnr.git
Improvements to FABulous (#1692)
* fabulous: fix I0mux naming Signed-off-by: Leo Moser <leomoser99@gmail.com> * fabulous: pack more FF types: reset before enable Signed-off-by: Leo Moser <leomoser99@gmail.com> * fabulous: fix block tracking of FABULOUS_LC, improve debug messages, fix masking of 1 Signed-off-by: Leo Moser <leomoser99@gmail.com> * fabulous: add 'corner' argument Signed-off-by: Leo Moser <leomoser99@gmail.com> --------- Signed-off-by: Leo Moser <leomoser99@gmail.com>
This commit is contained in:
Leo Moser
GitHub
parent
ae7843fbf0
commit
ca74f47c3f
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@ -45,7 +45,12 @@ struct ControlSetConfig
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*/
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std::vector<route_mask_t> routing; // default 1 shared between all
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bool have_signal = true;
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int can_mask = -1;
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enum MaskType
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{
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MASK_NONE = -1,
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MASK_ZERO = 0,
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MASK_ONE = 1
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} can_mask = MaskType::MASK_NONE;
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bool can_invert = false;
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};
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@ -53,6 +53,8 @@ struct FabulousImpl : ViaductAPI
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cfg.clb.lut_k = std::stoi(a.second);
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else if (a.first == "pcf")
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pcf_file = a.second;
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else if (a.first == "corner")
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corner = a.second;
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else
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log_error("unrecognised fabulous option '%s'\n", a.first.c_str());
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}
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@ -87,16 +89,16 @@ struct FabulousImpl : ViaductAPI
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{
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// TODO: loading from file or something
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uint64_t default_routing = (1ULL << (cfg.clb.lc_per_clb * cfg.clb.ff_per_lc)) - 1;
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auto setup_cfg = [&](ControlSetConfig &ctrl, int mask) {
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auto setup_cfg = [&](ControlSetConfig &ctrl, ControlSetConfig::MaskType mask) {
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ctrl.routing.clear();
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ctrl.routing.push_back(default_routing);
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ctrl.can_mask = mask;
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ctrl.can_invert = false;
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};
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setup_cfg(cfg.clb.clk, -1);
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setup_cfg(cfg.clb.en, 1);
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setup_cfg(cfg.clb.sr, 0);
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setup_cfg(cfg.clb.clk, ControlSetConfig::MaskType::MASK_NONE); // clk can not be masked
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setup_cfg(cfg.clb.en, ControlSetConfig::MaskType::MASK_ONE); // en can be masked with 1
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setup_cfg(cfg.clb.sr, ControlSetConfig::MaskType::MASK_ZERO); // sr can be masked with 0
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}
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void update_cell_timing(Context *ctx)
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@ -154,9 +156,38 @@ struct FabulousImpl : ViaductAPI
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assign_cell_info();
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update_cell_timing(ctx);
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}
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void postPlace() override
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{
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if (ctx->debug) {
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log_info("================== Final Placement ==================\n");
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for (auto &cell : ctx->cells) {
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auto ci = cell.second.get();
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if (ci->bel != BelId()) {
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log_info("%s: %s\n", ctx->nameOfBel(ci->bel), ctx->nameOf(ci));
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if (ctx->getBelType(ci->bel).in(id_FABULOUS_LC)) {
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for (IdString port : {id_CLK, id_SR, id_EN}) {
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if (ci->ports.count(port)) {
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WireId wire = ctx->getBelPinWire(ci->bel, port);
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PortInfo pi = ci->ports[port];
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if (pi.net) {
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log_info("- %s/%s: %s\n", ctx->getWireName(wire)[0].c_str(ctx),
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ctx->getWireName(wire)[1].c_str(ctx), pi.net->name.c_str(ctx));
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}
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}
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}
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}
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} else {
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log_info("unknown: %s\n", ctx->nameOf(ci));
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}
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}
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log_break();
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}
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}
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bool isBelLocationValid(BelId bel, bool explain_invalid) const override
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{
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return blk_trk->check_validity(bel, cfg, cell_tags);
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return blk_trk->check_validity(bel, cfg, cell_tags, explain_invalid);
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}
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private:
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@ -167,6 +198,8 @@ struct FabulousImpl : ViaductAPI
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std::string pcf_file;
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std::string corner;
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std::unique_ptr<BlockTracker> blk_trk;
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std::string get_env_var(const std::string &name, const std::string &prompt = "")
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@ -318,6 +351,7 @@ struct FabulousImpl : ViaductAPI
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// TODO: this is for legacy fabulous only, the new code path can be a lot simpler
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void init_bels_v1()
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{
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log_info("Reading BELs file: /npnroutput/bel.txt\n");
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std::ifstream in = open_data_rel("/npnroutput/bel.txt");
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CsvParser csv(in);
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while (csv.fetch_next_line()) {
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@ -357,6 +391,7 @@ struct FabulousImpl : ViaductAPI
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void init_bels_v2()
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{
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log_info("Reading BELs file: /.FABulous/bel.v2.txt\n");
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std::ifstream in = open_data_rel("/.FABulous/bel.v2.txt");
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CsvParser csv(in);
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BelId curr_bel;
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@ -382,6 +417,11 @@ struct FabulousImpl : ViaductAPI
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Loc loc = tile_loc(tile);
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curr_bel = ctx->addBel(IdStringList::concat(tile, bel_name), bel_type, Loc(loc.x, loc.y, bel_z), false,
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false);
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// add FABULOUS_LC to the block tracker to check the control set
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if (bel_type.in(id_FABULOUS_LC)) {
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blk_trk->set_bel_type(curr_bel, BelFlags::BLOCK_CLB, BelFlags::FUNC_LC_COMB, bel_z);
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}
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} else if (cmd.in(id_I, id_O)) {
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IdString port = csv.next_field().to_id(ctx);
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auto wire_name = csv.next_field().split('.');
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@ -476,7 +516,18 @@ struct FabulousImpl : ViaductAPI
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int max_x = 0, max_y = 0;
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void init_pips()
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{
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std::ifstream in = open_data_rel(is_new_fab ? "/.FABulous/pips.txt" : "/npnroutput/pips.txt");
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// PIP file selection
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std::string pips_file = "/npnroutput/pips.txt";
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if (is_new_fab) {
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if (!corner.empty()) {
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pips_file = stringf("/.FABulous/pips.%s.txt", corner.c_str());
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} else {
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pips_file = "/.FABulous/pips.txt";
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}
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}
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log_info("Reading PIPs file: %s\n", pips_file.c_str());
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std::ifstream in = open_data_rel(pips_file);
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CsvParser csv(in);
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while (csv.fetch_next_line()) {
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IdString src_tile = csv.next_field().to_id(ctx);
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@ -170,7 +170,7 @@ struct FabFasmWriter
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unsigned width = 1U << cfg.clb.lut_k;
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write_int_vector(stringf("INIT[%d:0]", width - 1), init, width); // todo lut depermute and thru
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if (bool_or_default(lc->params, id_I0MUX, false))
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add_feature("IOmux"); // typo in FABulous?
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add_feature("I0mux");
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}
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if (lc->type == id_FABULOUS_LC) {
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write_bool(lc, "FF");
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@ -97,16 +97,44 @@ struct FabulousPacker
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void prepare_ffs()
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{
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// The following LUTFF are supported:
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// Enable before reset: LUTFF_[N][E][AS|AR|SS|SR]
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// Reset before enable: LUTFF_[N][AS|AR|SS|SR][E]
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// Note: A simple LUTFF will have SR and EN disconnected,
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// ensure that the default value is SR=0 and EN=1.
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// N ... clock inversion (NEG_CLK=1)
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// E ... clock enable (EN port)
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// AS ... async set (SET_NORESET=1, ASYNC_SR=1)
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// AR ... async reset (SET_NORESET=0, ASYNC_SR=1)
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// SS ... sync set (SET_NORESET=1, ASYNC_SR=0)
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// SR ... sync reset (SET_NORESET=0, ASYNC_SR=0)
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// The ports of FABULOUS_FF are:
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// - CLK: clock
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// - SR: set/reset
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// - EN: enable
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// The parameters of FABULOUS_FF are:
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// - SET_NORESET: the value to load into the flip-flop when SR=1
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// - ASYNC_SR: used to indicate asynchronous load
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// - NEG_CLK: invert the clock
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// Note: Both ASYNC_SR and NEG_CLK are currently unused by the default FABulous fabric.
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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const std::string &type_str = ci->type.str(ctx);
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if (type_str.size() < 5 || type_str.substr(0, 5) != "LUTFF")
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continue;
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ci->type = id_FABULOUS_FF;
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// parse config string and unify
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size_t idx = 5;
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if (idx < type_str.size() && type_str.at(idx) == '_')
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++idx;
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// clock inversion
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if (idx < type_str.size() && type_str.at(idx) == 'N') {
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ci->params[id_NEG_CLK] = 1;
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@ -114,36 +142,70 @@ struct FabulousPacker
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} else {
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ci->params[id_NEG_CLK] = 0;
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}
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// clock enable
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// clock enable (enable before reset)
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if (idx < type_str.size() && type_str.at(idx) == 'E')
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++idx;
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if (ci->ports.count(id_E))
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ci->renamePort(id_E, id_EN);
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else
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ci->addInput(id_EN); // autocreate emtpy enable port if enable missing or unused
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// sr presence and type
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std::string srt = type_str.substr(idx);
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if (srt == "S") {
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ci->params[id_SET_NORESET] = 1;
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ci->params[id_ASYNC_SR] = 1;
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} else if (srt == "R") {
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ci->params[id_SET_NORESET] = 0;
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ci->params[id_ASYNC_SR] = 1;
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} else if (srt == "SS") {
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// default settings
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ci->params[id_SET_NORESET] = 0;
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ci->params[id_ASYNC_SR] = 0;
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// synchronous set
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if (idx < type_str.size() - 1 && type_str.substr(idx, 2) == "SS") {
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ci->params[id_SET_NORESET] = 1;
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ci->params[id_ASYNC_SR] = 0;
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} else if (srt == "SR" || srt == "") {
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idx += 2;
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}
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// synchronous reset
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if (idx < type_str.size() - 1 && type_str.substr(idx, 2) == "SR") {
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ci->params[id_SET_NORESET] = 0;
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ci->params[id_ASYNC_SR] = 0;
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} else {
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idx += 2;
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}
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// asynchronous set
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if (idx < type_str.size() - 1 && type_str.substr(idx, 2) == "AS") {
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ci->params[id_SET_NORESET] = 1;
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ci->params[id_ASYNC_SR] = 1;
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idx += 2;
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}
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// asynchronous reset
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if (idx < type_str.size() - 1 && type_str.substr(idx, 2) == "AR") {
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ci->params[id_SET_NORESET] = 0;
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ci->params[id_ASYNC_SR] = 1;
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idx += 2;
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}
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// clock enable (reset before enable)
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if (idx < type_str.size() && type_str.at(idx) == 'E')
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++idx;
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// check that we are the end of the string
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if (idx != type_str.size()) {
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log_error("unhandled FF type %s of cell %s\n", type_str.c_str(), ci->name.c_str(ctx));
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NPNR_ASSERT_FALSE("unhandled FF type");
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}
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// Rename S/R ports to SR
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if (ci->ports.count(id_S))
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ci->renamePort(id_S, id_SR);
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else if (ci->ports.count(id_R))
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ci->renamePort(id_R, id_SR);
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// Rename E port to EN
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if (ci->ports.count(id_E))
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ci->renamePort(id_E, id_EN);
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// autocreate empty set/reset port if enable missing or unused
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if (!ci->ports.count(id_SR))
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ci->addInput(id_SR); // autocreate emtpy enable port if enable missing or unused
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ci->addInput(id_SR);
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// autocreate empty enable port if enable missing or unused
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if (!ci->ports.count(id_EN))
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ci->addInput(id_EN);
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}
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}
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@ -130,16 +130,18 @@ void BlockTracker::update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
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}
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}
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bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_data)
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bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_data, bool explain_invalid)
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{
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SSOArray<ControlSig, 2> used_clk(cfg.clk.routing.size()), used_sr(cfg.sr.routing.size()),
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used_en(cfg.en.routing.size());
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auto check_ctrlsig = [&](unsigned idx, ControlSig actual, const ControlSetConfig &ctrl,
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SSOArray<ControlSig, 2> &used) {
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if (ctrl.can_mask != -1) {
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if (ctrl.can_mask != ControlSetConfig::MaskType::MASK_NONE) {
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// Using the per-entry control signal masking
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if (actual.net == id___disconnected || (actual.net == id__CONST0 && ctrl.can_mask == 0) ||
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(actual.net == id__CONST1 && ctrl.can_mask == 0)) {
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if (actual.net == id___disconnected ||
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(actual.net == id__CONST0 && ctrl.can_mask == ControlSetConfig::MaskType::MASK_ZERO) ||
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(actual.net == id__CONST1 && ctrl.can_mask == ControlSetConfig::MaskType::MASK_ONE)) {
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return true;
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}
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}
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@ -164,6 +166,7 @@ bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_dat
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// no option available
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return false;
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};
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for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
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// flipflop control set checking
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if (cfg.split_lc) {
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@ -176,15 +179,28 @@ bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_dat
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auto &lct = cell_data.get(lc);
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if (lct.ff.ff_used) {
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// check shared control signals
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if (!check_ctrlsig(z, lct.ff.clk, cfg.clk, used_clk))
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if (!check_ctrlsig(z, lct.ff.clk, cfg.clk, used_clk)) {
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if (explain_invalid) {
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log_nonfatal_error("CLK control signal invalid.\n");
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}
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return false;
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if (cfg.en.have_signal && !check_ctrlsig(z, lct.ff.en, cfg.en, used_en))
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}
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if (cfg.en.have_signal && !check_ctrlsig(z, lct.ff.en, cfg.en, used_en)) {
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if (explain_invalid) {
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log_nonfatal_error("EN control signal invalid.\n");
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}
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return false;
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if (cfg.sr.have_signal && !check_ctrlsig(z, lct.ff.sr, cfg.sr, used_sr))
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}
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if (cfg.sr.have_signal && !check_ctrlsig(z, lct.ff.sr, cfg.sr, used_sr)) {
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if (explain_invalid) {
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log_nonfatal_error("SR control signal invalid.\n");
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}
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return false;
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}
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}
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}
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}
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// don't allow mixed MUX types in the classic fabulous arch where ctrl sigs are shared
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int tile_mux_type = 0;
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for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
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@ -202,14 +218,19 @@ bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_dat
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NPNR_ASSERT_FALSE("unknown mux type");
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if (tile_mux_type == 0)
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tile_mux_type = this_mux;
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else if (tile_mux_type != this_mux)
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else if (tile_mux_type != this_mux) {
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if (explain_invalid) {
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log_nonfatal_error("Invalid mux type.\n");
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}
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return false;
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}
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}
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// TODO: other checks...
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return true;
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}
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bool BlockTracker::check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data)
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bool BlockTracker::check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data, bool explain_invalid)
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{
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if (bel.index >= int(bel_data.size()))
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return true; // some kind of bel not being tracked
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@ -224,7 +245,7 @@ bool BlockTracker::check_validity(BelId bel, const FabricConfig &cfg, const Cell
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return true; // some kind of bel not being tracked
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const auto &entry = row.at(loc.x);
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if (flags.block == BelFlags::BLOCK_CLB) {
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return entry.clb->check_validity(cfg.clb, cell_data);
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return entry.clb->check_validity(cfg.clb, cell_data, explain_invalid);
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} else {
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return true;
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}
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@ -101,7 +101,7 @@ struct CLBState
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std::unique_ptr<CellInfo *[]> ff;
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// If there is (a) separate mux bel(s), map them to cells
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std::unique_ptr<CellInfo *[]> mux;
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bool check_validity(const LogicConfig &cfg, const CellTagger &cell_data);
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bool check_validity(const LogicConfig &cfg, const CellTagger &cell_data, bool explain_invalid = false);
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};
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struct BlockTracker
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@ -119,7 +119,7 @@ struct BlockTracker
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// ...
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};
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std::vector<std::vector<TileData>> tiles;
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bool check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data);
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bool check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data, bool explain_invalid);
|
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};
|
||||
|
||||
struct PseudoPipTags
|
||||
|
|
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Loading…
Reference in New Issue