ripup_arc walks from the sink wire back to the net source, unbinding
pips as it goes. For nets with constant_value set, the walk condition
required every wire on the path to itself carry that constant value
(getWireConstantValue(cursor) == net->constant_value). This is false
for all general-purpose routing wires, so the walk terminated at the
sink immediately and ripup never unbound anything.
Consequences on congested designs with const routing (observed on
himbaechel/xilinx, where GND/VCC use const-net mode):
- re-routing the arc rebound the same path on top of itself, leaking
one wire refcount per ripup/re-route cycle
- congestion on contested constant tap wires could never resolve; the
router livelocked with a handful of wires stuck overused for
thousands of iterations
Constant-net arc trees root at a tap wire bound with a null pip (the
const_mode midpoint bind in route_arc), so terminate the walk there
instead: walk to the net source as usual, and stop at the first
null-pip binding.
Hardware-verified on xc7a100t: a MEGA65 core port (~34k LCs) that
previously livelocked (>3000 iterations, 6 wires pinned overused) now
routes to 0 overused wires in ~30 iterations.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).
Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).
A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing
bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.
A few cosmetics and comments added.
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.
Signed-off-by: gitRaiku <raraiku@proton.me>
When a PLL output is connected to a BUFG, it can only be connected to it.
The message is improved in mentioning it and listing all ports connected and the pll name.
This simplify debug.
Adding freeing of the addition/subtraction mode switch PIP.
We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.
LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.
Addresses https://github.com/YosysHQ/apicula/issues/514
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Joris van Zwieten
Jonas K.
Lunaphied
Miodrag Milanovic
gatecat
gitRaiku
Jasper Homann
Lofty
Michael Offel
mrcmry
YRabbit
Rowan Goemans
William D. Jones
Patrick Urban
Catherine