Depth-cascaded RAMB36E1 pairs (e.g. an inferred 64K x 1 memory) set
RAM_EXTENSION_A/B to LOWER on the bottom cell and UPPER on the top
cell. The fasm writer ignored these parameters entirely.
The UPPER value shares its encoding with NONE (feature bit clear), so
only the LOWER cell needs its RAM_EXTENSION_{A,B}_LOWER bit written.
Without it the cascade data path between the two cells is not
configured and the memory misbehaves beyond the first 32K.
Verified against Vivado bitstreams and on xc7a100t hardware (128K
ROM built from cascaded pairs passes a full content fingerprint).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
A RAMB36E1 port configured with width 1 (true 32K x 1 mode) needs the
RAMB36-level BRAM36_{READ,WRITE}_WIDTH_{A,B}_1 feature in addition to
the per-half RAMB18_Yx width bits, which were the only ones emitted.
In this mode the two 16K halves interleave even/odd bit addresses.
Without the RAMB36-level feature both halves respond at addr>>1:
every write hits the bit pair 2k/2k+1 and the address LSB is ignored,
so half the memory aliases the other half.
Verified against Vivado bitstreams for the same configuration and on
xc7a100t hardware (32K x 1 and cascaded 64K x 1 inferred memories).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).
Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).
A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing
bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.
A few cosmetics and comments added.
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.
Signed-off-by: gitRaiku <raraiku@proton.me>
When a PLL output is connected to a BUFG, it can only be connected to it.
The message is improved in mentioning it and listing all ports connected and the pll name.
This simplify debug.
Adding freeing of the addition/subtraction mode switch PIP.
We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.
LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.
Addresses https://github.com/YosysHQ/apicula/issues/514
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Joris van Zwieten
Jonas K.
Lunaphied
Miodrag Milanovic
gatecat
gitRaiku
Jasper Homann
Lofty
Michael Offel
mrcmry
YRabbit
Rowan Goemans
William D. Jones
Patrick Urban
Catherine