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4924 Commits

Author SHA1 Message Date
Miodrag Milanovic 0e76ff312c Fix signal routing 2025-07-01 19:53:27 +02:00
Miodrag Milanovic ee2a5781d8 Resolve name conflicts 2025-07-01 19:52:11 +02:00
Miodrag Milanovic f883848faf Cleanup 2025-07-01 19:52:11 +02:00
Miodrag Milanovic d23e235dc3 Bump required version of database 2025-07-01 19:52:11 +02:00
Miodrag Milanovic b5c7823e7c Cleanup 2025-07-01 19:52:11 +02:00
Miodrag Milanovic c62611d8f9 Cleanup 2025-07-01 19:52:11 +02:00
Miodrag Milanovic 6da16a982d clangformat 2025-07-01 19:52:11 +02:00
Miodrag Milanovic f37de50a49 Cleanup 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 6f93d87ac8 Optimize 2025-07-01 19:51:52 +02:00
Miodrag Milanovic f61c10ea19 Fixes 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 27fdf4e16f Fixes 2025-07-01 19:51:52 +02:00
Miodrag Milanovic f32541a1b4 Cleanups 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 1019ee3862 Cleanup 2025-07-01 19:51:52 +02:00
Miodrag Milanovic c2e8bc89c0 Cleanups 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 367fe9b651 Small fixes 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 0d913b2eb9 Fixes 2025-07-01 19:51:52 +02:00
Miodrag Milanovic f195ff73fd Use CP_OUT for adders 2025-07-01 19:51:52 +02:00
Miodrag Milanovic db222fa9ba Fix GUI 2025-07-01 19:51:52 +02:00
Miodrag Milanovic ee7484b9f7 Renamed some timings 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 93230e0bdc Fixes 2025-07-01 19:51:52 +02:00
Miodrag Milanovic 96ae9bf630 Add dummy L2T4 2025-07-01 19:50:23 +02:00
Miodrag Milanovic fde10c40e0 Fix ramio 2025-07-01 19:50:23 +02:00
Miodrag Milanovic a5e8d4c110 Use L2T4 for constant drivers 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 16faaa681a Fix ADDF 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 91ce3b3509 Fixes 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 4cef33a22f Fixes for ram_o 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 994afb2261 Fixes 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 1ab73d4b7c Fixes 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 316dd7621a Fixes 2025-07-01 19:50:23 +02:00
Miodrag Milanovic d57c6efd0a Fixes 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 4d1fb361cf Start using FFs 2025-07-01 19:50:23 +02:00
Miodrag Milanovic 1012d9fea9 CPE mapping improvements 2025-07-01 19:50:23 +02:00
Miodrag Milanovic a3e102c987 Add lut tree tests for future improvements 2025-07-01 19:50:23 +02:00
José Miguel Sánchez García cb9f3117ba
himbaechel: gatemate: replace VLA with C++ features (#1513) 2025-07-01 19:39:25 +02:00
myrtle 27635785c8
heap: Allow customising legalisation ordering (#1507) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-07-01 15:32:28 +02:00
YRabbit 39f020b033
Gowin. Unbreak the segment routing. (#1508) 
Use loop enumeration of PIPs instead of direct name construction for the
upper and lower ends of the segment wire.

Also do not allow clock wires for segments.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-06-30 10:14:21 +02:00
Lofty e642e21f9b
himbaechel: output normalised wire in getWireByName (#1506) 2025-06-25 18:46:19 +02:00
gatecat 9ade2d1877 himbaechel: Add Python binding for get_tile_wire_range 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 18:37:17 +02:00
gatecat 1cd1e4a8d9 xilinx: Fix packing of weird mux trees 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 12:38:11 +02:00
gatecat 23cf1d3b92 docs: Fix outdated content in generic.md 
Fixes #1263

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 12:02:27 +02:00
gatecat ff695f26d5 sdc: Fix EOF handling during string parse 
Fixes #1490

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 11:58:11 +02:00
gatecat f74aee7047 gowin: Remove logspam during build 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 11:49:45 +02:00
gatecat a77eb9e941 ice40: Fix accidental division by DIVR in 2_PAD mode 
Fixes #1500

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 11:44:16 +02:00
Frans Skarman 0c86a218fd
Add sources to detailed timing report (#1502) 2025-06-25 11:39:25 +02:00
YRabbit 66f051d853
Gowin. BUGFIX. Stupid == vs = (#1504) 
he good thing is that these cases are very few.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-06-24 13:24:10 +02:00
Miodrag Milanovic 311a1a711d gatemate: do not use special serdes pins for auto placement 2025-06-18 09:56:54 +02:00
Miodrag Milanovic f58dd2d719 clangformat 2025-06-18 09:12:14 +02:00
Miodrag Milanović 7318d6a8ba
gatemate: Multi die support and primitives model improvement (#1501) 
* SER_CLK support

* Update constids

* wip

* CLK_FEEDBACK

* Handle SER_CLK and SER_CLK_N

* clangformat

* Cleanup

* Use _ as separator for PLL CFGs

* Remove unused clocking cells

* Do not use same name for IO models

* Fix IDDR merge

* Cleanup

* Properly handle user global signals

* Move signal inversion in bitstream creation

* Start adding multi die support

* Display die location for pins used

* Do not use constant s as locations

* Cleanup SB_DRIVE handling

* Use DDR locations from chip database

* Place only in prefered die for now

* Set D2D

* Fixed typos
 2025-06-18 08:32:57 +02:00
Lofty 5275c14ac0
gatemate: include DDR route-throughs in clock router (#1499) 
* route_clock: small cleanup

* gatemate: include DDR route-throughs for clock router
 2025-06-10 18:00:15 +02:00
YRabbit 000faab213
Gowin. BUGFIX. Fix routing of the FF inputs. (#1498) 
A segment router replaces the source-to-sink connection by
general-purpose PIPs with bus-branch segment network connections.

The problem arises when the source is connected to the sinks directly
without switching as in the case of LUT->DFF, such wires should be left
as is, which is what this PR does.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-06-10 07:54:20 +02:00