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Cleanup

This commit is contained in:
Miodrag Milanovic 2025-06-23 14:45:57 +02:00
parent d23e235dc3
commit f883848faf
2 changed files with 4 additions and 4 deletions
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4
himbaechel/uarch/gatemate/bitstream.cc
View File

@ -176,10 +176,10 @@ struct BitstreamBackend
Loc l;
auto ti = *tile_extra_data(pip.tile);
tile_xy(ctx->chip_info, pip.tile, l.x, l.y);
l.z = 0;
l.z = CPE_LT_U_Z;
BelId cpe_bel = ctx->getBelByLocation(l);
// Only if switchbox is inside core (same as sharing location with CPE)
if (cpe_bel != BelId() && ctx->getBelType(cpe_bel).in(id_CPE_LT_L, id_CPE_LT_U)) {
if (cpe_bel != BelId() && ctx->getBelType(cpe_bel) == id_CPE_LT_U) {
// Bitstream data for certain SB_DRIVES is located in other tiles
switch (word[14]) {
case '3':

4
himbaechel/uarch/gatemate/route_clock.cc
View File

@ -48,8 +48,8 @@ void GateMateImpl::route_clock()
auto clk_nets = std::vector<NetInfo *>{};
auto reserved_wires = dict<WireId, IdString>{};
auto feeds_clk_port = [](PortRef &port) {
return port.cell->type.in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U) && port.port.in(id_CLK);
auto feeds_clk_port = [&](PortRef &port) {
return (ctx->getBelBucketForCellType(port.cell->type) == id_CPE_FF) && port.port.in(id_CLK);
};
auto feeds_ddr_port = [&](NetInfo *net, PortRef &port) {