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nextpnr
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Fixes

This commit is contained in:
Miodrag Milanovic 2025-06-22 18:58:40 +02:00
parent f195ff73fd
commit 0d913b2eb9
4 changed files with 9 additions and 5 deletions
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3
himbaechel/uarch/gatemate/bitstream.cc
View File

@ -243,13 +243,10 @@ struct BitstreamBackend
break;
case id_CPE_L2T4.index:
case id_CPE_L2T5.index:
case id_CPE_L2T5_U.index:
case id_CPE_L2T5_L.index:
case id_CPE_FF.index:
case id_CPE_RAMI.index:
case id_CPE_RAMO.index:
case id_CPE_RAMIO.index:
case id_CPE_LT.index:
case id_CPE_LT_U.index:
case id_CPE_LT_L.index: {
// Update configuration bits based on signal inversion

1
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -252,6 +252,7 @@ void GateMateImpl::postPlace()
for (auto &port : ctx->cells[pcell]->ports) {
ctx->cells[pcell]->disconnectPort(port.first);
}
ctx->unbindBel(ctx->cells[pcell]->bel);
ctx->cells.erase(pcell);
}
delete_cells.clear();

8
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -172,8 +172,14 @@ def set_timings(ch):
dff.add_setup_hold("CLK", "DIN", ClockEdge.RISING, TimingValue(60), TimingValue(50))
dff.add_clock_out("CLK", "DOUT", ClockEdge.RISING, TimingValue(60))
lut = ch.timing.add_cell_variant(speed, "CPE_RAMI")
lut.add_comb_arc("RAM_I", "OUT", TimingValue(0, 0))
lut = ch.timing.add_cell_variant(speed, "CPE_RAMO")
lut.add_comb_arc("I", "RAM_O", TimingValue(0, 0))
lut = ch.timing.add_cell_variant(speed, "CPE_RAMIO")
lut.add_comb_arc("I", "OUT", TimingValue(0, 0))
#lut.add_comb_arc("I", "OUT", TimingValue(0, 0))
lut.add_comb_arc("I", "RAM_O", TimingValue(0, 0))
lut.add_comb_arc("RAM_I", "OUT", TimingValue(0, 0))

2
himbaechel/uarch/gatemate/pack_cpe.cc
View File

@ -272,7 +272,7 @@ void GateMatePacker::pack_cpe()
}
for (auto &cell : dff_list) {
CellInfo &ci = *cell;
CellInfo *lt = create_cell_ptr(id_CPE_LT, ctx->idf("%s$lt", ci.name.c_str(ctx)));
CellInfo *lt = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$lt", ci.name.c_str(ctx)));
lt->cluster = ci.name;
lt->constr_abs_z = false;
lt->constr_z = -2;