Merge branch 'master' into netgen-1.5

with the file number, so that it can get confused between libraries.
Also made a fix to coerce one cell class to be forced to be the
same in both circuits under some circumstances.

Makefile

@@ -9,7 +9,7 @@ MODULES = base
 MAKEFLAGS =
 INSTALL_CAD_DIRS = lib doc
 
-include defs.mak
+-include defs.mak
 
 all:	$(ALL_TARGET)
 
@@ -51,8 +51,8 @@ depend:
 install: $(INSTALL_TARGET)
 
 install-netgen:
-	@echo --- installing executable to $(DESTDIR)${BINDIR}
-	@echo --- installing run-time files to $(DESTDIR)${LIBDIR}
+	@echo --- installing executable to $(DESTDIR)${INSTALL_BINDIR}
+	@echo --- installing run-time files to $(DESTDIR)${INSTALL_LIBDIR}
 	@${MAKE} install-real >> install.log
 
 install-real: install-dirs
@@ -60,15 +60,15 @@ install-real: install-dirs
 		(cd $$dir && ${MAKE} install); done
 
 install-tcl-dirs:
-	${NETGENDIR}/scripts/mkdirs $(DESTDIR)${BINDIR} \
-		$(DESTDIR)${TCLDIR} $(DESTDIR)${PYDIR}
+	${NETGENDIR}/scripts/mkdirs $(DESTDIR)${INSTALL_BINDIR} \
+		$(DESTDIR)${INSTALL_TCLDIR} $(DESTDIR)${INSTALL_PYDIR}
 
 install-dirs:
-	${NETGENDIR}/scripts/mkdirs $(DESTDIR)${BINDIR}
+	${NETGENDIR}/scripts/mkdirs $(DESTDIR)${INSTALL_BINDIR}
 
 install-tcl: install-dirs
-	@echo --- installing executable to $(DESTDIR)${BINDIR}
-	@echo --- installing run-time files to $(DESTDIR)${LIBDIR}
+	@echo --- installing executable to $(DESTDIR)${INSTALL_BINDIR}
+	@echo --- installing run-time files to $(DESTDIR)${INSTALL_LIBDIR}
 	@${MAKE} install-tcl-real 2>&1 >> install.log
 
 install-tcl-real: install-tcl-dirs

VERSION

@@ -1 +1 @@
-1.5.133
+1.5.156

base/flatten.c

@@ -259,7 +259,7 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
   struct  nlist *ChildCell;
   struct objlist *tmp, *ob2, *ob3;
   int	notdone, rnodenum;
-  char	tmpstr[200];
+  char	tmpstr[1024];
   int	nextnode, oldmax, numflat = 0;
 #if !OLDPREFIX
   int     prefixlength;
@@ -1166,7 +1166,7 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
           while (ob && obt && (ob->type > FIRSTPIN || ob == firstpin) &&
 			ob->model.class != NULL) {
 	     nob = ob->next;
-	     if ((obt->type == PORT) && (obt->node == -1)) {
+	     if ((obt->type == PORT) && (obt->node == -2)) {
 
 	        /* Remove this pin */
 
@@ -1238,7 +1238,7 @@ int CleanupPins(char *name, int filenum)
 
    for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
       if (ob->type != PORT) break;
-      if (ob->node == -1) {
+      if (ob->node == -2) {
 	 needscleanup = 1;
 	 break;
       }
@@ -1265,7 +1265,7 @@ int CleanupPins(char *name, int filenum)
       }
       else if (ob->type != PORT) break;
       nob = ob->next;
-      if (ob->node == -1) {
+      if (ob->node == -2) {
 	 if (lob == NULL) {
 	    ThisCell->cell = ob->next;
 	 }
@@ -1539,7 +1539,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	/* (it without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
-			(ecomp->cell2->class == CLASS_SUBCKT)) {
+			(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
 	    ecomp->add2 = -ecomp->num2;
 	    match = 1;
 	    for (ob2 = ecomp->cell2->cell; ob2; ob2 = ob2->next) {
@@ -1597,7 +1597,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	/* (it without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
-			(ecomp->cell1->class == CLASS_SUBCKT)) {
+			(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
 	    ecomp->add1 = -ecomp->num1;
 	    match = 1;
 	    for (ob2 = ecomp->cell1->cell; ob2; ob2 = ob2->next) {

base/netcmp.h

@@ -8,6 +8,9 @@ extern struct nlist *Circuit2;
 
 extern int ExhaustiveSubdivision;
 
+extern int left_col_end;
+extern int right_col_end;
+
 #ifdef TCL_NETGEN
 #include <tcl.h>
 extern int InterruptPending;

base/netfile.c

@@ -289,6 +289,7 @@ int GetNextLineNoNewline(char *delimiter)
     char *newbuf;
     int testc;
     int nested = 0;
+    int llen;
 
     if (feof(infile)) return -1;
 
@@ -301,20 +302,33 @@ int GetNextLineNoNewline(char *delimiter)
 
 	if (linesize == 0) {
 	    /* Allocate memory for line */
-	    linesize = 500;
-	    line = (char *)MALLOC(linesize);
-	    linetok = (char *)MALLOC(linesize);
+	    linesize = 2000;
+	    line = (char *)MALLOC(linesize + 1);
+	    linetok = (char *)MALLOC(linesize + 1);
 	}
 	fgets(line, linesize, infile);
-	while (strlen(line) == linesize - 1) {
-	    newbuf = (char *)MALLOC(linesize + 500);
+	/* Immediately resolve backslash-EOL */
+	llen = strlen(line);
+	while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
+	    *(line + llen - 2) = '\n';
+	    fgets(line + llen - 1, linesize - llen + 1, infile);
+	    llen = strlen(line);
+	}
+	while (llen == linesize - 1) {
+	    newbuf = (char *)MALLOC(linesize + 501);
 	    strcpy(newbuf, line);
 	    FREE(line);
 	    line = newbuf;
 	    fgets(line + linesize - 1, 501, infile);
+	    llen = strlen(line);
+	    while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
+		*(line + llen - 2) = '\n';
+		fgets(line + llen - 1, linesize - llen + 1, infile);
+		llen = strlen(line);
+	    }
 	    linesize += 500;
 	    FREE(linetok);
-	    linetok = (char *)MALLOC(linesize);
+	    linetok = (char *)MALLOC(linesize + 1);
 	}
 
 	/* Check for substitutions (verilog only).  Make sure linetok is    */
@@ -329,7 +343,7 @@ int GetNextLineNoNewline(char *delimiter)
 	    for (s = line; *s != '\0'; s++) {
 		if (*s == '`') {
 		    w = s + 1;
-		    while (isalnum(*w)) w++;
+		    while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
 		    e = *w;
 		    *w = '\0';
 		    kl = (struct property *)HashLookup(s + 1, definitions);
@@ -365,7 +379,7 @@ int GetNextLineNoNewline(char *delimiter)
 	    for (s = line; *s != '\0'; s++) {
 		if (*s == '`') {
 		    w = s + 1;
-		    while (isalnum(*w)) w++;
+		    while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
 		    e = *w;
 		    *w = '\0';
 		    kl = (struct property *)HashLookup(s + 1, definitions);
@@ -496,6 +510,24 @@ void GetNextLine(char *delimiter)
     } while (nexttok == NULL);
 }
 
+/*----------------------------------------------------------------------*/
+/* Return a pointer to the line at the position of nexttok		*/
+/* This is used only when returning the entire line, untokenized, and	*/
+/* is only called by the verilog read routine when reading the value of	*/
+/* a `define statement.							*/
+/*----------------------------------------------------------------------*/
+
+char *GetLineAtTok()
+{
+    char *lpos;
+
+    if (nexttok == NULL) return NULL;
+    if (line == NULL) return NULL;
+
+    lpos = strstr(line, nexttok);
+    return lpos;
+}
+
 /*----------------------------------------------------------------------*/
 /* if nexttok is already NULL, force scanner to read new line		*/
 /*----------------------------------------------------------------------*/
@@ -673,6 +705,7 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
     /* accordingly (needs to be done).						*/
 
     if (*s == '\\') {
+        s++;
         while (*s != '\0') {
 	    if ((*s == ' ') || (*s == '\\')) {
 		s++;
@@ -765,7 +798,7 @@ int OpenParseFile(char *name, int fnum)
   FILE *locfile;
   struct filestack *newfile;
 
-  locfile = fopen(name,"r");
+  locfile = fopen(name, "r");
   linenum = 0;
   /* reset the token scanner */
   nexttok = NULL;  
@@ -850,7 +883,12 @@ char *ReadNetlist(char *fname, int *fnum)
       {SPICE_EXTENSION, ReadSpice},
       {SPICE_EXT2, ReadSpice},
       {SPICE_EXT3, ReadSpice},
+      {SPICE_EXT4, ReadSpice},
+      {SPICE_EXT5, ReadSpice},
+      {SPICE_EXT6, ReadSpice},
+      {SPICE_EXT7, ReadSpice},
       {VERILOG_EXTENSION, ReadVerilog},
+      {SYS_VERILOG_EXTENSION, ReadVerilog},
       {NETGEN_EXTENSION, ReadNetgenFile},
       {NULL, NULL}
     };

base/netfile.h

@@ -9,11 +9,16 @@
 #define SIM_EXTENSION ".sim"
 #define SPICE_EXTENSION ".spice"
 #define SPICE_EXT2 ".spc"
-#define SPICE_EXT3 ".fspc"
+#define SPICE_EXT3 ".sp"
+#define SPICE_EXT4 ".spi"
+#define SPICE_EXT5 ".fspc"
+#define SPICE_EXT6 ".cir"
+#define SPICE_EXT7 ".ckt"
 #define NETGEN_EXTENSION ".ntg"
 #define CCODE_EXTENSION ".c.code"
 #define ESACAP_EXTENSION ".esa"
 #define VERILOG_EXTENSION ".v"
+#define SYS_VERILOG_EXTENSION ".sv"
 
 #define LINELENGTH 80
 
@@ -31,6 +36,7 @@ extern struct hashdict *definitions;
 extern char *nexttok;
 #define SKIPTO(a) do {SkipTok(NULL);} while (!match(nexttok,a))
 extern char *strdtok(char *pstring, char *delim1, char *delim2);
+extern char *GetLineAtTok();
 extern void SkipTok(char *delimiter);
 extern void SkipTokNoNewline(char *delimiter);
 extern void SkipTokComments(char *delimiter);

base/objlist.c

@@ -289,7 +289,7 @@ static struct hashdict cell_dict;
 void InitCellHashTable(void)
 {
     hashfunc = hash;
-    matchfunc = match;
+    matchfunc = NULL;
     matchintfunc = matchfile;
     InitializeHashTable(&cell_dict, CELLHASHSIZE);
 }
@@ -1112,13 +1112,17 @@ void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr)
 
 /***************  GENERAL UTILITIES ****************************/
 
-int NumberOfPorts(char *cellname)
+int NumberOfPorts(char *cellname, int file)
 {
   struct nlist *tp;
   struct objlist *ob;
   int ports;
 
-  tp = LookupCell(cellname);
+  if (file == -1)
+    tp = LookupCell(cellname);
+  else
+    tp = LookupCellFile(cellname, file);
+
   if (tp == NULL) return(0);
   ports = 0;
   for (ob = tp->cell; ob != NULL; ob = ob->next)

base/objlist.h

@@ -242,7 +242,7 @@ extern void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr);
 extern void FreePorts(char *cellname);
 extern struct IgnoreList *ClassIgnore;
 
-extern int NumberOfPorts(char *cellname);
+extern int NumberOfPorts(char *cellname, int file);
 extern struct objlist *InstanceNumber(struct nlist *tp, int inst);
 
 extern struct objlist *List(char *list_template);

base/place.c

@@ -929,7 +929,7 @@ void ToggleDebug(void)
 void DescribeCell(char *name, int detail)
 {
   Printf("Cell: %s contains %d instances, %d nodes and %d ports\n", name, 
-	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name));
+	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name, -1));
   PrintEmbeddingTree(stdout,name,detail);
 }
 

base/query.c

@@ -801,9 +801,16 @@ void DescribeInstance(char *name, int file)
   {
     if (ob->node > nodemax) nodemax = ob->node;
     else if ((ob->node == -1) && (ob->model.port != PROXY)) {
-      if (disconnectednodes == 0) Fprintf(stderr, "\n");
-      disconnectednodes++;
-      Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
+
+      /* All black-box modules and placeholders by definition have all	*/
+      /* disconnected pins, so don't report those.			*/
+
+      if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
+      {
+	if (disconnectednodes == 0) Fprintf(stderr, "\n");
+        disconnectednodes++;
+        Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
+      }
     }
   }
   instlist = (unsigned char *) CALLOC((nodemax + 1), sizeof(unsigned char));
@@ -900,7 +907,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
   np->dumped = 1;
 
   if (np->class != CLASS_SUBCKT) {
-    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname));
+    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname, filenum));
     return;
   }
 
@@ -913,7 +920,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
       am_a_leaf = 0;
     }
 
-  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname));
+  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname, filenum));
   return;
 }
 
@@ -1063,7 +1070,7 @@ void Query(void)
       ActelLib();
       break;
     case 'S':
-      promptstring("Read SPICE (.ckt) file? ", repstr);
+      promptstring("Read SPICE (.spice) file? ", repstr);
       ReadSpice(repstr, &filenum);
       break;
     case 'V':

base/spice.c

@@ -1883,20 +1883,36 @@ char *ReadSpiceTop(char *fname, int *fnum, int blackbox)
   CurrentCell = NULL;
 
   if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
-    char name[100];
 
-    SetExtension(name, fname, SPICE_EXTENSION);
-    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
-      Fprintf(stderr,"Error in SPICE file read: No file %s\n",name);
+    if (strrchr(fname, '.') == NULL) {
+      char name[1024];
+      SetExtension(name, fname, SPICE_EXTENSION);
+      if ((filenum = OpenParseFile(name, *fnum)) < 0) {
+        Fprintf(stderr, "Error in SPICE file read: No file %s\n", name);
+        *fnum = filenum;
+        return NULL;
+      }
+    }    
+    else {
+      Fprintf(stderr, "Error in SPICE file read: No file %s\n", fname);
       *fnum = filenum;
       return NULL;
-    }    
+    }
   }
 
-  /* Make sure all SPICE file reading is case insensitive */
-  matchfunc = matchnocase;
-  matchintfunc = matchfilenocase;
-  hashfunc = hashnocase;
+  /* Make sure all SPICE file reading is case insensitive   */
+  /* BUT if a verilog file was read before it, then it will */
+  /* be forced to be case sensitive, caveat end-user.	    */
+
+  if (matchfunc == match) {
+      Printf("Warning:  A case-sensitive file has been read and so the "
+                "SPICE netlist must be treated case-sensitive to match.\n");
+  }
+  else {
+      matchfunc = matchnocase;
+      matchintfunc = matchfilenocase;
+      hashfunc = hashnocase;
+  }
 
   InitializeHashTable(&spiceparams, OBJHASHSIZE);
 
@@ -1980,14 +1996,18 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
 	/* helps, if the file didn't have an extension.  But	*/
 	/* really, we're getting desperate at this point.	*/
 
-	if (strchr(fname, '.') == NULL) {
+	if (strrchr(fname, '.') == NULL) {
            SetExtension(name, fname, SPICE_EXTENSION);
            filenum = OpenParseFile(name, parent);
-	}
-        if (filenum < 0) {
-           Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
-           return;
+	   if (filenum < 0) {
+             Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
+             return;
+	   }
         }    
+        else {
+          Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
+          return;
+	}
      }
   }
   ReadSpiceFile(fname, parent, CellStackPtr, blackbox);

base/verilog.c

@@ -98,6 +98,31 @@ struct bus *NewBus()
     return (wb);
 }
 
+//-------------------------------------------------------------------------
+// Find a character c in a string, assuming that string may contain
+// verilog names, where anything, including char c, may appear in the
+// string if it is a backslash-escaped name.  Only the position of
+// character c outside of a verilog name is reported.
+//-------------------------------------------------------------------------
+
+char *strvchr(char *string, char c)
+{
+    char *s;
+
+    for (s = string; *s != '\0'; s++) {
+	if (*s == '\\') {
+	    while (*s != '\0' && *s != ' ') s++;
+	    if (*s == '\0') {
+		Fprintf(stderr, "Error:  Verilog backslash-escaped name"
+			" does not end with a space.\n");
+		break;
+	    }
+	}
+	if (*s == c) return s;
+    }
+    return NULL;
+}
+
 //-------------------------------------------------------------------------
 // Get bus indexes from the notation name[a:b].  If there is only "name"
 // then look up the name in the bus hash list and return the index bounds.
@@ -283,7 +308,7 @@ int GetBusTok(struct bus *wb)
 
 int GetBus(char *astr, struct bus *wb)
 {
-    char *colonptr, *brackstart, *brackend, *sigend, sdelim;
+    char *colonptr, *brackstart, *brackend, *sigend, sdelim, *aastr;
     int result, start, end;
 
     if (wb == NULL) return 0;
@@ -302,8 +327,8 @@ int GetBus(char *astr, struct bus *wb)
 	astr++;
 	wb->end = 0;
 	while((*astr != '\0') && (*astr != '}')) {
-	    sigend = strchr(astr, ',');
-	    if (sigend == NULL) sigend = strchr(astr, '}');
+	    sigend = strvchr(astr, ',');
+	    if (sigend == NULL) sigend = strvchr(astr, '}');
 	    if (sigend == NULL) {
 		Printf("Badly formed wire bundle \"%s\"\n", astr - 1);
 		return 1;
@@ -325,15 +350,22 @@ int GetBus(char *astr, struct bus *wb)
 	return 0;
     }
 
-    brackstart = strchr(astr, '[');
+    // Delimiters may appear in backslash-escaped names. . . ignore these.
+    aastr = astr;
+    if (*aastr == '\\') {
+	aastr++;
+	while (*aastr != ' ' && *aastr != '\\' && *aastr != '\0') aastr++;
+    }
+
+    brackstart = strvchr(aastr, '[');
     if (brackstart != NULL) {
-	brackend = strchr(astr, ']');
+	brackend = strvchr(aastr, ']');
 	if (brackend == NULL) {
 	    Printf("Badly formed array notation \"%s\"\n", astr);
 	    return 1;
 	}
 	*brackend = '\0';
-	colonptr = strchr(astr, ':');
+	colonptr = strvchr(aastr, ':');
 	if (colonptr) *colonptr = '\0';
 	result = sscanf(brackstart + 1, "%d", &start);
 	if (colonptr) *colonptr = ':';
@@ -912,7 +944,7 @@ skip_endmodule:
     }
     else if (match(nexttok, "input") || match(nexttok, "output")
 		|| match(nexttok, "inout")) {
-	struct bus wb;
+	struct bus wb, *nb;
  
 	// Parsing of ports as statements not in the module pin list.
 	wb.start = wb.end = -1;
@@ -945,6 +977,11 @@ skip_endmodule:
 			    Port(portname);
 			}
 		    }
+		    /* Also register this port as a bus */
+		    nb = NewBus();
+		    nb->start = wb.start;
+		    nb->end = wb.end;
+		    HashPtrInstall(nexttok, nb, &buses);
 		    wb.start = wb.end = -1;
 		}
 		else {
@@ -1058,6 +1095,13 @@ skip_endmodule:
 	 kl->pdefault.ival = 1;
          kl->slop.ival = 0;
       }
+      else if (nexttok[0] == '(') {
+	 /* For now, the netgen verilog parser doesn't handle `define f(X) ... */
+	 SkipNewLine(VLOG_DELIMITERS);
+	 FREE(kl->key);
+	 FREE(kl);
+	 kl = NULL;
+      }
       else if (ConvertStringToInteger(nexttok, &ival) == 1) {
 	 /* Parameter parses as an integer */
       	 kl->type = PROP_INTEGER;
@@ -1071,12 +1115,19 @@ skip_endmodule:
          kl->slop.dval = 0.01;		// One percent default
       }
       else {
-	 /* Treat the parameter as a string */
+         char *toks;
+
+	 /* Treat the parameter as a string; BUT pull everything to */
+	 /* EOL, not just the current token.			    */
+	 toks = GetLineAtTok();
+
       	 kl->type = PROP_STRING;
-	 kl->pdefault.string = strsave(nexttok);
+	 kl->pdefault.string = strsave(toks);
          kl->slop.dval = 0.0;
+
+	 SkipNewLine(VLOG_DELIMITERS);
       }
-      HashPtrInstall(kl->key, kl, &verilogdefs);
+      if (kl) HashPtrInstall(kl->key, kl, &verilogdefs);
     }
     else if (match(nexttok, "`undef")) {
       struct property *kl = NULL;
@@ -1165,7 +1216,7 @@ skip_endmodule:
 	else {	    /* "assign" */
 	    SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 	    if (GetBus(nexttok, &wb) == 0) {
-		char *aptr = strchr(nexttok, '[');
+		char *aptr = strvchr(nexttok, '[');
 		if (aptr != NULL) {
 		    *aptr = '\0';
 		    /* Find object of first net in bus */
@@ -1174,9 +1225,16 @@ skip_endmodule:
 		    lhs = LookupObject(nodename, CurrentCell);
 		    *aptr = '[';
 		}
+		else {
+		    strcpy(noderoot, nexttok);
+		    /* Set LHS to the start of the vector */
+		    sprintf(nodename, "%s[%d]", nexttok, wb.start);
+		    lhs = LookupObject(nodename, CurrentCell);
+		}
 	    }
 	    else {
 		lhs = LookupObject(nexttok, CurrentCell);
+		strcpy(noderoot, nexttok);
 	    }
 	    SkipTokComments(VLOG_DELIMITERS);
 	    if (lhs && ((!nexttok) || (!match(nexttok, "=")))) {
@@ -1219,7 +1277,7 @@ skip_endmodule:
 		}
 		else {
 		    if (GetBus(nexttok, &wb2) == 0) {
-			char *aptr = strchr(nexttok, '[');
+			char *aptr = strvchr(nexttok, '[');
 			j = wb2.start;
 			if (aptr != NULL) {
 			    *aptr = '\0';
@@ -1237,13 +1295,21 @@ skip_endmodule:
 			if (rhs != NULL) {
 			    Printf("Improper assignment;  left-hand side cannot "
 					"be parsed.\n");
-			    Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    if (j != -1)
+			    	Printf("Right-hand side is \"%s\".\n", assignroot);
+			    else
+			    	Printf("Right-hand side is \"%s\".\n", rhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    break;
 			}
 			if (lhs != NULL) {
 			    Printf("Improper assignment;  right-hand side cannot "
 					"be parsed.\n");
-			    Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    if (i != -1)
+			    	Printf("Left-hand side is \"%s\".\n", noderoot);
+			    else
+			    	Printf("Left-hand side is \"%s\".\n", lhs->name);
+			    Printf("Improper expression is \"%s\".\n", nexttok);
 			    /* Not parsable, probably behavioral verilog? */
 			    Printf("Module '%s' is not structural verilog, "
 				    "making black-box.\n", model);
@@ -1308,6 +1374,7 @@ skip_endmodule:
       struct portelement {
 	char *name;	// Name of port in subcell
 	char *net;	// Name of net connecting to port in the parent
+	int   width;	// Width of port, if port is a bus
 	struct portelement *next;
       };
 
@@ -1315,6 +1382,22 @@ skip_endmodule:
       struct objlist *obptr;
 
       strncpy(modulename, nexttok, 99);
+
+      /* If module name is a verilog primitive, then treat the module as a  */
+      /* black box (this is not a complete list.  Preferable to use hash    */
+      /* function instead of lots of strcmp() calls).			    */
+
+      if (!strcmp(modulename, "buf") || !strcmp(modulename, "notif1") ||
+	    !strcmp(modulename, "not") || !strcmp(modulename, "and") ||
+	    !strcmp(modulename, "or") || !strcmp(modulename, "bufif0") ||
+	    !strcmp(modulename, "bufif1") || !strcmp(modulename, "notif0")) {
+
+         Printf("Module contains verilog primitive '%s'.\n", nexttok);
+         Printf("Module '%s' is not structural verilog, making black-box.\n", model);
+	 SetClass(CLASS_MODULE);
+	 goto skip_endmodule;
+      }
+
       if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
@@ -1417,6 +1500,7 @@ nextinst:
 	    else {
 	       new_port = (struct portelement *)CALLOC(1, sizeof(struct portelement));
 	       new_port->name = strsave(nexttok + 1);
+	       new_port->width = -1;
 	       SkipTokComments(VLOG_DELIMITERS);
 	       if (!match(nexttok, "(")) {
 	           Printf("Badly formed subcircuit pin line at \"%s\"\n", nexttok);
@@ -1438,25 +1522,25 @@ nextinst:
 	       }
 	       else {
 		  if (!strcmp(nexttok, "{")) {
-		     char *in_line_net = (char *)MALLOC(1);
-		     char *new_in_line_net = NULL;
-		     *in_line_net = '\0';
-		     /* In-line array---read to "}" */
+		     char *wire_bundle = (char *)MALLOC(1);
+		     char *new_wire_bundle = NULL;
+		     *wire_bundle = '\0';
+		     /* Wire bundle---read to "}" */
 		     while (nexttok) {
-			 new_in_line_net = (char *)MALLOC(strlen(in_line_net) +
+			 new_wire_bundle = (char *)MALLOC(strlen(wire_bundle) +
 				    strlen(nexttok) + 1);
 			 /* Roundabout way to do realloc() becase there is no REALLOC() */
-			 strcpy(new_in_line_net, in_line_net);
-			 strcat(new_in_line_net, nexttok);
-			 FREE(in_line_net);
-			 in_line_net = new_in_line_net;
+			 strcpy(new_wire_bundle, wire_bundle);
+			 strcat(new_wire_bundle, nexttok);
+			 FREE(wire_bundle);
+			 wire_bundle = new_wire_bundle;
 			 if (!strcmp(nexttok, "}")) break;
 			 SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 		     }
 		     if (!nexttok) {
-			 Printf("Unterminated net in pin %s\n", in_line_net);
+			 Printf("Unterminated net in pin %s\n", wire_bundle);
 		     }
-		     new_port->net = in_line_net;
+		     new_port->net = wire_bundle;
 		  }
 		  else
 		     new_port->net = strsave(nexttok);
@@ -1558,19 +1642,40 @@ nextinst:
 	    // Check if net name is a wire bus or portion of a bus
 	    if (GetBus(scan->net, &wb) == 0) {
 		int range;
+
+		// This takes care of three situations:
+		// (1) The signal bus length matches the number of instances:
+		//     apply one signal per instance.
+		// (2) The signal bus length is a multiple of the number of instances:
+		//     apply a signal sub-bus to each instance.
+		// (3) The number of instances is a multiple of the signal bus length:
+		//     apply the same signal to each instance.
+
 		if ((arrayend - arraystart) == (wb.end - wb.start)) {
 		    // Net is a bus, but net is split over arrayed instances
 		    Port(scan->name);
 		}
 		else if (wb.start > wb.end) {
-		    range = wb.start - wb.end;
+		    if ((arraystart - arrayend) > (wb.start - wb.end))
+			range = (((arraystart - arrayend) + 1) /
+				    ((wb.start - wb.end) + 1)) - 1;
+		    else
+			range = (((wb.start - wb.end) + 1) /
+				    ((arraystart - arrayend) + 1)) - 1;
+
 		    for (i = range; i >= 0; i--) {
 			sprintf(defport, "%s[%d]", scan->name, i);
 			Port(defport);
 		    }
 		}
 		else {
-		    range = wb.end - wb.start;
+		    if ((arrayend - arraystart) >  (wb.end - wb.start))
+			range = (((arrayend - arraystart) + 1) /
+				    ((wb.end - wb.start) + 1)) - 1;
+		    else
+			range = (((wb.end - wb.start) + 1) /
+				    ((arrayend - arraystart) + 1)) - 1;
+
 		    for (i = 0; i <= range; i++) {
 			sprintf(defport, "%s[%d]", scan->name, i);
 			Port(defport);
@@ -1622,7 +1727,12 @@ nextinst:
 	    int j, result;
 	    struct objlist *bobj;
 	    char *bptr;
-	    int minnet, maxnet, testidx;
+	    int minnet, maxnet, testidx, width;
+
+	    width = portstart - portend;
+	    if (width < 0) width = -width;
+	    width++;
+	    scan->width = width;
 
 	    result = GetBus(scan->net, &wb);
 	    if (result == -1) {
@@ -1636,7 +1746,7 @@ nextinst:
 
 		for (bobj = CurrentCell->cell; bobj; bobj = bobj->next) {
 		    if (bobj->type == PORT) {
-			if ((bptr = strchr(bobj->name, '[')) != NULL) {
+			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
 			    *bptr = '\0';
 			    if (!strcmp(bobj->name, scan->net)) {
 				*bptr = '[';
@@ -1648,7 +1758,7 @@ nextinst:
 			}
 		    }
 		    else if (bobj->type == NODE) {
-			if ((bptr = strchr(bobj->name, '[')) != NULL) {
+			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
 			    *bptr = '\0';
 			    if (!strcmp(bobj->name, scan->net)) {
 				if (sscanf(bptr + 1, "%d", &testidx) == 1) {
@@ -1674,17 +1784,31 @@ nextinst:
 	    }
 
 	    if (result == 0) {
-	       if (((wb.start - wb.end) != (portstart - portend)) &&
-		   	((wb.start - wb.end) != (portend - portstart))) {
-		  if (((wb.start - wb.end) != (arraystart - arrayend)) &&
-			((wb.start - wb.end) != (arrayend - arraystart))) {
-		     Fprintf(stderr, "Error:  Net %s bus width does not match "
-				"port %s bus width.\n", scan->net, scan->name);
-		  }
-		  // Otherwise, net is bit-sliced across array of instances.
+	       int match = 0;
+	       int wblen, arraylen;
+
+	       arraylen = arraystart - arrayend;
+	       wblen = wb.start - wb.end;
+
+	       if (arraylen < 0) arraylen = -arraylen;
+	       if (wblen < 0) wblen = -wblen;
+
+	       arraylen++;
+	       wblen++;
+
+	       if ((scan->width * arraylen) == wblen) match = 1;
+	       else if (wblen == scan->width) match = 1;
+	       else if (wblen == arraylen) match = 1;
+	       else {
+		  Fprintf(stderr, "Warning:  Net %s bus width (%d) does not match "
+				"port %s bus width (%d) or array width (%d).\n",
+				scan->net, wblen, scan->name, scan->width, arraylen);
 	       }
-	       else if (wb.start > wb.end) {
-		  char *bptr, *cptr, cchar, *netname;
+
+	       // Net is bit-sliced across array of instances.
+
+	       if (wb.start > wb.end) {
+		  char *bptr = NULL, *cptr = NULL, cchar, *netname;
 		  unsigned char is_bundle = 0;
 		  struct bus wbb;
 
@@ -1695,8 +1819,8 @@ nextinst:
 		  if (*netname == '{') {
 		     is_bundle = 1;
 		     netname++;
-		     cptr = strchr(netname, ',');
-		     if (cptr == NULL) cptr = strchr(netname, '}');
+		     cptr = strvchr(netname, ',');
+		     if (cptr == NULL) cptr = strvchr(netname, '}');
 		     if (cptr == NULL) cptr = netname + strlen(netname) - 1;
 		     cchar = *cptr;
 		     *cptr = '\0';
@@ -1705,14 +1829,12 @@ nextinst:
 		  // Remove indexed part of scan->net
 		  if (GetBus(netname, &wbb) == 0) {
 		     i = wbb.start;
-		     if ((bptr = strchr(netname, '[')) != NULL)
+		     if ((bptr = strvchr(netname, '[')) != NULL)
 			 *bptr = '\0';
 		  }
 		  else
 		     i = -1;
 
-		  if (is_bundle) *cptr = cchar;	 /* Restore bundle delimiter */
-		  
 		  while (1) {
 	             new_port = (struct portelement *)CALLOC(1,
 				sizeof(struct portelement));
@@ -1723,6 +1845,7 @@ nextinst:
 		     else
 			 sprintf(vname, "%s[%d]", netname, i); 
 	             new_port->net = strsave(vname);
+		     new_port->width = scan->width;
 
 		     if (last == NULL)
 			head = new_port;
@@ -1736,34 +1859,36 @@ nextinst:
 
 		     if (portstart > portend) j--;
 		     else j++;
-		     if (wbb.start > wbb.end) i--;
-		     else i++;
+		     if (i != -1) {
+			if (wbb.start > wbb.end) i--;
+			else i++;
+		     }
 
 		     if (is_bundle &&
 			    ((i == -1) ||
 			    ((wbb.start > wbb.end) && (i < wbb.end)) ||
-			    ((wbb.start < wbb.end) && (i > wbb.end)))) {
+			    ((wbb.start <= wbb.end) && (i > wbb.end)))) {
 		         if (bptr) *bptr = '[';
 
 			 netname = cptr + 1;
-		         cptr = strchr(netname, ',');
-			 if (cptr == NULL) cptr = strchr(netname, '}');
+			 if (cptr) *cptr = cchar; /* Restore previous bundle delimiter */
+		         cptr = strvchr(netname, ',');
+			 if (cptr == NULL) cptr = strvchr(netname, '}');
 			 if (cptr == NULL) cptr = netname + strlen(netname) - 1;
 			 cchar = *cptr;
 			 *cptr = '\0';
 
 			 if (GetBus(netname, &wbb) == 0) {
 			    i = wbb.start;
-			    if ((bptr = strchr(netname, '[')) != NULL)
+			    if ((bptr = strvchr(netname, '[')) != NULL)
 				*bptr = '\0';
 			 }
 			 else i = -1;
-
-			 *cptr = cchar;	    /* Restore delimiter */
 		     }
 		  }
 		  FREE(scan);
 		  scan = last;
+		  if (cptr) *cptr = cchar; /* Restore bundle delimiter */
 	       }
 	    }
 	    else if (portstart != portend) {
@@ -1793,7 +1918,7 @@ nextinst:
          obptr = LookupInstance(locinst, CurrentCell);
          if (obptr != NULL) {
             do {
-	       struct bus wb;
+	       struct bus wb, wb2;
 	       char *obpinname;
 	       int obpinidx;
 
@@ -1815,14 +1940,19 @@ nextinst:
 		  scan = scan->next;
 	       }
 	       if (scan == NULL) {
-		  Fprintf(stderr, "Error:  No match in call for pin %s\n", obpinname);
-		  break;
-	       }
+		  char localnet[100];
 
-	       if (GetBus(scan->net, &wb) == 0) {
+		  /* Assume an implicit unconnected pin */
+		  sprintf(localnet, "_noconnect_%d_", localcount++);
+		  Node(localnet);
+		  join(localnet, obptr->name);
+		  Fprintf(stderr, "Note:  Implicit pin %s\n", obpinname);
+	       }
+	       else if (GetBus(scan->net, &wb) == 0) {
+		   char *bptr2;
 		   char *scanroot;
 		   scanroot = strsave(scan->net);
-		   brackptr = strchr(scanroot, '[');
+		   brackptr = strvchr(scanroot, '[');
 		   if (brackptr) *brackptr = '\0';
 
 		   if (arraystart == -1) {
@@ -1854,16 +1984,37 @@ nextinst:
 		   else {
 		       // Instance must be an array
 		       char netname[128];
-		       int slice;
-		       if (wb.start >= wb.end && arraystart >= arrayend)
-			   slice = wb.start - (arraystart - i);
-		       else if (wb.start < wb.end && arraystart > arrayend)
-			   slice = wb.start + (arraystart - i);
-		       else if (wb.start > wb.end && arraystart < arrayend)
-			   slice = wb.start - (arraystart + i);
-		       else // (wb.start < wb.end && arraystart < arrayend)
-			   slice = wb.start + (arraystart + i);
-			   
+		       int slice, portlen, siglen;
+
+		       /* Get the array size of the port for bit slicing */
+		       portlen = (scan->width < 0) ? 1 : scan->width;
+
+		       /* Get the full array size of the connecting bus */
+		       GetBus(scanroot, &wb2);
+		       siglen = wb2.start - wb2.end;
+		       if (siglen < 0) siglen = -siglen;
+		       siglen++;
+
+		       // If signal array is smaller than the portlength *
+		       // length of instance array, then the signal wraps.
+
+		       if (wb2.start >= wb2.end && arraystart >= arrayend) {
+			   slice = wb.start - (arraystart - i) * portlen;
+			   while (slice < wb2.end) slice += siglen;
+		       }
+		       else if (wb2.start < wb2.end && arraystart > arrayend) {
+			   slice = wb.start + (arraystart - i) * portlen;
+			   while (slice > wb2.end) slice -= siglen;
+		       }
+		       else if (wb2.start > wb2.end && arraystart < arrayend) {
+			   slice = wb.start - (arraystart + i) * portlen;
+			   while (slice < wb2.end) slice += siglen;
+		       }
+		       else { // (wb2.start < wb2.end && arraystart < arrayend)
+			   slice = wb.start + (arraystart + i) * portlen;
+			   while (slice > wb2.end) slice -= siglen;
+		       }
+
 		       sprintf(netname, "%s[%d]", scanroot, slice);
 	               if (LookupObject(netname, CurrentCell) == NULL) Node(netname);
 	               join(netname, obptr->name);
@@ -1931,14 +2082,21 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
   CurrentCell = NULL;
 
   if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
-    char name[100];
 
-    SetExtension(name, fname, VERILOG_EXTENSION);
-    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
-      Fprintf(stderr,"Error in Verilog file read: No file %s\n",name);
-      *fnum = filenum;
-      return NULL;
+    if (strchr(fname, '.') == NULL) {
+      char name[1024];
+      SetExtension(name, fname, VERILOG_EXTENSION);
+      if ((filenum = OpenParseFile(name, *fnum)) < 0) {
+        Fprintf(stderr, "Error in Verilog file read: No file %s\n", name);
+        *fnum = filenum;
+        return NULL;
+      }
     }    
+    else {
+       Fprintf(stderr, "Error in Verilog file read: No file %s\n", fname);
+       *fnum = filenum;
+       return NULL;
+    }
   }
 
   /* All Verilog file reading is case sensitive.  However:  if	*/
@@ -1949,6 +2107,11 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
      Printf("Warning:  A case-insensitive file has been read and so the	"
 		"verilog file must be treated case-insensitive to match.\n");
   }
+  else {
+     matchfunc = match;
+     matchintfunc = matchfile;
+     hashfunc = hash;
+  }
 
   InitializeHashTable(&verilogparams, OBJHASHSIZE);
   InitializeHashTable(&verilogdefs, OBJHASHSIZE);
@@ -2036,11 +2199,15 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
 	if (strchr(fname, '.') == NULL) {
            SetExtension(name, fname, VERILOG_EXTENSION);
            filenum = OpenParseFile(name, parent);
+	   if (filenum < 0) {
+	      fprintf(stderr,"Error in Verilog file include: No file %s\n", name);
+	      return;
+	   }
         }
-	if (filenum < 0) {
+	else {
 	   fprintf(stderr,"Error in Verilog file include: No file %s\n", fname);
 	   return;
-        }    
+        }
      }
   }
   ReadVerilogFile(fname, parent, CellStackPtr, blackbox);

doc/Makefile

@@ -2,11 +2,11 @@ NETGENDIR = ..
 
 include ${NETGENDIR}/defs.mak
 
-MANDIRS = $(DESTDIR)${MANDIR} $(DESTDIR)${MANDIR}/man1
-DOCDIRS = $(DESTDIR)${DOCDIR}
+MANDIRS = $(DESTDIR)${INSTALL_MANDIR} $(DESTDIR)${INSTALL_MANDIR}/man1
+DOCDIRS = $(DESTDIR)${INSTALL_DOCDIR}
 
 MANFILES = 
-DOCFILES = $(DESTDIR)${DOCDIR}/netgen.doc
+DOCFILES = $(DESTDIR)${INSTALL_DOCDIR}/netgen.doc
 
 install-tcl: ${DOCDIRS} ${DOCFILES}
 
@@ -23,8 +23,8 @@ make-doc-dirs:
 	${SCRIPTS}/mkdirs ${DOCDIRS}
 
 # This file does not actually exist. . .
-$(DESTDIR)${MANDIR}/man1/netgen.1: netgen.1 ${MANDIRS}
-	${CP} netgen.1 $(DESTDIR)${MANDIR}/man1/netgen.1
+$(DESTDIR)${INSTALL_MANDIR}/man1/netgen.1: netgen.1 ${MANDIRS}
+	${CP} netgen.1 $(DESTDIR)${INSTALL_MANDIR}/man1/netgen.1
 
-$(DESTDIR)${DOCDIR}/netgen.doc: netgen.doc ${DOCDIRS}
-	${CP} netgen.doc $(DESTDIR)${DOCDIR}/netgen.doc
+$(DESTDIR)${INSTALL_DOCDIR}/netgen.doc: netgen.doc ${DOCDIRS}
+	${CP} netgen.doc $(DESTDIR)${INSTALL_DOCDIR}/netgen.doc

lib/Makefile

@@ -4,14 +4,14 @@ include ${NETGENDIR}/defs.mak
 
 LIB_FILES = ntk2adl.sh spice spice.bot spice.top
 
-LIB_INST_FILES= $(LIB_FILES:%=$(DESTDIR)${LIBDIR}/netgen/%)
-BIN_INST_FILES= $(BIN_FILES:%=$(DESTDIR)${BINDIR}/%)
+LIB_INST_FILES= $(LIB_FILES:%=$(DESTDIR)${INSTALL_LIBDIR}/netgen/%)
+BIN_INST_FILES= $(BIN_FILES:%=$(DESTDIR)${INSTALL_BINDIR}/%)
 
 install-tcl: ${LIB_INST_FILES}
 
 install: ${LIB_INST_FILES}
 
-$(DESTDIR)${LIBDIR}/netgen/%: %
-	../scripts/mkdirs $(DESTDIR)${LIBDIR}/netgen
-	${RM} $(DESTDIR)${LIBDIR}/netgen/$*
-	${CP} $* $(DESTDIR)${LIBDIR}/netgen/$*
+$(DESTDIR)${INSTALL_LIBDIR}/netgen/%: %
+	../scripts/mkdirs $(DESTDIR)${INSTALL_LIBDIR}/netgen
+	${RM} $(DESTDIR)${INSTALL_LIBDIR}/netgen/$*
+	${CP} $* $(DESTDIR)${INSTALL_LIBDIR}/netgen/$*

netgen/Makefile

@@ -25,23 +25,23 @@ tclnetgen${SHDLIB_EXT}: ${EXTRA_LIBS}
 		${LD_RUN_PATH} ${EXTRA_LIBS} ${LD_EXTRA_LIBS} \
 		-lc ${LIBS} ${LIB_SPECS} ${LDFLAGS}
 
-$(DESTDIR)${BINDIR}/netgen:
+$(DESTDIR)${INSTALL_BINDIR}/netgen:
 	${RM} $@
 	${CP} netgen $@
 
-$(DESTDIR)${BINDIR}/ntk2adl:
+$(DESTDIR)${INSTALL_BINDIR}/ntk2adl:
 	${RM} $@
 	${CP} ntk2adl $@
 
-$(DESTDIR)${BINDIR}/ntk2xnf:
+$(DESTDIR)${INSTALL_BINDIR}/ntk2xnf:
 	${RM} $@
 	${CP} ntk2xnf $@
 
-$(DESTDIR)${BINDIR}/netcomp:
+$(DESTDIR)${INSTALL_BINDIR}/netcomp:
 	${RM} $@
 	${CP} netcomp $@
 
-$(DESTDIR)${BINDIR}/inetcomp:
+$(DESTDIR)${INSTALL_BINDIR}/inetcomp:
 	${RM} $@
 	${CP} inetcomp $@
 
@@ -61,14 +61,14 @@ ntk2xnf: ntk2xnf.c
 	${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS} ntk2xnf.c -o $@ ${EXTRA_LIBS} \
 		${LIBS} ${LDFLAGS}
 
-install: $(DESTDIR)${BINDIR}/netgen $(DESTDIR)${BINDIR}/netcomp \
-		$(DESTDIR)${BINDIR}/inetcomp $(DESTDIR)${BINDIR}/ntk2adl \
-		$(DESTDIR)${BINDIR}/ntk2xnf
+install: $(DESTDIR)${INSTALL_BINDIR}/netgen $(DESTDIR)${INSTALL_BINDIR}/netcomp \
+		$(DESTDIR)${INSTALL_BINDIR}/inetcomp $(DESTDIR)${INSTALL_BINDIR}/ntk2adl \
+		$(DESTDIR)${INSTALL_BINDIR}/ntk2xnf
 
-install-tcl: $(DESTDIR)${TCLDIR} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
+install-tcl: $(DESTDIR)${INSTALL_TCLDIR} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
 
-$(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}: tclnetgen${SHDLIB_EXT}
-	${RM} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
-	${CP} tclnetgen${SHDLIB_EXT} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
+$(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}: tclnetgen${SHDLIB_EXT}
+	${RM} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
+	${CP} tclnetgen${SHDLIB_EXT} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
 
 include ${NETGENDIR}/rules.mak

python/Makefile

@@ -4,7 +4,7 @@ SRCS =
 SCRIPTS = consoletext.py helpwindow.py lvs_manager.py treeviewsplit.py
 SCRIPTS += tksimpledialog.py tooltip.py lvs_help.txt
 
-SCRIPTINSTALL = $(DESTDIR)${PYDIR}
+SCRIPTINSTALL = $(DESTDIR)${INSTALL_PYDIR}
 
 include ${NETGENDIR}/defs.mak
 
@@ -12,11 +12,11 @@ main: lvs_manager.py
 
 tcl-main: lvs_manager.py
 
-$(DESTDIR)${PYDIR}/consoletext.py:
+$(DESTDIR)${INSTALL_PYDIR}/consoletext.py:
 	${RM} $@
 	${CP} consoletext.py $@
 
-$(DESTDIR)${PYDIR}/helpwindow.py:
+$(DESTDIR)${INSTALL_PYDIR}/helpwindow.py:
 	${RM} $@
 	${CP} helpwindow.py $@
 
@@ -24,31 +24,31 @@ lvs_manager.py: lvs_manager.py.in
 	sed -e '/SUBST_SCRIPT_DIR/s#SUBST_SCRIPT_DIR#$(SCRIPTINSTALL)#' \
 		lvs_manager.py.in > lvs_manager.py
 
-$(DESTDIR)${PYDIR}/lvs_manager.py: lvs_manager.py
+$(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py: lvs_manager.py
 	${RM} $@
 	${CP} lvs_manager.py $@
 
-$(DESTDIR)${PYDIR}/treeviewsplit.py: treeviewsplit.py
+$(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py: treeviewsplit.py
 	${RM} $@
 	${CP} treeviewsplit.py $@
 
-$(DESTDIR)${PYDIR}/tksimpledialog.py: tksimpledialog.py
+$(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py: tksimpledialog.py
 	${RM} $@
 	${CP} tksimpledialog.py $@
 
-$(DESTDIR)${PYDIR}/tooltip.py: tooltip.py
+$(DESTDIR)${INSTALL_PYDIR}/tooltip.py: tooltip.py
 	${RM} $@
 	${CP} tooltip.py $@
 
-$(DESTDIR)${PYDIR}/lvs_help.txt: lvs_help.txt
+$(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt: lvs_help.txt
 	${RM} $@
 	${CP} lvs_help.txt $@
 
 install: install-tcl
 
-install-tcl: $(DESTDIR)${PYDIR} $(DESTDIR)${PYDIR}/consoletext.py \
-	$(DESTDIR)${PYDIR}/helpwindow.py $(DESTDIR)${PYDIR}/lvs_manager.py \
-	$(DESTDIR)${PYDIR}/treeviewsplit.py $(DESTDIR)${PYDIR}/tksimpledialog.py \
-	$(DESTDIR)${PYDIR}/tooltip.py $(DESTDIR)${PYDIR}/lvs_help.txt
+install-tcl: $(DESTDIR)${INSTALL_PYDIR} $(DESTDIR)${INSTALL_PYDIR}/consoletext.py \
+	$(DESTDIR)${INSTALL_PYDIR}/helpwindow.py $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py \
+	$(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py $(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py \
+	$(DESTDIR)${INSTALL_PYDIR}/tooltip.py $(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt
 
 include ${NETGENDIR}/rules.mak

scripts/configure

@@ -633,6 +633,7 @@ gr_srcs
 gr_libs
 gr_dflags
 gr_cflags
+DIST_DIR
 cadinstall
 programs
 unused
@@ -734,6 +735,7 @@ ac_subst_files=''
 ac_user_opts='
 enable_option_checking
 with_gnu_ld
+with_distdir
 with_interpreter
 with_tcl
 with_tk
@@ -1372,6 +1374,7 @@ Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
   --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
   --with-gnu-ld           assume the C compiler uses GNU ld [default=no]
+  --with-distdir=DIR       install into location DIR for distribution
   --with-interpreter=arg	enable interpreter
   --with-tcl=DIR          Find tclConfig.sh in DIR
   --with-tk=DIR           Find tkConfig.sh in DIR
@@ -4798,6 +4801,24 @@ usingTcl=1
 usingX11=
 
 
+# For distributed installs, where the run-time files are installed in a
+# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
+# the prefix is replaced by the destination directory, rather than appended
+# to it.
+DIST_DIR="\${exec_prefix}"
+
+# Check whether --with-distdir was given.
+if test "${with_distdir+set}" = set; then :
+  withval=$with_distdir;
+  if test "$withval" = "no" -o "$withval" = "NO" ; then
+     DIST_DIR="\${exec_prefix}"
+  else
+     DIST_DIR=${withval}
+  fi
+
+fi
+
+
 
 # Check whether --with-interpreter was given.
 if test "${with_interpreter+set}" = set; then :
@@ -6587,6 +6608,7 @@ fi
 
 
 
+
 
 
 ac_config_files="$ac_config_files defs.mak"

scripts/configure.in

@@ -249,6 +249,20 @@ usingX11=
 
 dnl Compile-time options below. . .
 
+# For distributed installs, where the run-time files are installed in a
+# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
+# the prefix is replaced by the destination directory, rather than appended
+# to it.
+DIST_DIR="\${exec_prefix}"
+AC_ARG_WITH(distdir,
+[  --with-distdir=DIR       install into location DIR for distribution], [
+  if test "$withval" = "no" -o "$withval" = "NO" ; then
+     DIST_DIR="\${exec_prefix}"
+  else
+     DIST_DIR=${withval}
+  fi
+], )
+
 AC_ARG_WITH(interpreter,
 [  --with-interpreter=[arg]	enable interpreter], [
   if test "$withval" = "no" -o "$withval" = "NO"; then
@@ -1272,6 +1286,7 @@ AC_SUBST(modules)
 AC_SUBST(unused)
 AC_SUBST(programs)
 AC_SUBST(cadinstall)
+AC_SUBST(DIST_DIR)
 
 AC_SUBST(gr_cflags)
 AC_SUBST(gr_dflags)

scripts/defs.mak.in

@@ -35,6 +35,13 @@ DOCDIR                 = ${libdir}/netgen/doc
 TCLDIR                 = ${libdir}/netgen/tcl
 PYDIR		       = ${libdir}/netgen/python
 
+INSTALL_BINDIR                 = @DIST_DIR@/bin
+INSTALL_MANDIR                 = @DIST_DIR@/share/man
+INSTALL_LIBDIR                 = @DIST_DIR@/lib
+INSTALL_DOCDIR                 = ${INSTALL_LIBDIR}/netgen/doc
+INSTALL_TCLDIR                 = ${INSTALL_LIBDIR}/netgen/tcl
+INSTALL_PYDIR		       = ${INSTALL_LIBDIR}/netgen/python
+
 MAIN_EXTRA_LIBS        = @extra_libs@
 LD_EXTRA_LIBS          = @ld_extra_libs@
 LD_SHARED              = @ld_extra_objs@

tcltk/Makefile

@@ -12,20 +12,20 @@ CLEANS += netgen.sh netgen.tcl netgenexec${EXEEXT}
 CFLAGS += -I${NETGENDIR}/base
 
 TCL_FILES = \
-	$(DESTDIR)${TCLDIR}/tkcon.tcl \
-	$(DESTDIR)${TCLDIR}/console.tcl \
-	$(DESTDIR)${TCLDIR}/netgen.tcl
+	$(DESTDIR)${INSTALL_TCLDIR}/tkcon.tcl \
+	$(DESTDIR)${INSTALL_TCLDIR}/console.tcl \
+	$(DESTDIR)${INSTALL_TCLDIR}/netgen.tcl
 
 tcl-main: netgenexec${EXEEXT} netgen.tcl netgen.sh
 
-install-tcl: netgenexec${EXEEXT} $(DESTDIR)${BINDIR}/netgen.sh ${TCL_FILES}
-	${RM} $(DESTDIR)${TCLDIR}/netgenexec${EXEEXT}
-	${CP} netgenexec${EXEEXT} $(DESTDIR)${TCLDIR}/netgenexec${EXEEXT}
+install-tcl: netgenexec${EXEEXT} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh ${TCL_FILES}
+	${RM} $(DESTDIR)${INSTALL_TCLDIR}/netgenexec${EXEEXT}
+	${CP} netgenexec${EXEEXT} $(DESTDIR)${INSTALL_TCLDIR}/netgenexec${EXEEXT}
 
 netgenexec${EXEEXT}: netgenexec.c
 	${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS_NOSTUB} netgenexec.c \
 		-o netgenexec${EXEEXT} \
-		${LDFLAGS} ${LIBS} ${LIB_SPECS_NOSTUB}
+		${LIB_SPECS_NOSTUB} ${LDFLAGS} ${LIBS} ${GR_LIBS}
 
 netgen.tcl: netgen.tcl.in
 	sed -e 's%TCL_DIR%${TCLDIR}%g' \
@@ -39,13 +39,13 @@ netgen.sh: netgen.sh.in
 	    -e 's%WISH_EXE%${WISH_EXE}%g' \
 	    netgen.sh.in > netgen.sh
 
-$(DESTDIR)${TCLDIR}/%: %
-	${RM} $(DESTDIR)${TCLDIR}/$*
-	${CP} $* $(DESTDIR)${TCLDIR}/$*
+$(DESTDIR)${INSTALL_TCLDIR}/%: %
+	${RM} $(DESTDIR)${INSTALL_TCLDIR}/$*
+	${CP} $* $(DESTDIR)${INSTALL_TCLDIR}/$*
 
-$(DESTDIR)${BINDIR}/netgen.sh: netgen.sh
-	${RM} $(DESTDIR)${BINDIR}/netgen.sh $(DESTDIR)${BINDIR}/netgen
-	${CP} netgen.sh $(DESTDIR)${BINDIR}/netgen
-	(cd $(DESTDIR)${BINDIR}; chmod 0755 netgen)
+$(DESTDIR)${INSTALL_BINDIR}/netgen.sh: netgen.sh
+	${RM} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh $(DESTDIR)${INSTALL_BINDIR}/netgen
+	${CP} netgen.sh $(DESTDIR)${INSTALL_BINDIR}/netgen
+	(cd $(DESTDIR)${INSTALL_BINDIR}; chmod 0755 netgen)
 
 include ${NETGENDIR}/rules.mak

tcltk/netgen.tcl.in

@@ -138,7 +138,7 @@ proc netgen::convert_to_json {filename lvs_final} {
 		     foreach net $cktval {
 			incr nidx
 	                puts $fjson "          \["
-			set netname [string map {"\\" ""} [lindex $net 0]]
+			set netname [string map {"\\" "\\\\"} [lindex $net 0]]
 		        puts $fjson "            \"$netname\","
 		        puts $fjson "            \["
 			set netconn [lindex $net 1]
@@ -169,7 +169,7 @@ proc netgen::convert_to_json {filename lvs_final} {
 		     foreach net $cktval {
 			incr nidx
 	                puts $fjson "          \["
-			set netname [string map {"\\" ""} [lindex $net 0]]
+			set netname [string map {"\\" "\\\\"} [lindex $net 0]]
 		        puts $fjson "            \"$netname\","
 		        puts $fjson "            \["
 			set netconn [lindex $net 1]
@@ -221,7 +221,7 @@ proc netgen::convert_to_json {filename lvs_final} {
 		     foreach inst $cktval {
 			incr iidx
 	                puts $fjson "          \["
-			set instname [lindex $inst 0]
+			set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
 		        puts $fjson "            \"$instname\","
 		        puts $fjson "            \["
 			set instpins [lindex $inst 1]
@@ -250,7 +250,7 @@ proc netgen::convert_to_json {filename lvs_final} {
 		     foreach inst $cktval {
 			incr iidx
 	                puts $fjson "          \["
-			set instname [lindex $inst 0]
+			set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
 		        puts $fjson "            \"$instname\","
 		        puts $fjson "            \["
 			set instpins [lindex $inst 1]
@@ -292,8 +292,8 @@ proc netgen::convert_to_json {filename lvs_final} {
 		  foreach instance $value {
 		     incr pidx
 	             puts $fjson "      \["
-		     set instnames [lindex $instance 0]
-		     set instname0 [lindex $instnames 0]
+		     set instnames [string map {"\\" "\\\\"} [lindex $instance 0]]
+		     set instname0 [string map {"\\" "\\\\"} [lindex $instnames 0]]
 	             puts $fjson "         \["
 		     puts $fjson "           \"${instname0}\","
 	             puts $fjson "           \["
@@ -310,7 +310,7 @@ proc netgen::convert_to_json {filename lvs_final} {
 		     puts $fjson "             \[\"${propname}\", \"${propval}\"\]"
 	             puts $fjson "           \]"
 	             puts $fjson "         \],"
-		     set instname1 [lindex $instnames 1]
+		     set instname1 [string map {"\\" "\\\\"} [lindex $instnames 1]]
 	             puts $fjson "         \["
 		     puts $fjson "           \"${instname1}\","
 	             puts $fjson "           \["
@@ -501,6 +501,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       return
    }
    set properr {}
+   set pinsgood 0
    while {$endval != {}} {
       if {$dolist == 1} {
          netgen::run -list converge
@@ -546,6 +547,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
+	    set pinsgood $result
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
@@ -569,7 +571,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    netgen::log echo off
    puts stdout "Result: " nonewline
    netgen::log echo on
-   verify only
+   if {$pinsgood == 0} {
+      netgen::log put "The top level cell failed pin matching.\n"
+   } else {
+      verify only
+   }
    if {$properr != {}} {
       netgen::log put "The following cells had property errors: $properr\n"
    }

tcltk/tclnetgen.c

@@ -85,6 +85,7 @@ int _netcmp_compare(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_iterate(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_summary(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_print(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
+int _netcmp_format(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_run(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_verify(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_automorphs(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -199,6 +200,9 @@ Command netcmp_cmds[] = {
 	{"print",		_netcmp_print,
 		"\n   "
 		"print netcomp internal data structure"},
+	{"format",		_netcmp_format,
+		"<col1_width> <col2_width>\n   "
+		"set width of formatted output"},
 	{"run",			_netcmp_run,
 		"[converge|resolve]\n   "
 		"converge: run netcomp to completion (convergence)\n   "
@@ -1528,23 +1532,24 @@ int
 _netgen_model(ClientData clientData,
     Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
 {
-   struct nlist *tp;
+   struct nlist *tp, *tp2;
    char *model, *retclass;
    unsigned char class;
    int fnum = -1;
-   int result, index, nports;
+   int result, index, nports, nports2;
 
    char *modelclasses[] = {
       "undefined", "nmos", "pmos", "pnp", "npn",
       "resistor", "capacitor", "diode",
       "inductor", "module", "blackbox", "xline",
-      "moscap", "mosfet", "bjt", "subcircuit", NULL
+      "moscap", "mosfet", "bjt", "subcircuit", "copy",
+      NULL
    };
    enum OptionIdx {
       UNDEF_IDX,  NMOS_IDX, PMOS_IDX, PNP_IDX, NPN_IDX,
       RES_IDX, CAP_IDX, DIODE_IDX, INDUCT_IDX,
       MODULE_IDX, BLACKBOX_IDX, XLINE_IDX, MOSCAP_IDX,
-      MOSFET_IDX, BJT_IDX, SUBCKT_IDX
+      MOSFET_IDX, BJT_IDX, SUBCKT_IDX, COPY_IDX
    };
 
    if (objc != 3 && objc != 2) {
@@ -1576,7 +1581,7 @@ _netgen_model(ClientData clientData,
 
    if (objc == 3) {
       model = Tcl_GetString(objv[2]);
-      nports = NumberOfPorts(model);
+      nports = NumberOfPorts(model, fnum);
 
       if (Tcl_GetIndexFromObj(interp, objv[2], (CONST84 char **)modelclasses,
 		"class", 0, &index) != TCL_OK) {
@@ -1640,6 +1645,40 @@ _netgen_model(ClientData clientData,
 	    break;
 	 case SUBCKT_IDX:
 	    class = CLASS_SUBCKT;
+	    break;
+	 case COPY_IDX:
+	    /* "copy" is not a class, but indicates that the cell,  */
+	    /* if undefined or a module, should have its class	    */
+	    /* taken from the other circuit, if that circuit has a  */
+	    /* cell of the same name.				    */
+	    if (Circuit1 == NULL || Circuit2 == NULL) {
+		Tcl_SetResult(interp, "Circuits have not been queued for comparison.",
+			NULL);
+		return TCL_ERROR;
+	    }
+	    if (tp == Circuit1) {
+		tp2 = LookupCellFile(tp->name, Circuit2->file);
+		nports2 = NumberOfPorts(tp2->name, Circuit2->file);
+	    }
+	    else if (tp == Circuit2) {
+		tp2 = LookupCellFile(tp->name, Circuit1->file);
+		nports2 = NumberOfPorts(tp2->name, Circuit1->file);
+	    }
+	    else {
+		Tcl_SetResult(interp, "The referenced netlist is not being compared.",
+			NULL);
+		return TCL_ERROR;
+	    }
+	    /* Should a non-matching number of ports be considered a fatal error? */
+	    // if (nports2 != nports) {
+	    //	Tcl_SetResult(interp, "The number of ports for this cell does not "
+	    //		"match between netlists.", NULL);
+	    //	return TCL_ERROR;
+	    // }
+
+	    class = tp2->class;
+	    /* To do (maybe): Rename tp ports to match tp2? */
+
 	    break;
       }
       tp->class = class;
@@ -1971,6 +2010,61 @@ _netgen_printmem(ClientData clientData,
 }
 #endif
 
+/*------------------------------------------------------*/
+/* Function name: _netcmp_format			*/
+/* Syntax:						*/
+/*    netgen::format [col1_width [col2_width]]		*/
+/* Formerly: (none)					*/
+/* Results:						*/
+/* Side Effects:					*/
+/*------------------------------------------------------*/
+
+int
+_netcmp_format(ClientData clientData,
+    Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
+{
+    int col1_width = 41, col2_width = 41;
+
+    if (objc > 1) {
+	if (Tcl_GetIntFromObj(interp, objv[1], &col1_width) != TCL_OK)
+	    return TCL_ERROR;
+	if (objc > 2) {
+	    if (Tcl_GetIntFromObj(interp, objv[2], &col2_width) != TCL_OK)
+		return TCL_ERROR;
+	} else {
+	    /* If only one argument is given, then apply it to both columns */
+	    col2_width = col1_width;
+	}
+
+	if (col1_width <= 0 || col2_width <= 0) {
+	    Tcl_SetResult(interp, "Column width cannot be zero or less\n", NULL);
+	}
+
+	// Default values for left and right columns are 43 and 87
+	left_col_end = col1_width + 2;
+	right_col_end = left_col_end + col2_width + 3;
+    }
+    else if (objc == 1) {
+	Tcl_Obj *lobj, *tobj;
+
+	col1_width = left_col_end - 2;
+	col2_width = right_col_end - col1_width - 5;
+
+	lobj = Tcl_NewListObj(0, NULL);
+
+	tobj = Tcl_NewIntObj(col1_width);
+        Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col1_width));
+        Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col2_width));
+
+	Tcl_SetObjResult(interp, lobj);
+	return TCL_OK;
+    }
+    else {
+	Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
+	return TCL_ERROR;
+    }
+}
+
 /*------------------------------------------------------*/
 /* The following code breaks up the NETCOMP() command	*/
 /* from netcmp.c into individual functions w/arguments	*/
@@ -2900,15 +2994,34 @@ _netcmp_equate(ClientData clientData,
 
       case PINS_IDX:
 	 if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
-	    if (CurrentCell == NULL)
+	    if (CurrentCell == NULL) {
 		Fprintf(stderr, "Equate elements:  no current cell.\n");
-	    Fprintf(stderr, "Equate pins:  cell %s and/or %s has no elements.\n",
-			name1, name2);
-	    Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
-	    return TCL_OK;
+		Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
+		return TCL_OK;
+	    }
+	    else if ((tp1->flags & CELL_PLACEHOLDER) ||
+			(tp2->flags & CELL_PLACEHOLDER)) {
+		if (tp1->flags & CELL_PLACEHOLDER) {
+		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
+			"has no definition, treated as a black box.\n", name1);
+		}
+		if (tp2->flags & CELL_PLACEHOLDER) {
+		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
+			"has no definition, treated as a black box.\n", name2);
+		}
+		// If a cell in either circuit is marked as a black box, then
+		// the cells in both circuits should be marked as a black box.
+		tp1->flags |= CELL_PLACEHOLDER;
+		tp2->flags |= CELL_PLACEHOLDER;
+	    }
+	    else {
+		Fprintf(stdout, "Equate pins:  cell %s and/or %s "
+			"has no elements.\n", name1, name2);
+		/* This is not necessarily an error, so go ahead and match pins. */
+	    }
 	 }
-	 else if (ElementClasses == NULL) {
-	    /* This has been called outside of a netlist compare,	*/
+	 if (ElementClasses == NULL) {
+	    /* This may have been called outside of a netlist compare,	*/
 	    /* probably to force name matching of pins on black-box	*/
 	    /* devices.  But MatchPins only works if tp1 == Circuit1	*/
 	    /* and tp2 == Circuit2, so preserve these values and 	*/