to go into an infinite loop and fill memory until it crashes, due
to a complete pin mismatch between devices causing one device to
have its pins removed and replaced with proxy pins.
was running through the entire object linked list to find the
predecessor of a record that it had already found. Solved by simply
keeping track of the predecessor record.
format files to the SPICE parser, so that netgen can be run
directly on a testbench file and not generate errors due to
statements in the control block.
I have a design that is taking quite a long time for netgen to complete LVS
checking. Profiles show a large chunk of runtime is in the hash functions.
Some of the hashtables are very sparsely populated, but others are
heavily used. One hashtable has chains of over 250. Longer term it would
be worth investigating resizing the hashtables (or perhaps using other
data strutures), but for now I looked at what changing the number of
hash buckets (OBJHASHSIZE) does for performance:
OBJHASHSIZE time (mm:ss)
997 24:18
10093 4:42
42073 3:12
104729 2:51
I somewhat arbitrarily chose 42073 which gives us a 7.6x improvement in
runtime.
file input so that pins occur first before nodes, as they do in a
SPICE netlist. Certain parts of the comparison code depend on pins
being first in the netlist, and reordering them when reading input
is easier than rewriting the rest of the code.
The previous script would swallow the exit code of the `./configure`
script and thus it looked like doing a configure always succeeded.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
introduced in revision 150 can result in an incorrect result
reporting a bad match where the match is actually good (as proven
by running the full symmetry breaking on the same netlist).
Because the fast symmetry breaking is orders of magnitude faster
for large circuits, and because the false positive result appears
to be rare, I have introduced a command "symmetry" to switch
methods between fast and full. So fast symmetry breaking can be
run unless the result fails on symmetry breaking, in which case
the method can be switched to full to see if the problem is a
false positive or not. This is not an ideal solution, and some
investigation is needed to determine if there is a way to apply
fast symmetry breaking without encountering a false positive
error.
with the file number, so that it can get confused between libraries.
Also made a fix to coerce one cell class to be forced to be the
same in both circuits under some circumstances.
the top level circuits to be declared matching with no errors even
though the pins do not match. "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
corrected the error statement so that it refers both to the (corrected)
left-hand side and also the portion of the right-hand side that cannot
be parsed as structural verilog.
breaking by property was only matching properties between circuits but
not within the same circuit, which is needed for correct symmetry
breaking. But the PropertyMatch() routine assumed that it is passed
one item from each circuit, leading to a segfault when running the
symmetry breaking within a single circuit. This has been fixed.
that are not declared in the verilog netlist because they don't
connect to anything, and their presence is not required by verilog
syntax) and the printing of proxy pins created to act as placeholders
for those implicit pins. Also removed the pinting of the "disconnected
pin" messages for black-box modules (since by definition they have
disconnected pins, because black-box modules have no contents).
black-box circuits, especially those coming from verilog netlists
where a pin does not need to be declared and is implicitly floating.
This prevents the need to have an explicit black-box entry for any
verilog module that may have an instance that does not declare all
the pin connections. Also corrected an error which causes mysterious
failures if a verilog netlist is read before a SPICE netlist,
because the former gets hashed case-sensitive and the latter changes
the hashing to case-insensitive. Modified to force the SPICE
netlist to be treated case-sensitive, which may cause errors, but
is consistent with the reverse order handling, and doesn't cause
unexplained errors.
symmetry of all elements in all symmetric partitions, rather than
(as previously done) all elements in each partition, before re-
running iterations to convergence. This solves the problem of
having a very large number of partitions with a few elements each
taking a long time to run.
automorphisms so that it arbitrarily assigns all pairs from
circuit1 and circuit2 at once rather than assigning one pair at
a time and rerunning to convergence. I'm not sure of the validity
of this, other than that I have never seen a circuit fail to match
after resolving automorphisms, leading me to believe that the way
the symmetry breaking is done is irrelevant.
Tim Edwards
Alessandro De Laurenzis
Anton Blanchard
Tim 'mithro' Ansell