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test_bridge_rx_sim.py
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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test_bridge_tx_sim.py
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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test_config_export.py
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meta: replace Signal(1) with Signal()
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2026-01-19 16:31:12 -07:00 |
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test_ether_bridge_sim.py
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ethernet: bugfix in read transmit logic
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2026-01-02 14:10:19 -07:00 |
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test_ethernet_interface_hw.py
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ethernet: remove obsolete tests, fix naming
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2026-01-19 16:26:33 -07:00 |
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test_examples_build.py
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ethernet: add HWITL ethernet test
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2024-11-27 19:10:52 -07:00 |
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test_io_core_hw.py
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docs: autogenerate Python API docs, update IO core docs
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2024-10-08 11:42:10 -06:00 |
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test_io_core_sim.py
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meta: replace Signal(1) with Signal()
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2026-01-19 16:31:12 -07:00 |
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test_logic_analyzer_fsm_sim.py
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tests: refactor to use Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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test_logic_analyzer_hw.py
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docs: autogenerate Python API docs, update IO core docs
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2024-10-08 11:42:10 -06:00 |
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test_logic_analyzer_sim.py
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meta: replace Signal(1) with Signal()
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2026-01-19 16:31:12 -07:00 |
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test_mem_core_hw.py
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ethernet: add HWITL ethernet test
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2024-11-27 19:10:52 -07:00 |
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test_mem_core_sim.py
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meta: add pre-commit, commit changes it makes
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2024-11-27 19:10:52 -07:00 |
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test_uart_baud_mismatch.py
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uart: remove flaky nexys4ddr baudrate mismatch test case
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2024-10-08 11:42:10 -06:00 |
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test_uart_bridge_sim.py
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uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
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2026-01-19 16:29:09 -07:00 |
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test_uart_rx_sim.py
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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test_uart_tx_sim.py
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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test_verilog_gen.py
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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test_verilog_gen.yaml
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uart: fix #36, explicitly handle scientific notation in YAML config
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2025-04-06 18:28:29 -06:00 |
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