Fischer Moseley
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112bd43963
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remove mention of wdata/rdata
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d95ca04dd5
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move macro functions to tasks, update to
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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df2dbf4ec6
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update makefile to reflect new paths
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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07624d83ee
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move back to iverilog 13 compatability
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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925fd915be
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update simulation syntax for iverilog 11 compat
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1aa067b435
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update logic_analyzer_tb to use only generated HDL
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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a2ad90a66a
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modify sim and generator, seems to work in simulation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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353be7551e
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remove all narly verilog from python! 🤠
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2023-04-08 16:23:02 -04:00 |