Fischer Moseley
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59d960d79f
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docs: update Ethernet Interface
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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194dc4110d
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docs: update UART Interface
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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f69666407e
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docs: update layout and references for LogicAnalyzerCore docs
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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70f58b401b
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docs: update memory_core
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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6425bc3823
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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3036f6bbc2
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docs: document amaranth-based flow
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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20b4d6bdb8
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ethernet: move LiteEth core connections from Signals to IOPorts
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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42a219e3ec
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examples: make verilog/amaranth versions of uart_logic_analyzer match
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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e6de09ff1e
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tests: fix bug where base_addr was not passed but not used
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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528cb07673
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meta: fix circular imports
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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b8f25716f1
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docs: condense a few pages
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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2e54f40a77
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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Fischer Moseley
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b22cb900bb
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meta: switch from black to ruff
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2024-09-14 10:22:57 -07:00 |
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Fischer Moseley
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1310eac747
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cli: remove JSON loader, add test for instantiation generation
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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dc03184d2a
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deps: load liteeth from PyPI
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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5d22e0839c
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tests: include building examples in test suite
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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d02c5ccb5e
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formatting
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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3e7bd8f1a5
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manta: fix code generation from config file, update tests
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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da0429e8e4
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meta: expose Amaranth API via __all__
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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03d6ded25d
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ethernet: update __init__ away from config dict
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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d434e1b00f
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tests: fix mem_core_hw
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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c6926ae06e
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tests: fix logic_analyzer_sim
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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349cd214c7
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ci: check formatting with black
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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b66c7ea4b5
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tests: refactor to use Amaranth-native API
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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994a2e17cb
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logic analyzer: move __init__ away from config dict
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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92b685092a
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meta: add boilerplate for Amaranth-native API
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2024-09-14 10:22:32 -07:00 |
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Fischer Moseley
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59e77f07a0
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uart: update length checking to accomodate extra newlines
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2024-09-13 07:53:39 -06:00 |
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Fischer Moseley
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29727ffc96
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add newline every 32 read requests
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2024-09-13 07:53:39 -06:00 |
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Fischer Moseley
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19342c4735
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ci: add codecov.yml
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2024-09-10 17:33:55 -06:00 |
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Fischer Moseley
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236305729e
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ci: invoke codecov via Python, not from command line
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2024-09-10 15:21:41 -06:00 |
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Fischer Moseley
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3fb5bfb4ad
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ci: run codecov directly instead of via GitHub Action
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2024-09-10 13:45:40 -06:00 |
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Fischer Moseley
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354309394d
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meta: export JSON during tests for codecov to injest
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2024-09-10 10:09:56 -06:00 |
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Fischer Moseley
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129f991dda
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meta: add codecov
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2024-09-10 07:17:50 -06:00 |
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Fischer Moseley
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0715788ed7
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meta: update description in pyproject.toml
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2024-07-18 06:35:37 -07:00 |
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Fischer Moseley
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fd65d9a009
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meta: increment version to 1.0.1
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2024-07-18 06:34:34 -07:00 |
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Fischer Moseley
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24b4ca2468
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docs: add mention of CSV export from logic analyzer
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2024-07-17 19:47:18 -07:00 |
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Fischer Moseley
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f687f071dd
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cli: enable CSV export from logic analyzer capture
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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67103ad70e
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doc: remove warning about bidirectional mem cores on xilinx platforms
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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b87f8cbc48
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meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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753a3f9427
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meta: finish moving simulations to new async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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8fd943257c
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sim: update testbenches to async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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978937e4bc
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modify example design naming convention
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2024-05-12 10:25:00 -07:00 |
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Fischer Moseley
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6c25f6e8d3
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add sponsor button
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2024-05-11 11:52:35 -06:00 |
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Fischer Moseley
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7957e5d74e
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doc: change WaveDrom render branch to main
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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f6127791c7
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doc: add inline CSS to fix WaveDrom renders in dark mode
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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b35bfa1152
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doc: fix typo and migrate read timing diagram
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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697d6a00d9
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doc: directly render read transaction timing diagram
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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8da5b27010
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Merge pull request #17 from KennethWilke/main
add warning about reset polarity in Manta instance
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2024-04-06 00:50:19 -06:00 |
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Fischer Moseley
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7a44f34ae3
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tweak wording of active low reset warning
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2024-04-05 23:46:54 -07:00 |