Fischer Moseley
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a57b5908f2
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add verbose output to serial
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2023-03-23 18:10:52 -04:00 |
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Fischer Moseley
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500267798f
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add example instantiation to top of autogenerated output
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2023-03-19 10:57:32 -06:00 |
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Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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11495fca61
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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Fischer Moseley
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fade794333
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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Fischer Moseley
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aa2ba43e8f
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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3fda03ec90
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break up hdl definition into multiple member functinos
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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334aa8c005
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refactor __init__.py to be object-oriented
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5e2f02ebd6
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d9792702a
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |