fact that "extract all" does not enumerate cells from bottom up
as I had assumed---The order is roughly bottom-to-top, but cells
re-used in different places in the hierarchy could end up called
before one or more of their own subcells is extracted. Since
this conflicted with the preparation of the substrate in each
extracted subcircuit, I changed the method to enumerate cells so
that it is properly bottom-to-top. Also, methods were added to
"extract" (incremental), "extract cell", and "extract parents"
to ensure that the substrate is prepared on all subcells before
extraction.
extFindNodes() does; consequently, ExtLabelRegions() when called
after ExtFindRegions() may accidentally chain together a substrate
region with whatever was left in this linked list after the
previous call to extFindNodes(), with unpredictable results.
is specified in the extraction section of the techfile, then magic
will compute the effect of a nearby shape partially shielding the
sidewall overlap capacitance, which approaches 100% shielding as
the shapes converge to zero separation. This method prevents
magic from vastly overestimating the fringe capacitance of closely
spaced wires, which was magic's worst problem with parasitic
accuracy. The "fringeshieldhalo" value is the distance at which
the fringe shielding becomes negligible. Typically, it will be
about three times the distance at which half the fringe value is
shielded. It may be necessary at some point to make both the
fringe shielding halo and the sidewall halo values per-type values
(or per-plane, at least). For now, it should suffice to bring
Magic's parasitic extraction back in line with other tools.
not be seen during hierarchical processing, causing the substrate
to get split into several names that may conflict in the netlist.
At issue is the fact that ExtLabelRegions() will not attach a
default substrate label to a default substrate region. This may
need further untangling, as extFindNodes() will set the default
substrate node and is sometimes followed by ExtLabelRegions(),
which will label it. Any place ExtFindRegions() is called, this
could be an issue.
Most of this had to do with the incorrect use of the parent's substrate
name in extHierSubstrate(). After the correction, there still remains
an issue that is caused when a labeled isolated substrate region overlaps
an extraction tile boundary. I believe that this particular error has
existed for some time and is not new, so I am committing these changes.
which had become fouled up due to the changes in the way that the
substrate is defined and handled. Worked through a large torture
test until all types of substrate coupling and overlap shielding
were resolved to be extracted as expected.
a routine that should have been called with a NULL argument, but
instead was called with no argument, making the behavior system-
dependent. Revised the parsing of the "defaultareacap" and
"defaultperimeter" statements in the tech file, such that the short
version of both statements gets automatic handling of the substrate
and isolated substrate areas; this goes back to the recent change
in extraction behavior to redefine the "substrate type" (e.g., pwell)
during extraction as defining isolated substrate areas, and not the
default substrate. The earlier code change dealt with problems
related to extracting nodes and regions, but did not consider how
parasitic capacitance was affected. This commit resolves that issue.
The extSubtree() routine cuts a layout into squares and extracts
each separately, checking for subcell interactions. In each
square it parses all labels looking for unconnected ones. This
section of code not only parses all labels M x N times, but it
then marks interaction areas where there may be none, forcing
additional unnecessary processing. This commit makes the first
quick optimization, which is to change the return value of
DRCFindInteractions() from boolean to integer, allowing it to
return a value indicating that there are no subcells in the
area. This prevents the loop through labels from happening in
cases where there can never be interactions. More to come.
effectively forcing the substrate type (e.g., "pwell") to be defined
as delineating isolated substrate areas only (e.g., pwell in deep nwell
or isosub a.k.a. subcut). It does so by erasing all of the substrate
type out of a cell prior to extraction before redrawing it in the
isolated areas. This avoids issues caused by pwell drawn in separate
unconnected areas of a cell, as these are removed and the area treated
as the default substrate everywhere. Has worked on all layouts tested
so far.
check for abstract views to determine how to handle the substrate
node. Running tests to check if this has any negative impact on
the extraction of abstract views that do not specify substrate
and well types.
traditionally been kept for backwards compatibility. However, the
operation of "ext2spice" and "ext2sim" as separate programs has
become extremely difficult to maintain, and so it has been dropped
in favor of folding both into the program as commands, as was done
a long time ago in the Tcl/Tk version.
the timestamp is updated after reading in CIF or GDS, and managed to
get the timestamp dirty flag to remain clear after reading when
"gds datestamp" is used. This includes a modification of the timestamp
update routine that only updates timestamps on a single file if only a
single file is being written.
file to generate a mask of all the types called out in the section
as being used for parasitic calculations (resistive and capacitive)
and device terminal types. This is supplemented with a list of all
types that are specified in the "connect" and "contact" sections as
connecting to something other than themselves. All remaining types
are considered non-electrical and removed from the list of types
that can be considered electrical nodes. This works a bit better
than the existing method of using "resist <types> None" to specify
non-electrical types, as it is backwardly-compatible to older tech
files. The upshot is that in the worst case, if a type needs to be
extracted as an electrical node but does not satisfy any of the
above criteria, then it should be added to the "resist" list, with
a resistance of 0 if necessary.
time ago by cleaning up excess usage of "equiv" lines in the .ext
file output. The hierarchical extraction code did not distinguish
between node names which were output and those that were not,
requiring a setting "extract do aliases" to force all node aliases
to be output with "equiv" statements. So hierarchical names
might be any alias, whether output or not, and "merge" and "cap"
lines might contain references to nodes that were not output,
causing them to be disconnected nodes. This fix handles the
"extract no aliases" (default) case by flagging node names that
are redundant and not output, and not creating hierarchical names
with them.
node representing the global substrate on cells that are abstract
views. Corrected a typecasting issue in ext2spice.c that throws
a compiler warning. Added another check for a cell being editable
when painting, which is a case that was not covered by the
previous code change to address the same issue.
Print the names of the tile types that are illegally overlapping. This
gives us a better idea of what is wrong, eg:
feedback add "Illegal overlap between obsm2 and m2 (types do not connect)" medium
"defaultareacap" and "defaultperimeter" statements in the technology
file. Now, the parser makes use of the configuration of the
substrate from the "substrate" line to generate a default list of
which types and planes represent the substrate, and which types and
planes represent shielding to the substrate. This solves an issue
with the use of substrate isolation layers (e.g., "isosub" in
sky130A), because its definition and usage created substrate shields
on two planes (well and dwell), while the syntax for "defaultareacap"
and "defaultperimeter" only allow one shielding plane to be defined.
value 1 after finding a substrate connecting type shielded (by deep
nwell, in the example) from the substrate, thus preventing the
search from processing any remaining substrate types. Solved by
changing the return value to zero to keep the search going.
record to the label structure to hold the port number. One major
issue stemming from this was reported in github issue #203 by Anton
Blanchard. This commit fixes that error.
clean up memory after running "ext2spice". There are apparently
still memory leaks somewhere, difficult to diagnose with valgrind,
but this fix removes the most substantial leakage and allows
"ext2spice" to be run continuously, at least for a while.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
connections through the substrate as the same node, and so will
not force different nodes names on the soft connection to be
unique. This should probably be selectable behavior. However, as
written, the "extract" command will always merge soft connections,
so giving them unique names just causes problems with "extract".
entries for "floating" labels. Otherwise it is possible for the
hierarchical checks to find the label in flattened geometry and
reference it, resulting in merge statements in an .ext file that
reference undeclared nodes, ultimately resulting in extflat
failing to perform the merge, and an incorrect netlist.
to eliminate all redundant names resulting from redundant labels.
Changed the behavior of "goto" so that it will find local names with
slashes, which are the result of using "flatten". A hierarchical
search is done first, as before, but on failure to find a subcell
component, the local cell is searched for the verbatim name.
statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file. This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
wrong, and it needs revisiting. This is the cause of a number of
negative capacitances appearing in the netlist (even after accounting
for overlap with subcircuits).
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
to be scaled twice when using the "extract style" command and with an
extraction style that uses micron units. The microns-to-internal
units conversion expects an unscaled result when calling
CIFGetOutputScale(), but except when loading a tech file for the
first time, this value is scaled, and causes the double scaling.
Fixed by unscaling the CIF output before reloading the extraction
style, then scaling it afterward.
necessarily a 1:1 correspondence from tile types to extracted
device names, and not necessarily a 1:1 correspondence in the other
direction, either. So the search for devices at the location given
by the .sim file has been loosened to look for any tile type at that
location. Matches are restricted to those in which the plane of the
type found is the same as the plane of the device recorded in the .sim
file; this prevents matching device like MiM caps that may be in the
same location as a device in another plane.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
behavior of keeping the same first record when merging two nodes.
This does not seem to have any effect on extraction output. But
since the order of nodes can make a difference and there is no
performance impact in the code change, I will keep it as-is.
optimization done in ExtFlat, which is to keep a count of the
number of different node names assigned to the node so that when
merging, the one with fewer nodes can be updated to match the one
with more nodes. Note: This change is made on the assumption
that the names for node1 and node2 are equally preferred.
Supposedly the first name in the node list is canonical, so if
node1 is preferred in any case, it may be necessary to move
the first item of the second list to the beginning (a minor code
change).
recursive loop and crash magic. Corrected a number of other issues
along the way, especially one where routines in EFantenna and extresist
make use of array EFDevTypes which was only created by ext2sim and
ext2spice, and freed when done. Having run extresist through valgrind,
there are still issues in the code.
for sticky labels making connections through the hierarchy. This
is only needed for some annoying layouts that put point-size labels
with no connecting geometry in cells, and causes magic to spent
excessive amounts of time searching through labels for any layout
that has lots of labels.
not restored until after all cells have been processed through
extraction. Otherwise, top-down connections can end up with
different generated names for the same node, resulting in a
disconnect in the netlist.
extracting substrate regions, due to failure to clean up the tagged
tiles after exiting a search due to finding a substrate type that
was not the global substrate.
subcells that do not have deep nwell. This commit handles the
case where the pwell region is explicitly marked with a layer
type. To do: Handle the case where the pwell region is implicit.
statement in a .ext file require that all aliases of a node name be
rehashed after a node merge, or else node loops can occur. Also
prevented statements of the form "equiv A A" from being output in
the .ext file, as they are useless.
The previous behavior was to generate hierarchical names for all
labels when copying contents of subcells. This is "safe" for
copying selections without accidentally shorting things through
labeling, but it can make a mess of the selection. Options are
now "select do labels" for the existing behavior, "select no labels"
to not show any labels, and "select simple labels" to show only the
root name of labels in subcells.
unique will also be assigned a unique port index at the end of the
port list. That ensures that the unique names are all properly
found in the extracted .subckt for the cell.
asymmetric MOSFET definitions in the tech file "extract" section.
Corrected the nmos.tech.in file to put the resistance classes in
plane order, as otherwise the interpretation of which resistance
classes belongs to the transistor source and drain can get messed
up by the presence of buried contacts.
to stop the search whenever a cell is not found. Used this to implement
a new option for GDS writes, "gds undefined allow|disallow" (default
"disallow") controls whether or not GDS with undefined references will
be allowed to be written. Similarly affects CIF and LEF writes, extraction,
and DRC (when running "drc check" from the top).
restricted to its original intent, which is to replace the long name
formed from the plane short name and the "minfinity" coordinate.
This avoids issues with conflicting substrate names derived from a
real layer such as pwell. Also, the global substrate node name now
returns the variable name without the "$" in front if the variable
has not been set to anything. This avoids potential syntax errors
in the netlist.
one terminal of a device as the substrate, but also specifies
shielding types for the substrate, then the extraction cannot just
assume that a missing terminal is connected to the substrate without
first checking that there are no substrate shielding types under the
device.
could have multiple ports of the same name. This problem had been
worked over before, but there was an indpendent mechanism producing
the same result for a completely different reason, caused by subcells
being much larger than the cookie-cutter extraction method's extraction
regions. Solved by tracking port names in a hash table and preventing
re-use. (2) ext2spice was producing "no such node" errors; like (1)
this had been previously worked on, and like (1) this mechanism was
independent. Problem came from not passing -1 to extHierSubstrate for
the non-arrayed dimension of a 1-dimensional array. Also: Removed
the word "fatal" from extraction error reporting, as nearly all
extraction errors are entirely benign. This should clear up confusion
among alarmed end-users.
unique" code. It was using DBEraseLabelsByContent() which would
erase all matching labels, and could potentially erase labels that
were still remaining on the list being processed, causing a segfault.
Also corrected minor errors identified by valgrind during debugging
the above-referenced problem.
such that it looks for material connecting to the label at the
center point of the label and not the lower left corner. This keeps
the behavior of looking for tiles on the corners of a degenerate
label line or point between layers, but avoids problems with sticky
labels that are not quite aligned with the rectangle (due to certain
commercial EDA tools that have a sloppier notion of labeling).
p device; this was previously dependent only on the first character
of the extracted device model name. Since the tech file has control
over what the device layer names are but not the extracted model
names, the device layer type name is used as a backup way to determine
if the type is n or p, if that cannot be determined from the extracted
model name.
with two or more terminals other than the device identifier type
tied together) would fail if there were not a device record
specifically matching a one-S/D-terminal device. This is
inconsistent with past behavior, and so has been fixed.
because the opposite type (pwell) is not directly underneath the
gate, but touches it on the plane below. Because the pwell may
be represented by space tiles on the well plane, it was also
necessary to deal with the space type in the bitmask.
type in the device record, which was not updated at the end of
checking terminals for matching device extraction types. so the
boundary survey might see the wrong device type and generate an
incorrect boundary survey as a result.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
device layer type to describe the extraction for both a regular FET
and an extended-drain device. Note that the current code still
requires that the extended-drain device be declared first, and does
not check for this or attempt to reorder if incorrect.
supposed to pull "sticky labels" into the cumulative flattened
layout. Because it failed to check for the "sticky" flag, it
would copy all labels, causing extraction time to go exponential
as the number of labels in the design increases. Based on this
correction, the extHierConnectFunc1() routine should be able to
be optimized by stopping the search for sticky labels on the first
non-sticky label, since extSubtreeFunc() ensures that all sticky
labels come first in the label list.
the extractor was not checking temp_subsname as well as glob_subsname,
and so was failing to apply the substrate name to child cells in
"merge" statements in the extract file, causing the substrate to get
disconnected between parent and child.
works for the first pair of types/plane being below the second pair of
types/plane (upward fringing from the top of a wire to an overlapping
wire above it), which was not being handled due to an implicit assumption
that plane1 < plane2, which does not have to be the case.
could cause serious errors on systems that do not auto-zero allocated
memory. Also: Fixed an error introduced by a recent commit to allocate
character memory for efReadLine() which frees the memory before reading
a .res.ext file, causing a crash when using "ext2spice" with the
"extresist on" option.
optional name field to the "substrate" line in the extract section
of the techfile. This is the default name of the substrate if not
connected to anything labeled. It may use a Tcl variable (preferred).
(2) Added command option "instance orientation [-def]" that returns
the orientation of the named or selected instance. The -def option
returns the orientation using DEF naming convention; otherwise, the
naming used with "getcell" is generated.
areas and writes ANTENNAGATEAREA and ANTENNADIFFAREA values.
(2) Determines "USE POWER" or "USE GROUND" from label names
matching Tcl variables $VDD and $GND, if the USE has not been
registered as a cell property (knowning the use allows magic
to avoid writing an ANTENNADIFFAREA for power rails, although
doing so should not be an issue).
not copy labels; not copying labels speeds up the antenna checks
(which don't need labels) greatly. Also fixed several numerical
overflow problems in the antenna checks, which resulted in false
positive errors, as well as nonsensical results.
Conflicts:
VERSION
Merged recent changes from master back into bplane, as the efficiency of
bplane for doing extraction on large layouts is unquestionably better.
Fixed the implementation of DBMoveCell() for bplane. Corrected an error
in the bplane version of dbScaleCell() that enumerates cell uses but
does not free the list.
generating duplicate devices that may have parts overlaid in
different subcells; this failed to filter the check by plane of
the device, and so if any two devices exist at the same point in
two different planes (e.g., metal resistor and a transistor), one
of them would get eliminated.
Conflicts:
VERSION
calma/Depend
cif/Depend
cmwind/Depend
commands/Depend
database/Depend
dbwind/Depend
debug/Depend
drc/Depend
ext2sim/Depend
ext2spice/Depend
extflat/Depend
extract/Depend
garouter/Depend
gcr/Depend
graphics/Depend
grouter/Depend
irouter/Depend
lef/Depend
lisp/Depend
mzrouter/Depend
netmenu/Depend
plot/Depend
plow/Depend
resis/Depend
router/Depend
select/Depend
sim/Depend
tcltk/Depend
textio/Depend
tiles/Depend
utils/Depend
windows/Depend
wiring/Depend
Merged recent changes from master branch into bplane branch. Testing the
bplane implementation which has about a 5x improvement in extraction times
for large layouts, which is significant enough to move ahead with the bplane
implementation; however, the bplane implementation has not been thoroughly
vetted yet, so it will remain a branch until such time that it has been
validated.
substrate more than once for the same subcell, since the substrate
extraction method scans the entire plane area; this was making
large standard cell layouts extract very slowly, as every component
cell was causing the substrate search to be repeated.
extraction: Fixed a problem causing long extraction times, at
least some of which had to do with a poor string hash function
implementation. Fixed a huge problem in ext2spice, where the
node merge function was particularly poorly implemented, causing
exponentially increasing processing times with layout size.
Corrected a minor issue with ext2spice where arguments were
improperly specified, causing unnecessary error messages to be
issued. Fixed an error in the "load -dereference" command option,
which again caused unnecessary error messages to be issued.
Changed .gitignore to ignore Depend files, which are now regenerated
on every build.
Conflicts:
VERSION
database/DBcellsrch.c
database/DBconnect.c
extract/ExtInter.c
lef/Depend
utils/Depend
Updated bplane branch with all changes to master since the bplane branch
was last modified.
only at the time of running the command "load". But cells are generally
loaded only on an as-needed basis, so the dereferencing option must be
saved as a flag in the cell and honored whenever its subcells are expanded
or otherwise read at a later time.
include (1) specification of sidewall or surface to use for
each type individually, rather than a single method for all
types, and (2) specification of a linear model R = Ax + B for
the ratio limit when diodes are attached to the wire, where x
is the diode surface area (unitless, as this is a ratio).
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
rid of redundant port entries in subcircuits. There is still an outstanding
issue as to whether nodes and connections need to be recursively iterated
to the hierarchy bottom. The current fix corrected the test case. Also,
added a "-dereference" option to the "load" command to revert to the
original behavior of using only search paths from "addpath" when searching
for files to load.
to multiple entries per device; the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
perimeter were not output because of recent code that broke the
routine that assigns the resistance classes to devices. This is
now fixed. Thanks to Dan Moore for bringing this to my attention,
and debugging investigations.
device type so that it is now properly backwards compatible with
the old-style "fet" records. Also corrected the record matching
such that it properly matches according to the number of terminals
while allowing the traditional interpretation that there may be
fewer S/D type records than terminals if the S/D types are the
same for all terminals.
principle layer name, which should not happen (especially in the
case of space, where layers may be aliased to "space" to make them
ignored on input). Also: Implemented a "-<types>" option to the
"substrate" record in the techfile to declare types which shield
layers from the substrate. This allows types like pwell to be used
in different contexts, e.g., as part of the substrate, or as a P-well
in deep N-well, without requiring a different type. This works in
conjunction with the recently-implemented "+<types>" ID types for
devices. All of this may seem unnecessary but helps to reduce the
number of layers needing to be defined, and the subsequent complexity
of the DRC rulesets.
handles diodes or other devices with source/drain on planes other
than the plane of the device type. This no longer requires that
the non-connecting type be in any given terminal position. The
device type boundary is surveyed for all types, connecting or
overlapping, and at least one of each required type must be present.
format with multiple devices per magic tile type. The code was left
incompatible with diodes defined with one terminal as substrate
(and therefore no source/drain-like types connecting to the device
type). This has been fixed.
all types specified in the "substrate" statement, split such types
into those on the declared well plane, and everything else. Any
types on the well plane are searched as before. Types not on the
well plane (e.g., psd on active) are searched and added to the
substrate node *only* if overlapping nothing on the well plane.
This allows a type such as "psd" to be used on, e.g., both space
(substrate) and deep pwell, but only be extracted as part of the
substrate when found over space. Note that if there is NO
implicit substrate, the substrate connections will always be
found through the usual connection rules.
to be more robust and not depend on the ordering of the devices in
the techfile. The extraction method now keeps a mask of which
properties of the device (source/drain types, substrate type,
identifier type) have been found, and will look only for device
records that match what is known about the device. Added a device
identifier record which is the last record before parameters if the
record begins with "+". This allows marker layers to be placed
over a device such that it will extract with a different type.
This helps reduce the complexity of the techfile and allows
certain specialized devices like RF or ESD to be identified without
a separate layer type for the device.
where devices extracted as "device resistor" or "device capacitor"
and defining parameters (e.g., area, perimeter) will generate the
device arguments in the wrong order in the .ext file, resulting in
incorrect readback when attempting to do ext2spice, resulting in the
device being omitted from the resulting netlist.
extraction times, which is an incorrect units conversion of the
"step" parameter in the extract section. It was converting based
on the "lambda" parameter in the same section, which has to do with
the scaling of values in the output file, not the scale factor of
the database to be extracted, which is set by the current CIF output
scale. Once fixed, extraction times are minimized using the rule of
thumb mentioned in the techfile reference, which is 50 times the
minimum feature size. Also: Give the lengthy nature of extraction
on large designs no matter how well optimized, added a feature to
mark the progress of the extraction in increments of 5%. Does not
output progress for small cells that extract quickly.
all the settings normally used for LVS (hierarchy on, cthresh
infinite, subcircuit top auto, etc.). (2) Extract and extract
unique ignore cells marked as abstract views (property LEFview
is set) when checking for unconnected nets with the same name
label.
in the SPICE netlist when using new device "csubcircuit" due to
a mismatch in the expected number of parameters. However, more
work needs to be done to cover capacitor top and bottom plates on
different planes.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
development had been halted since it was first created back in April.
Version 8.2 is now the official development version, with the first
development push to create a Cairo graphics interface.
Tim Edwards
Anton Blanchard
Dan Moore