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Corrected an error in the last commit that causes serious problems 

in the SPICE netlist when using new device "csubcircuit" due to
a mismatch in the expected number of parameters.  However, more
work needs to be done to cover capacitor top and bottom plates on
different planes.
This commit is contained in:
Tim Edwards 2018-10-30 17:17:49 -04:00
parent a36b12eadd
commit e20319f3c1
1 changed files with 10 additions and 10 deletions
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20
extract/ExtBasic.c
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@ -2118,16 +2118,6 @@ extOutputDevices(def, transList, outFile)
(void) ExtFindNeighbors(reg->treg_tile, arg.fra_pNum, &arg);
extComputeCapLW(&length, &width);
if ((length * width) > reg->treg_area)
{
if (ExtDoWarn)
extTransBad(def, reg->treg_tile, "L,W estimated "
"for non-rectangular capacitor.");
fprintf(outFile, " %d %d", width,
reg->treg_area / width);
}
else
fprintf(outFile, " %d %d", length, width);
/* Free the lists */
@ -2153,6 +2143,16 @@ extOutputDevices(def, transList, outFile)
}
else /* SPICE semiconductor resistor */
{
if ((length * width) > reg->treg_area)
{
if (ExtDoWarn)
extTransBad(def, reg->treg_tile, "L,W estimated "
"for non-rectangular capacitor.");
fprintf(outFile, " %d %d", width,
reg->treg_area / width);
}
else
fprintf(outFile, " %d %d", length, width);
if (subsName != NULL)
fprintf(outFile, " \"%s\"", subsName);
}