Corrected the extraction method for devices with terminals on the
implicit global substrate, as a block of code meant to handle this case was left unreachable by another recent code fix.
This commit is contained in:
Tim Edwards
parent
cf54d146d1
commit
3c42c5a7f3
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@ -21,6 +21,7 @@ scmos/scmos-sub.tech
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scmos/scmos-tm.tech
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scmos/scmos.tech
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scmos/scmosWR.tech
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scmos/nmos.tech
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tcltk/magic.sh
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tcltk/magic.tcl
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tcltk/magicdnull
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@ -1812,8 +1812,33 @@ extOutputDevices(def, transList, outFile)
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|| (TTMaskHasType(tmask, TT_SPACE)))
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{
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node = NULL;
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/* First try to find a region under the device */
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extTransFindSubs(reg->treg_tile, t, tmask, def, &node, NULL);
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if (node == NULL) {
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if ((node == NULL) && (TTMaskHasType(tmask, TT_SPACE))) {
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/* Device node is possibly the substrate. But: Note */
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/* that TT_SPACE in the mask covers all planes, and it */
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/* is not possible to specify TT_SPACE in a single */
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/* plane. So it is necessary to check for any */
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/* shielding types that block the substrate. */
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if (!TTMaskIsZero(&ExtCurStyle->exts_globSubstrateShieldTypes))
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{
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extTransFindSubs(reg->treg_tile, t,
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&ExtCurStyle->exts_globSubstrateShieldTypes,
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def, &node, NULL);
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}
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if ((glob_subsnode == NULL) || (node != NULL)) {
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/* See if there is another matching device record */
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/* with a different terminal type, and try again. */
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devptr = extDevFindMatch(devptr, t);
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break;
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}
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else if ((node == NULL) && (glob_subsnode != NULL))
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node = glob_subsnode;
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}
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else if (node == NULL) {
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/* See if there is another matching device record */
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/* with a different terminal type, and try again. */
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devptr = extDevFindMatch(devptr, t);
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@ -1822,29 +1847,6 @@ extOutputDevices(def, transList, outFile)
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extTransRec.tr_devmatch |= (MATCH_TERM << termcount);
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extTransRec.tr_termnode[termcount] = node;
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}
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else if (TTMaskHasType(tmask, TT_SPACE)) {
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/* Device node is possibly the substrate. But: Note that */
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/* TT_SPACE in the mask covers all planes, and it is not */
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/* possible to specify TT_SPACE in a single plane. So it */
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/* is necessary to check for any shielding types that */
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/* block the substrate. */
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node = NULL;
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if (!TTMaskIsZero(&ExtCurStyle->exts_globSubstrateShieldTypes))
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{
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extTransFindSubs(reg->treg_tile, t,
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&ExtCurStyle->exts_globSubstrateShieldTypes,
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def, &node, NULL);
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}
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if ((glob_subsnode == NULL) || (node != NULL)) {
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/* See if there is another matching device record */
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/* with a different terminal type, and try again. */
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devptr = extDevFindMatch(devptr, t);
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break;
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}
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extTransRec.tr_devmatch |= (MATCH_TERM << termcount);
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extTransRec.tr_termnode[termcount] = glob_subsnode;
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}
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else {
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/* Determine if there is another matching device record */
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/* that has fewer required terminals. */
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@ -3173,8 +3175,9 @@ extSpecialPerimFunc(bp, sense)
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break;
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if (thisterm >= extTransRec.tr_nterm)
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{
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if (toutside == TT_SPACE)
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TxError("Internal Error in Transistor Perimeter Boundary Search!\n");
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/* This is not necessarily an error; e.g., happens for */
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/* a device like a diode with TT_SPACE in the source/ */
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/* drain list. */
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return 1;
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}
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}
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473
scmos/nmos.tech
473
scmos/nmos.tech
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@ -1,473 +0,0 @@
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#
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# nmos.tech --
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#
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# Defines the MOSIS 4.0 micron NMOS technology for Magic. Some
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# of the characteristics of this technology are:
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#
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# 1. 1 level of metal.
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# 2. Buried contacts.
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# 3. No butting contacts.
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#
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# Copyright (C) 1985 Regents of the University of California
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# All rights reserved.
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#
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# sccsid @(#)nmos.tech 3.73 MAGIC (Berkeley) 11/22/85
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#
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tech
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format 35
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nmos
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end
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version
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version 0
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description "MOSIS 4.0 micron NMOS"
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requires magic-8.3.0
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end
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planes
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active,diff,poly_diff
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metal
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end
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types
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active polysilicon,poly,red
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active diffusion,diff,green
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metal metal,blue
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active poly_metal_contact,pmc
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active diff_metal_contact,dmc
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active enhancement_fet,efet
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active depletion_fet,dfet
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active depletion_capacitor,dcap
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active buried_contact,bc
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metal glass_contact,glass
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end
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styles
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styletype mos
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polysilicon 1
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diffusion 2
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metal 20
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enhancement_fet 6
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enhancement_fet 7
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depletion_fet 6
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depletion_fet 10
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depletion_capacitor 6
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depletion_capacitor 11
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buried_contact 6
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buried_contact 33
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poly_metal_contact 1
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poly_metal_contact 20
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poly_metal_contact 32
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diff_metal_contact 2
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diff_metal_contact 20
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diff_metal_contact 32
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glass_contact 20
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glass_contact 34
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error_s 42
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error_p 42
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error_ps 42
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# Hint layers
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magnet 39
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fence 38
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rotate 37
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end
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contact
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pmc poly metal
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dmc diff metal
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end
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aliases
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allDiff diff,dmc,bc,efet,dfet,dcap
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allPoly poly,pmc,bc,efet,dfet,dcap
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tran efet,dfet
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allMetal metal,pmc,dmc,glass
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spP (space,poly,pmc)/a
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sdD (space,diff,dmc)/a
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notDmc space,metal,pmc,glass
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notPmc space,metal,dmc,glass
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allButFet (space,diff,poly,dmc,pmc,bc)/a
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allpdTypes (space,diff,poly,dmc,pmc,bc,dfet,dcap,efet)/a
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end
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compose
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# The following rule allows transistors to be built up of poly and diff */
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compose efet poly diff
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# The following rules allow poly or diff to be erased from fets or bcs */
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decompose dfet poly diff
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decompose dcap poly diff
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decompose bc poly diff
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# The following lets us erase metal from a glass_contact to get space */
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erase glass metal space
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end
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#
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# Electrical connectivity. Each tile in the group on the left
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# is considered to be connected to each tile in the group on
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# the right. Tiles within the groups are not necessarily
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# connected to each other.
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#
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connect
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poly pmc,efet,dfet,dcap,bc
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diff bc,dmc
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efet pmc,dmc,bc,dfet,dcap
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dfet pmc,dmc,bc,dcap
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dcap pmc,dmc,bc
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pmc dmc,bc
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dmc bc
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metal glass,pmc,dmc
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glass pmc,dmc
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end
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# Information used to generate CIF files. The only tricky business
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# is to merge necks between adjacent implants or buried windows.
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# The grow-shrink does this. Also, note that labels on Magic layers
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# get attached to the first CIF layer containing that Magic layer
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# in an "or" or "bloat-or" statement. This makes order important
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# (for example, we want transistor labels to attach to the poly gate).
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#
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cifoutput
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style lambda=2
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scalefactor 200 100
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layer NP poly,pmc,efet,dfet,dcap,bc
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labels poly,efet,dfet,dcap,bc
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calma 1 1
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layer ND diff,dmc,efet,dfet,dcap,bc
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labels diff
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calma 2 1
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layer NM metal,pmc,dmc,glass
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labels metal,pmc,dmc,glass
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calma 3 1
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layer NI
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bloat-or dfet,dcap * 200 diff,bc 400
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grow 100
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shrink 100
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calma 4 1
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layer NC dmc
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squares 400
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calma 5 1
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layer NC pmc
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squares 400
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calma 6 1
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layer NG glass
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calma 7 1
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layer NB
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bloat-or bc * 200 diff,dmc 400 dfet 0
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grow 100
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shrink 100
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calma 8 1
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end
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# Information on how to read CIF files. Read in all the CIF layers,
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# then perform geometric operations to get the Magic layers. The
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# order in which the Magic layers are generated is important!
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#
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cifinput
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style lambda=2
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scalefactor 200
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layer poly NP
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labels NP
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layer diff ND
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labels ND
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layer metal NM
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labels NM
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layer efet NP
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and ND
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layer dfet NI
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and NP
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and ND
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layer pmc NC
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grow 200
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and NM
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and NP
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layer dmc NC
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grow 200
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and NM
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and ND
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# Buried contacts must be generated after transistors, since they
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# override transistors.
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#
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layer bc NB
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and NP
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and ND
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layer glass NG
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end
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mzrouter
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style irouter
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layer metal 32 32 256 1
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layer poly 64 64 256 1
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contact pmc metal poly 1024
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end
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#
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# DRC information
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# Width, spacing and edge rules are "compiled" into rules table entries.
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#
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# width: types in the mask, taken collectively, must have the given width
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#
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# spacing: types in mask1 must be separated by distance from types in mask2
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#
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# edge: explict entries for the rules table --
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# LHS RHS distance types allowed on RHS corner mask reason
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#
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# All combinations of single elements of the LHS and RHS masks
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# are used to form a rule.
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#
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drc
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width allDiff 2 "Diffusion width must be at least 2"
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width dmc 4 "Metal_diff contact width must be at least 4"
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width allPoly 2 "Polysilicon width must be at least 2"
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width pmc 4 "Metal_poly contact width must be at least 4"
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width bc 2 "Buried contact width must be at least 2"
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width efet 2 "Enhancement FET width must be at least 2"
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width dfet 2 "Depletion FET width must be at least 2"
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width dcap 2 "Depletion capacitor width must be at least 2"
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width allMetal 3 "Metal width must be at least 3"
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spacing allDiff allDiff 3 touching_ok \
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"Diff-diff separation must be at least 3"
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spacing allPoly allPoly 2 touching_ok \
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"Poly-poly separation must be at least 2"
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spacing tran pmc,dmc 1 touching_illegal \
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"Transistor-contact separation must be at least 1"
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spacing efet dfet,dcap 3 touching_illegal \
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"Enhancement-depletion transistor separation must be at least 3"
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spacing allMetal allMetal 3 touching_ok \
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"Metal-metal separation must be at least 3"
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#
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# Diff and poly cannot be adjacent, except at corners where
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# the intermediate material is "bc", "efet", "dfet", or "dcap".
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# Thus, there is no need for rules with RHS equal to "Bef".
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# But corner extension applies if the intermediate material is "s".
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# For this reason, the first edge rule CANNOT be rewritten as
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# "edge diff pP 1 0 pP 1".
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#
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edge diff spP 1 (space)/a spP 1 \
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"Diff-poly separation must be at least 1"
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edge poly sdD 1 (space)/a sdD 1 \
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"Diff-poly separation must be at least 1"
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#
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# Allow dmc and pmc to be adjacent since they are electrically shorted.
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#
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edge dmc (space,poly)/a 1 (space)/a (space,poly)/a 1 \
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"Diff-poly separation must be at least 1"
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edge pmc (space,diff)/a 1 (space)/a (space,diff)/a 1 \
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"Diff-poly separation must be at least 1"
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#
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# Don't let pmc and dmc have convex shapes, since this may interfere
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# with the via-generation process. The corner check in the rules
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# below does this. Also don't let contacts overlap between cells
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# unless they do so exactly.
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#
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edge4way dmc notDmc 1 notDmc notDmc,dmc 1 \
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"Diffusion-metal contacts must be rectangular"
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edge4way pmc notPmc 1 notPmc notPmc,pmc 1 \
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"Poly-metal contacts must be rectangular"
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exact_overlap pmc,dmc
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#
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# Transistors cannot touch space, except in corners.
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# The corner mask is set to 0 to prevent checking there.
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#
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edge tran (space)/a 1 0 0 0 \
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"Transistor overhang is missing"
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edge (space)/a tran 1 0 0 0 \
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"Transistor overhang is missing"
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#
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# Buried contacts must be 3 lambda from efets in all cases,
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# and 4 lambda in some. Depends on the orientation of the
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# buried contact implant. The 4x3 corner checks ON BOTH
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# SIDES solve the problem. Buried contacts may abut
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# depletion transistors, but only if the transistors are
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# fairly long (otherwise, a misalignment in the buried
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# window mask may make a huge difference in the transistor's
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# effective length).
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#
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spacing bc efet 3 touching_illegal \
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"Buried contact-transistor separation must be at least 3"
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spacing bc dfet 3 touching_ok \
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"Buried contact-transistor separation must be at least 3"
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edge4way bc diff,dmc 4 allButFet allpdTypes 3 \
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"Buried contact-transistor separation must be at least 4 on diff side"
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edge4way bc dfet 4 dfet 0 0 \
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||||
"Transistors next to buried contacts must be at least 4 long"
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||||
|
||||
#
|
||||
# WARNING: The above rules don't take care of poly approaching
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# the buried contact on the diffusion side. Unfortunately, the
|
||||
# only fix is a rule that is ridiculously conservative. So
|
||||
# for now, buyer beware!
|
||||
#
|
||||
|
||||
#
|
||||
# 3 by 2 shape of buried contact next to dfet.
|
||||
# No corner check.
|
||||
#
|
||||
edge4way dfet bc 3 bc 0 0 \
|
||||
"Buried contact next to depletion transistor must be at least 3x2"
|
||||
#
|
||||
# Poly and diffusion must overhang transistors by 2.
|
||||
#
|
||||
# Corner checks are necessary for L or S shaped transistors.
|
||||
#
|
||||
# Don't worry about dfet -- buried_contact boundaries here.
|
||||
#
|
||||
edge4way tran poly 2 poly,pmc poly 2 \
|
||||
"Polysilicon must overhang transistor by at least 2"
|
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edge4way tran diff 2 diff,dmc diff 2 \
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||||
"Diffusion must overhang transistor by at least 2"
|
||||
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||||
# Cannot change transistors as a result of cell overlaps */
|
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no_overlap efet,dfet efet,dfet
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||||
end
|
||||
|
||||
#
|
||||
# Parameters for circuit extraction.
|
||||
# A type may appear both as a node and as a transistor. When it
|
||||
# appears as a node, we are describing the gate, and when it appears
|
||||
# as a transistor, we are describing the channel.
|
||||
#
|
||||
|
||||
extract
|
||||
style default
|
||||
# scale factor: output units (centimicrons) per lambda */
|
||||
lambda 200
|
||||
|
||||
# chunk size for hierarchical extraction, in lambda */
|
||||
step 100
|
||||
|
||||
planeorder active 0
|
||||
planeorder metal 1
|
||||
|
||||
# sheet resistivity milli-ohms per square */
|
||||
resist poly,pmc/poly,efet,dfet,bc 30000
|
||||
resist diff,dmc/poly 10000
|
||||
resist metal,glass 30
|
||||
|
||||
# area capacitance atto-farads/lambda**2 */
|
||||
areacap poly,efet,dfet 200
|
||||
areacap metal,glass 120
|
||||
areacap diff 400
|
||||
areacap bc 600
|
||||
areacap dmc/poly 520
|
||||
areacap pmc/poly 320
|
||||
|
||||
# sidewall capacitance atto-farads/lambda */
|
||||
perimc diff,dmc/poly,bc space,dfet,efet 200
|
||||
|
||||
# transistors terms #terms name substr gs-cap gc-cap */
|
||||
fet efet diff 2 efet GND! 0 0
|
||||
fet dfet diff,bc 2 dfet GND! 0 0
|
||||
fet dcap diff,bc 1 dcap GND! 0 0
|
||||
# End of style "default" */
|
||||
end
|
||||
|
||||
# Information for the wiring interface */
|
||||
wiring
|
||||
contact pmc 4 metal 0 poly 0
|
||||
contact dmc 4 metal 0 diff 0
|
||||
contact bc 2 poly 0 diff 0
|
||||
end
|
||||
|
||||
# Information to control the router */
|
||||
router
|
||||
layer1 metal 3 metal,pmc/metal,dmc/metal,glass 3
|
||||
layer2 poly 2 poly,efet,dfet,dcap,pmc,bc 2 diff,dmc 1
|
||||
contacts pmc 4
|
||||
gridspacing 7
|
||||
end
|
||||
|
||||
# Information for plowing */
|
||||
plowing
|
||||
fixed efet,dfet,dcap,bc,glass
|
||||
covered efet,dfet,dcap,bc
|
||||
drag efet,dfet,dcap,bc
|
||||
end
|
||||
|
||||
plot
|
||||
style versatec
|
||||
|
||||
# Same as Gremlin stipple 9: */
|
||||
dfet,dcap \
|
||||
07c0 0f80 1f00 3e00 \
|
||||
7c00 f800 f001 e003 \
|
||||
c007 800f 001f 003e \
|
||||
00c7 00f8 01f0 03e0
|
||||
|
||||
# Same as Gremlin stipple 10: */
|
||||
efet,dcap \
|
||||
1f00 0f80 07c0 03e0 \
|
||||
01f0 00f8 007c 003e \
|
||||
001f 800f c007 e003 \
|
||||
f001 f800 7c00 3e00
|
||||
|
||||
# Same as Gremlin stipple 11: */
|
||||
bc \
|
||||
c3c3 c3c3 0000 0000 \
|
||||
0000 0000 c3c3 c3c3 \
|
||||
c3c3 c3c3 0000 0000 \
|
||||
0000 0000 c3c3 c3c3
|
||||
|
||||
# Same as Gremlin stipple 12: */
|
||||
glass \
|
||||
0040 0080 0100 0200 \
|
||||
0400 0800 1000 2000 \
|
||||
4000 8000 0001 0002 \
|
||||
0004 0008 0010 0020
|
||||
|
||||
# Same as Gremlin stipple 17: */
|
||||
diff,dmc/active,efet,dfet,dcap,bc \
|
||||
0000 4242 6666 0000 \
|
||||
0000 2424 6666 0000 \
|
||||
0000 4242 6666 0000 \
|
||||
0000 2424 6666 0000
|
||||
|
||||
# Same as Gremlin stipple 19: */
|
||||
poly,pmc/active,efet,dfet,dcap,bc \
|
||||
0808 0400 0202 0101 \
|
||||
8080 4000 2020 1010 \
|
||||
0808 0004 0202 0101 \
|
||||
8080 0040 2020 1010
|
||||
|
||||
# Same as Gremlin stipple 22: */
|
||||
metal,dmc/metal,pmc/metal,glass \
|
||||
8080 0000 0000 0000 \
|
||||
0808 0000 0000 0000 \
|
||||
8080 0000 0000 0000 \
|
||||
0808 0000 0000 0000
|
||||
|
||||
# Same as Gremlin stipple 23: */
|
||||
glass \
|
||||
0000 0000 1c1c 3e3e \
|
||||
3636 3e3e 1c1c 0000 \
|
||||
0000 0000 1c1c 3e3e \
|
||||
3636 3e3e 1c1c 0000
|
||||
|
||||
pmc,dmc X
|
||||
bc B
|
||||
|
||||
style gremlin
|
||||
dfet,dcap 9
|
||||
efet,dcap 10
|
||||
bc 11
|
||||
glass 12
|
||||
diff,dmc/active,efet,dfet,dcap,bc 17
|
||||
poly,pmc/active,efet,dfet,dcap,bc 19
|
||||
metal,dmc,pmc,glass 22
|
||||
pmc,dmc X
|
||||
bc B
|
||||
end
|
||||
Loading…
Reference in New Issue