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359 Commits

Author SHA1 Message Date
Matthias Koefferlein f06d435b05 WIP: netlist comparer - moved into it's own files. 2019-03-29 00:37:45 +01:00
Matthias Koefferlein e8d59504dd WIP: netlist compare - forced matching of circuits. 2019-03-29 00:13:13 +01:00
Matthias Koefferlein d255617051 WIP: netlist compare - tests for device class equivalence mapping, added Netlist#device_class_by_name 2019-03-28 18:01:22 +01:00
Matthias Koefferlein cefd6e91cf WIP: some refactoring, netlist compare. Goal: support explicit device class and circuit mapping. 2019-03-27 23:17:35 +01:00
Matthias Koefferlein b44a55d901 WIP: netlist compare - pin swapping. 2019-03-26 23:38:36 +01:00
Matthias Koefferlein 46cd80d606 WIP: netlist compare - terminal swapping of devices. 2019-03-26 22:05:08 +01:00
Matthias Koefferlein e0cb3f6303 WIP: netlist compare - subcircuit matching enhanced. 2019-03-26 20:54:49 +01:00
Matthias Koefferlein 93d2341bc7 WIP: netlist compare 2019-03-26 00:10:10 +01:00
Matthias Koefferlein fec2348d97 WIP: Net compare. 2019-03-25 23:26:46 +01:00
Matthias Koefferlein 1a30a3919d WIP: Net compare with subcircuits. 2019-03-25 22:14:16 +01:00
Matthias Koefferlein 55052038ea WIP: netlist compare 2019-03-24 21:14:08 +01:00
Matthias Koefferlein bb2d3765b8 WIP: netlist compare, ambiguous net resolution, device mapping. 2019-03-24 00:45:58 +01:00
Matthias Koefferlein 25b7ab9dab WIP: netlist comparer 2019-03-23 10:31:29 +01:00
Matthias Koefferlein 7042cdb98b Ported netlist normalization for #246 merge (unit test compatibility windows/linux) 2019-03-22 21:54:45 +01:00
Matthias Köfferlein d1acd722ad
Merge pull request #246 from KLayout/issue-245 
Issue 245
 2019-03-22 21:49:39 +01:00
Matthias Koefferlein 4e63b38092 Further normalization of Spice test files (unit tests) 2019-03-22 21:47:52 +01:00
Matthias Koefferlein 5dfc609724 Normalize netlists before compare for windows/linux compatibility. 2019-03-22 17:51:37 +01:00
Matthias Koefferlein 9356f32026 Fixed issue-245 (support Spice netlist with names instead of numbers) 
The option is in the Spice writer (writer.use_net_names=true).
 2019-03-21 23:34:16 +01:00
Matthias Koefferlein e424a88c90 WIP: netlist compare algo 
1.) Can identify transistor netlists without subcircuits
2.) Ambiguities stay unresolved

Next steps: assign ambiguous nets one by one and continue
in case of ambiguitites.
 2019-03-21 22:13:23 +01:00
Matthias Koefferlein c568838bbe WIP: netlist compare 2019-03-20 23:00:43 +01:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein d7eb9162ce WIP: unified to_string/to_parsable_string of db::Netlist, step 1 2019-03-18 19:28:20 +01:00
Matthias Koefferlein e4078ca750 String serialization for netlists. 2019-03-18 02:00:33 +01:00
Matthias Koefferlein 57fb764f16 Removed ambiguity for 64bit coordinate builds. 2019-03-12 00:09:52 +01:00
Matthias Koefferlein 510c675d21 Test cases for DRC-based net extraction and flat extraction 
Flat extraction requires that texts of subcells are not
considered. Otherwise they pollute the net namespace of
the top cell.
 2019-03-10 19:35:13 +01:00
Matthias Koefferlein 37cc84908e Updated test because of edge pair normlization 2019-03-09 20:25:45 +01:00
Matthias Koefferlein 6932977273 A few bug fixes and test updates 
- edge pairs are normalized before turning them into polygons.
  This makes flat and deep implementation more consistent.
- deep region and flat regions were not cooperating in geo
  checks
- unnamed layers are not registered in make_layer - this
  does not make sense and will just hold a fake ref
- tests now use GDS to represent texts after transformation
  (with orientation, OASIS can't do this)
- texts are more consistently handled in the tests
- test debug output is not written in the same format
  than golden data unless special normalization is
  requested.
- a non-orientable polygon was converted to orientable in
  a text because this can be represented in GDS consistently
- DRC testsuite uses "polygons" instead of "input" to achieve
  identical behavior for deep and flat mode with respect to
  texts
- dbRegionTests are updated because texts are not allowed
  for non-original layers too
 2019-03-09 19:40:38 +01:00
Matthias Koefferlein 8b29b30ff9 WIP: more consistent text handling 
Texts are not only kept inside original layers, but
also inside deep layers. This enables using texts
from DRC.

However, texts in deep layers are kept as markers.
Mostly they are converted back to texts, but the
orientation will be lost.

The change eliminates the need to using Iterators
in DRC instead of original layers and use of
label layers in deep mode.

A drawback is the presence of marker shapes in
deep mode (unless polygon layers are created).
Also, text output to RDB is not supported from
deep layers currently.
 2019-03-06 00:34:56 +01:00
Matthias Koefferlein 604a634bf1 Generalization of layout index for LayoutToNetlist 2019-03-03 18:10:52 +01:00
Matthias Koefferlein 261fb027fd GSI binding of antenna check function + tests. 2019-03-02 00:38:51 +01:00
Matthias Koefferlein 8d3b94201e Antenna check: tests added, 'catchall' diode protection 2019-03-01 23:07:28 +01:00
Matthias Koefferlein 9f4f2d58d7 First version of antenna check. 2019-02-28 23:56:49 +01:00
Matthias Koefferlein 4035c804b7 WIP: fixed bugs, added tests. 2019-02-28 22:23:20 +01:00
Matthias Koefferlein 36a3540e16 Allow empty regions for device extractor. 2019-02-25 23:51:21 +01:00
Matthias Koefferlein 21ea37f747 Updated test golden data. 2019-02-25 22:52:37 +01:00
Matthias Koefferlein 9b31bd3214 Fixed crash by introducing a new scheme for storing cluster refs 
The previous implementation was based on the Instance
pointers, but these got invalidated during device cell
construction. Now an explicit copy of the instance is
kept.
 2019-02-25 22:36:24 +01:00
Matthias Koefferlein d4ed21f42a Just new tests 2019-02-25 22:34:06 +01:00
Matthias Koefferlein 3c6aafcc0c Region: hierarchical text object detection implementated. 2019-02-23 00:56:55 +01:00
Matthias Koefferlein 18f74bac1e Enabled transformations for deep regions/edges/edge pairs - important for handling layouts with different DBUs in DRC 2019-02-22 01:02:48 +01:00
Matthias Koefferlein 91407ddaa9 Added tests for region processors. 2019-02-20 21:40:43 +01:00
Matthias Koefferlein 496b695ef0 Refactoring of the polygon processing in Region 2019-02-19 22:11:55 +01:00
Matthias Koefferlein 90c1d212a4 Refactoring: new concept for edge/polygon filters 2019-02-19 20:19:10 +01:00
Matthias Koefferlein 3918172c6a Fixed a nasty issue with editable mode. 2019-02-18 23:34:46 +01:00
Matthias Koefferlein 9ec6b44c93 Added some tests for the previous commit. 2019-02-18 00:15:26 +01:00
Matthias Koefferlein 311318c578 Ported edge/edge DRC functions to hierarchical mode. 2019-02-17 18:54:33 +01:00
Matthias Koefferlein c40f147dc7 Edge/edge and edge/polygon interaction test ported to hierarchical mode. 2019-02-17 18:36:15 +01:00
Matthias Koefferlein 7ef0451ca8 Partial segments of edges converted to hierarchical operations. 2019-02-17 17:53:21 +01:00
Matthias Koefferlein 74006b6208 Hierarchical implementation of extended method for edges 2019-02-17 17:34:31 +01:00
Matthias Koefferlein ae783a2245 Hiearchical implementation of edge filter. 2019-02-17 16:18:24 +01:00
Matthias Koefferlein 61d766bd4c Hierarchical implementation of edge to region operations. 2019-02-17 16:05:39 +01:00
Matthias Koefferlein e6ee1c064e Hierarchical implementation of edge/edge booleans. 2019-02-17 15:07:16 +01:00
Matthias Koefferlein 8e5bffcf18 Hierarchical angle check. 2019-02-17 11:42:30 +01:00
Matthias Koefferlein a7bfaac424 Cell variant resolution by propagation, grid check now implementation hierarchically (with propagation) 2019-02-17 10:59:04 +01:00
Matthias Koefferlein 5dc833970b Hierarchical implementation DRC functions (measurements) 2019-02-16 22:34:36 +01:00
Matthias Koefferlein 6e35e80963 Hierarchical implementation of polygon vs. edge interact 2019-02-15 23:43:45 +01:00
Matthias Koefferlein 78617930dd Hierarchical implementation of self-overlap merge. 2019-02-13 22:41:12 +01:00
Matthias Koefferlein ddcfda8761 Some optimization: keep merged state in deep region. 2019-02-13 17:17:03 +01:00
Matthias Koefferlein b0fc2be96e Deep regions: some more operations implemented hierarchically 
- snap (!) - but only for gx == gy
- filtering
- interact/inside/outside/overlap + not_... variants
- edges
 2019-02-13 01:07:32 +01:00
Matthias Koefferlein 10f9de8b66 Added test for edge-based clusters, edge connectivity modes 2019-02-12 22:14:50 +01:00
Matthias Koefferlein 4b5736ba6a Added result type template parameter to local hier processor. 2019-02-12 20:32:07 +01:00
Matthias Koefferlein 6404ca6b1d WIP: Deep edge pairs 2019-02-12 00:08:47 +01:00
Matthias Koefferlein 2d9a3aaaa6 WIP: Hierarchical production of error db's. Needs testing. 2019-02-11 00:11:03 +01:00
Matthias Koefferlein dd4fcd9e36 WIP: templatized local hierarchical processor. 2019-02-10 18:39:32 +01:00
Matthias Koefferlein a81a8cdbc8 Modified edge transformation to maintain the orientation paradigm 
When the transformation is mirroring, edges now swap their
points to maintain the right-is-inside paradigm.
 2019-02-10 16:03:46 +01:00
Matthias Koefferlein a14ca01bac WIP: more on deep edge collections. 2019-02-10 15:33:14 +01:00
Matthias Koefferlein 4abc38a5cc Test for deep/flat collaboration 2019-02-10 08:28:48 +01:00
Matthias Koefferlein e8e45b7272 Some tests, smooth and round method of deep region 2019-02-09 23:51:35 +01:00
Matthias Koefferlein 7a86f0d878 Bugfix: size method needs to produce polygon refs so the output is usable as input for booleans too. 2019-02-09 22:55:34 +01:00
Matthias Koefferlein b6dd149f53 Changed variant suffix to to be consistent with cell name suffix generation in KLayout. 2019-02-09 19:21:14 +01:00
Matthias Koefferlein 1f3af7bbfe Hierarchical area and perimeter and sizing 
Area and perimeter computation happens hierarchically
now. Magnified instances are supported.

Sizing is implemented hierarchically.

For anisotropic sizing, orientation variants may be
generated. For both isotropic and anisotropic
magnification variants will be created.
 2019-02-09 19:13:54 +01:00
Matthias Koefferlein bbf7b2768b WIP: cell variant collecting and building. 2019-02-09 16:29:34 +01:00
Matthias Koefferlein 50c8c067d5 WIP: cell variant formation utility class. 2019-02-07 23:13:23 +01:00
Matthias Koefferlein decc5ede13 Robustification of Region 
- Tests for merge
- Locking the layout when writing back the data for
  performance improvement
 2019-02-05 23:39:31 +01:00
Matthias Koefferlein 9c0123df20 Implemented implicit joining of nets with the same label. 2019-02-03 21:34:23 +01:00
Matthias Koefferlein c90f7e4af9 Introduced perimeter parameters for MOS3/MOS4 2019-02-02 01:29:28 +01:00
Matthias Koefferlein 4068478887 Implemented SPICE writer + tests. 2019-01-31 00:07:10 +01:00
Matthias Koefferlein 458d00969c Fixed issue #228 
Reason for the problem: the interaction test
has to keep separate "inside" records for both
below and above the scanline, not just once.
With the single record, the step in the
left polygon erased the "inside" condition.
 2019-01-27 00:04:15 +01:00
Matthias Koefferlein 29264013b0 WIP: more consistent handling of polygon splitting parameters. 2019-01-25 22:28:25 +01:00
Matthias Koefferlein 12aaa2db20 Refactoring: unified handling of splitting parameters. 2019-01-25 21:48:56 +01:00
Matthias Koefferlein 6da9bc5e85 Updated tests after switching to boolean core. 2019-01-25 21:38:45 +01:00
Matthias Koefferlein 707c761bac WIP: local hierarchical operations: take boolean core rather than shape ref core -> better hierarchical quality. Tests need to be fixed. 2019-01-25 00:21:01 +01:00
Matthias Koefferlein 1cfa3251ce Better reproducibility of results in hier processor: hash function of shape ref takes object hash, not pointer hash 2019-01-23 22:19:28 +01:00
Matthias Koefferlein 68fe668567 WIP: performance improvement. 2019-01-22 07:42:44 +01:00
Matthias Koefferlein 81bf47688e Renamed device model -> device abstract 2019-01-21 22:37:13 +01:00
Matthias Koefferlein d79a448eaa Some performance improvement by eliminating empty objects in the box scanner. 2019-01-21 22:37:02 +01:00
Matthias Koefferlein f83e1dae43 Refactoring, some bugfixes, GSI bindings for L2N methods. 2019-01-20 23:12:27 +01:00
Matthias Koefferlein 4c7f43d749 More l2n reader tests. 2019-01-20 17:31:58 +01:00
Matthias Koefferlein dd39168dc8 WIP: Enabled layout generation from read l2n data. 2019-01-20 02:50:23 +01:00
Matthias Koefferlein a5e2cf58c3 l2n dump format is leaner (device terminal shapes dropped from nets as they are contained in the device abstracts). Some refactoring. 2019-01-19 23:00:19 +01:00
Matthias Koefferlein 8213e71a79 WIP: l2n reader implementation, some bug fixes, refactoring. 2019-01-19 22:19:08 +01:00
Matthias Koefferlein 56bb39a273 LayoutToNetlist enhancements in the area of the dumper. 2019-01-16 22:45:58 +01:00
Matthias Koefferlein 438f50091f WIP: Refined output format for l2n 2019-01-16 00:49:51 +01:00
Matthias Koefferlein 4cb8982ca2 WIP: added concept of device model. 2019-01-15 23:03:25 +01:00
Matthias Koefferlein 5962d66940 WIP: major enhancements with respect to device handling 
The device handling in the netlist extractor was now
entirely moved to device cells. New options are introduced
for exporting these cells. Tests have been updated.
 2019-01-15 21:33:41 +01:00
Matthias Koefferlein 1af81b74d2 WIP: refactoring - turning devices into cells for better backannotation. 2019-01-14 00:59:47 +01:00
Matthias Koefferlein baf50bd0b1 WIP: refactoring - singularization of classes in separate files. 2019-01-10 23:36:52 +01:00
Matthias Koefferlein 9fa5618034 Added test for device combination. 2019-01-08 23:49:12 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein 294f1701b5 Added a test for joining of layers through multiple global net assignment. 2019-01-07 23:57:52 +01:00
Matthias Koefferlein 315bcdd016 WIP: bugfixed netlist extractor with global nets. 2019-01-07 23:33:57 +01:00
Matthias Koefferlein c80e335cd6 WIP: global nets integration in cluster builder. 2019-01-07 02:08:59 +01:00
Matthias Koefferlein a4f0fd665e Provided a solution for connectivity through global nets. 2019-01-06 17:50:51 +01:00
Matthias Koefferlein 6cf7558384 WIP: preparations for global net extraction 2019-01-06 17:04:13 +01:00
Matthias Koefferlein 64c2548ab8 WIP: first steps towards global nets. 2019-01-06 15:28:40 +01:00
Matthias Koefferlein eb435d5d85 WIP: refactoring - separated pins of net into outgoing and subcircuit. 2019-01-06 12:53:22 +01:00
Matthias Koefferlein ec3a3b0f8c WIP: added ability to export nets to layouts. 2019-01-06 01:32:20 +01:00
Matthias Koefferlein bc4f9efa5d One more test for probing with a slightly more complex hierarchy. 2019-01-05 23:21:37 +01:00
Matthias Koefferlein f86f8149eb Fixed a bug that caused a segfault in the Layout2Netlist object (array repo references to original layout rather than to the working layout) 2019-01-05 22:40:53 +01:00
Matthias Koefferlein 15b79c9ddb IMPORTANT BUGFIX: array repo handling 
The issue: when cloning an array, the
"in_repository" flag might be left set. This
makes the system think the array is kept in
a repo. In the best case this creates a
memory leak.
 2019-01-05 21:55:06 +01:00
Matthias Koefferlein 6e468b43e0 WIP: bugfix - local to instance interaction did shortcut too early. 2019-01-05 10:12:55 +01:00
Matthias Koefferlein c31c87916c WIP: bugfix - array reference were not always considered correctly. 2019-01-05 01:34:10 +01:00
Matthias Koefferlein ad6d9b5715 WIP: provide a less memory intensive way to deliver shapes from nets. 2019-01-04 17:41:09 +01:00
Matthias Koefferlein 3fd99407a3 WIP: bugfix - hierarchical net extractor wasn't considering self-interactions between instance array elements. 2019-01-03 23:25:28 +01:00
Matthias Koefferlein 62d9941c4a WIP: Bugfix - hierarchy was dropping instances. 2019-01-03 22:09:19 +01:00
Matthias Koefferlein 20799026d1 WIP: bugfix in net extraction (wrong hierarchy treatment) 2019-01-03 18:26:18 +01:00
Matthias Koefferlein 76330bea3a Save some memory on net shape retrieval. 2019-01-02 23:23:04 +01:00
Matthias Koefferlein 509de593e6 Removed a compiler warning. 2018-12-31 01:42:55 +01:00
Matthias Koefferlein 9c607d7663 Added a first version of the layout to netlist extraction feature 
The main entry point is RBA::LayoutToNetlist which is the
GSI binding for the layout to netlist extractor. For a first
impression about the abilities of this extractor see the
Ruby tests in testdata/ruby/dbLayoutToNetlist.rb.

The framework itself consists of many classes, specifically

- RBA::Netlist for the netlist representation
- RBA::DeviceClass and superclasses (e.g. RBA::DeviceClassResistor and
  RBA::DeviceClassMOS3Transistor) for the description of devices.
- RBA::DeviceExtractor and superclasses (i.e. RBA::DeviceExtractorMOS3Transistor or
  the generic RBA::GenericDeviceExtractor) for the implementation of the
  device extraction.
- RBA::Connectivity for the description of inter- and intra-layer connections.
 2018-12-30 22:43:56 +01:00
Matthias Koefferlein f989a85642 WIP: introduced Circuit::is_external_net 2018-12-30 18:44:30 +01:00
Matthias Koefferlein 72a140957d WIP: added test for recursive net shape retrieval 2018-12-30 18:22:45 +01:00
Matthias Koefferlein 16a2b1982d WIP: added one more level of abstraction to layout-to-netlist extraction (db::LayoutToNetlist) for easier use. 2018-12-30 17:53:46 +01:00
Matthias Koefferlein b512f628bc WIP: specific device extractor and GSI binding. 2018-12-30 14:54:59 +01:00
Matthias Koefferlein c841b84867 WIP: some minor refactoring. 2018-12-30 13:37:52 +01:00
Matthias Koefferlein 293c6f496e WIP: more query functions for netlist classes (i.e. net by name, device by name etc.), some refactoring, GSI bindings, tests. 2018-12-30 13:00:03 +01:00
Matthias Koefferlein 425acda31a WIP: GSI binding of device extractor classes. 2018-12-30 11:32:33 +01:00
Matthias Koefferlein 44b5b2742e WIP: tests for specialized device classes and device combination 2018-12-29 22:58:29 +01:00
Matthias Koefferlein 45b35f3aae WIP: to_string for netlist, tests, some bugfixes on device combination. 2018-12-29 22:18:58 +01:00
Matthias Koefferlein edbafae43e WIP: make top level pins for named nets and netlist purging. Tests. 2018-12-29 20:50:35 +01:00
Matthias Koefferlein 54adb84e27 WIP: locking of netlist for better performance. 2018-12-29 01:04:48 +01:00
Matthias Koefferlein d57ede441c WIP: netlist topology - children, parents, top-down and bottom-up iteration. 2018-12-29 00:48:28 +01:00
Matthias Koefferlein 2f48479838 WIP: a bit of simplification, renaming of methods, parents for subcircuits, devices. References for circuits pointing to subcircuits. 2018-12-28 22:51:11 +01:00
Matthias Koefferlein a5b9cbfe5b WIP: device extractor now declares it's layers, passing layers by name supported now. 2018-12-28 01:53:27 +01:00
Matthias Koefferlein c665d6aceb WIP: introduced error messaging for device extractor. 2018-12-28 01:06:17 +01:00
Matthias Koefferlein 411c18cdb4 WIP: also test parameter extraction in device extraction test. 2018-12-27 21:06:35 +01:00
Matthias Koefferlein 1c41c43b95 WIP: rename netlist extractor test. 2018-12-27 10:58:48 +01:00
Matthias Koefferlein d6473b4d84 WIP: moved netlist extractor into right place. 2018-12-27 10:57:46 +01:00
Matthias Koefferlein 8b2902c31b WIP: introduced expanded net name 2018-12-27 10:43:25 +01:00
Matthias Koefferlein 639b0026d3 WIP: some refactoring for better consistency and easier usage of the device extractor. 2018-12-27 10:33:08 +01:00
Matthias Koefferlein bfae347ffb WIP: renaming sub_circuit->subcircuit for consistency 2018-12-27 02:02:17 +01:00
Matthias Koefferlein f0f620b1cd WIP: added subcircuit IDs for easier referencing. 2018-12-27 01:58:34 +01:00
Matthias Koefferlein 795a77f7ce WIP: take care of the property name used for device terminal annotation. 2018-12-27 01:39:28 +01:00
Matthias Koefferlein 62ffcd38e6 WIP: refactoring of the netlist property thing. Now it's internal and there is only the device terminal property. The property also does not store device pointers but just IDs 2018-12-27 01:27:58 +01:00
Matthias Koefferlein f5071d3254 WIP: some more refactoring. 2018-12-27 01:03:52 +01:00
Matthias Koefferlein 2171b98bd8 WIP: introduced device IDs 2018-12-27 00:59:44 +01:00
Matthias Koefferlein 724d1bc255 WIP: some small refactoring. 2018-12-27 00:32:40 +01:00
Matthias Koefferlein 8f568641e0 WIP: some refactoring, added label recognition to net extraction, test enhancements. 2018-12-27 00:20:21 +01:00
Matthias Koefferlein 024907e7ef WIP: first test for device extraction. 2018-12-26 10:02:34 +01:00
Matthias Koefferlein 1db5ad016c WIP: added first tests for device extraction. 2018-12-26 00:39:46 +01:00
Matthias Koefferlein bfc0e24d50 WIP: fixed some compiler warnings. 2018-12-26 00:36:34 +01:00
Matthias Koefferlein 88c60420d0 WIP: fixed verbosity of some output. 2018-12-26 00:34:34 +01:00