4394aff909
Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
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Conflicts:
tgt-vhdl/stmt.cc
2008-10-05 12:44:30 +01:00
f233793061
Spelling fixes
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No code changes.
2008-09-09 19:21:42 -07:00
a34348bb35
Add (temporary) error for ICT_SCOPE_GENERATE
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Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
2008-09-06 11:38:37 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
c0c838f1bc
Logic devices now working again
2008-07-29 12:11:44 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
65c2ceb89d
Build entity hierarchy in separate stages
2008-07-29 11:01:02 +01:00
e25f946ac0
Merge branch 'vhdl' of file:///media/disk/data/iverilog/ into vhdl
2008-07-21 15:20:42 +01:00
2f4f075005
Typo
2008-07-21 15:20:40 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
3bd480a375
Allow ouput to be read if connected to child output
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If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
4e73b1b133
Fix bug when resolving nexus to VHDL signal
2008-06-30 17:47:45 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
af8c08e6a7
Allow optional VHPI $finish implementation
2008-06-17 20:16:16 +01:00
d6193c1622
Add _Reg internal signal if output is registered
2008-06-13 12:34:27 +01:00
b8c1f9ab67
A system for linking ivl_signal_t to entities
2008-06-12 20:26:23 +01:00
234f73e7bf
Don't generate any output if there were errors
2008-06-04 21:03:36 +01:00
4bf2e1669d
Store packages required with entity rather than globally
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Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
fe80da362c
Collect required packages as compilation progresses
2008-06-03 19:14:47 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
5cbd587833
Clean up generated objects
2008-05-31 16:08:57 +01:00
8189c4ee43
Generate VHDL entities and architectures for all module scopes
2008-05-31 15:28:25 +01:00
05de2f56b4
Dummy code for processes
2008-05-30 01:04:47 +01:00
e38494a10c
Pretty-print VHDL output
2008-05-29 16:24:16 +01:00
bfa2bfc8ae
Makefile and autoconf changes to build VHDL code generator
2008-05-28 17:17:39 +01:00
Nick Gasson
Larry Doolittle