e569e07d4e
vhdlpp: Type 'NATURAL' is translated to 'int unsigned'.
2015-02-19 17:07:41 +01:00
763c6fe3c9
vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
...
To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
12b4914b63
vhdlpp: ExpName resolves enum values.
2015-02-17 10:15:57 +01:00
19ff6a434b
vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances).
2015-02-05 12:00:25 +01:00
1a367c84b6
vhdlpp: Subprograms can have instances that take a different set of parameter types.
2015-02-05 11:25:03 +01:00
60077f4f06
vhdlpp: ExpBitstring elaborate_expr().
2015-02-05 11:25:03 +01:00
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
9ba7694484
vhdlpp: Minor assert.
2015-02-04 16:57:43 +01:00
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fde6525acb
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
2014-10-01 14:56:32 +02:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
54696e0127
vhdlpp: Elaboration & emit support for aggregate initializer expressions in records.
2014-09-17 11:24:16 +02:00
69b145e216
Minor cleaning for valgrind output.
2014-08-06 15:01:28 +02:00
5ed60a151f
Added support for real type in vhdlpp.
2014-08-06 15:00:35 +02:00
21b24c7725
Fix more compile warnings and a minor bug
2013-07-11 19:10:25 -07:00
8487cb5616
Do a better job of figuring the vtype of an expression.
2013-06-12 14:21:36 -07:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
...
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
11682fc7eb
Harmless cleanup of comments / initialization warnings.
2013-04-18 18:18:40 -07:00
c14134aa2e
Handle genvar variables in expressions.
...
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
85e000ed0c
Handle prefix expressions that include array index expressions.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
369a0b9eca
VHDL named types work in more places.
2012-05-22 17:31:27 -07:00
63b7fe059d
Reword concat to handle aggregate arguments.
...
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
71d2401221
Handle VHDL records.
...
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
ae06863db1
Elaborate prefix names which may be structure variables.
2012-05-22 17:31:26 -07:00
021d944a30
Probe type of ExpName with a record prefix.
2012-05-22 17:31:25 -07:00
7eb89c5548
Parse name prefix syntax for record member reference.
...
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
9b816f6478
Add support for nested when/else expressions.
2012-05-22 17:31:25 -07:00
0775e36a67
Properly elaborate argument types for binary relation expressions.
...
The argument types of binary relation expressions are decoupled
from the return type for the expression itself.
2012-05-22 17:31:25 -07:00
84f14dbc81
Spelling fixes to vhdlpp tree
...
Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
8e0beff3ab
Handle arrays of vectors in VHDL types.
...
This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
a109df04bb
Proper expression type for vhdl relation expressions.
2011-10-16 11:02:07 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
...
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
873a447b5c
Evaluate VHDL <name>'length attribute at compile time.
2011-09-18 17:45:06 -07:00
f0e61a1db7
Basic vhdl elaboration for unary not operator.
2011-09-18 15:13:30 -07:00
3497e2e663
Distinguish bit selects of entity ports from function calls.
...
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
563d73e7d9
Index/part select of VHDL l-values changes expression type
...
The changed expression type impacts how code is generated
for the r-value expression.
2011-09-03 17:57:37 -07:00
6d28c989ce
Handle the basics of aggregate expressions
...
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
4464c5849b
Handle a few built-in functions internally.
...
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
7556a37859
Parse function calls, and detect type case expressions.
...
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
f5220c54f1
Handle variables in process statements
...
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
72769146ee
Remove all the user code compilation warnings
...
Remove all the compilation warnings that are from user changeable code.
There are still some warnings related to the flex generated lexor code.
2011-07-30 09:37:14 -07:00
981425fcce
Add semantics check in component instantiation
...
There have been applied rules for port and signal
association in component instatiation statements
described in the VHDL standard.
2011-07-24 10:14:41 -07:00
e2932cb6b5
Add ExpName::elaborate_rval member function
...
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
2011-07-19 21:29:05 -07:00
721f9d5d9b
Add String Expression to the VHDL parser
2011-07-08 18:05:06 -07:00
d14f60f28a
Elaborate and emit vhdl elsif sections.
...
The IfStatement contains a list of elsif sections that need
to be elaborated/emitted in the middle of the true and false
clauses.
2011-06-22 18:13:40 -07:00
Maciej Suminski
Cary R
Stephen Williams
Arun Persaud
Larry Doolittle
Pawel Szostek