When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Stephen Williams