Nick Gasson
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e5ef0d97bd
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Fix signed/unsigned resizing
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2008-06-23 13:04:28 +01:00 |
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Nick Gasson
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08d80b35cb
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Rename signals that would be illegal VHDL names
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2008-06-19 16:15:47 +01:00 |
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Nick Gasson
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561953e494
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Minial LPM to support continuous assignments
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2008-06-16 19:41:01 +01:00 |
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Nick Gasson
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83a7796b74
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Make sure signal names conform to VHDL rules
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2008-06-16 17:37:17 +01:00 |
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Nick Gasson
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2fb57805ea
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Use signed rather than std_logic_vector
Arithmetic operators now working correctly
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2008-06-14 18:03:25 +01:00 |
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Nick Gasson
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005df31a0d
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Use renamed signal in expressions, if there is one
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2008-06-13 12:39:18 +01:00 |
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Nick Gasson
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d6193c1622
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Add _Reg internal signal if output is registered
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2008-06-13 12:34:27 +01:00 |
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Nick Gasson
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26a2c69c2e
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Change architecture name to `FromVerilog'
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2008-06-11 11:31:43 +01:00 |
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Nick Gasson
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babe694366
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Generate port mappings
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2008-06-10 13:58:41 +01:00 |
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Nick Gasson
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7560b29fb9
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Find signals to map together
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2008-06-10 12:21:48 +01:00 |
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Nick Gasson
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3106fe0ed6
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Generate port declarations for entities.
But doesn't emit them yet!
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2008-06-09 16:27:04 +01:00 |
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Nick Gasson
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e29954e03f
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Generate concurrent assignments from logic gates
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2008-06-09 15:05:32 +01:00 |
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Nick Gasson
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3b5d56e087
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Allow n-ary expressions
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2008-06-09 14:53:50 +01:00 |
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Nick Gasson
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aa91186119
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Add AST elements for unary/binary expressions to model logic gates
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2008-06-09 14:39:58 +01:00 |
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Nick Gasson
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d08f5af9c6
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Add concurrent assignments
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2008-06-09 14:21:55 +01:00 |
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Nick Gasson
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b96e471fa2
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Stub code for handling logic gates
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2008-06-09 14:08:27 +01:00 |
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Nick Gasson
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110a1b2ac7
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Replace type classes with enumeration
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2008-06-08 12:48:56 +01:00 |
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Nick Gasson
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fbf85398da
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Support converting bit strings to std_logic
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2008-06-07 16:19:10 +01:00 |
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Nick Gasson
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8c3461f0ff
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Generate sensitivity lists properly and add signal declarations
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2008-06-07 11:48:38 +01:00 |
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Nick Gasson
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c3ac1aac8c
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Remove debugging messages from output
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2008-06-04 21:07:50 +01:00 |
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Nick Gasson
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7bd1565cfb
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$display now (mostly) working
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2008-06-04 20:42:44 +01:00 |
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Nick Gasson
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ab6ae621cb
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Remove useless comments in output
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2008-06-02 20:24:25 +01:00 |
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Nick Gasson
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17ae0a6a09
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Fix a bug where the same instantiation appeared multiple times
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2008-06-02 18:05:39 +01:00 |
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Nick Gasson
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041925c123
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Component instantiation to replicate Verilog hierarchy
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2008-06-02 17:45:58 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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7c9d154461
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Forgot source files for entity generation
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2008-05-31 15:31:48 +01:00 |