Nick Gasson
|
849e7cb4d5
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Add equality operator
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2008-06-16 12:20:28 +01:00 |
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Nick Gasson
|
92c823680a
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Fix crash when `if' statement had no `else'
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2008-06-16 12:13:01 +01:00 |
|
Nick Gasson
|
8a9486eb49
|
Eliminate useless Resize() call
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2008-06-14 18:11:10 +01:00 |
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Nick Gasson
|
2fb57805ea
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Use signed rather than std_logic_vector
Arithmetic operators now working correctly
|
2008-06-14 18:03:25 +01:00 |
|
Nick Gasson
|
919c1d695c
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Adding binary +
|
2008-06-14 17:09:31 +01:00 |
|
Nick Gasson
|
0ea64ad8ab
|
Correct misleading comment
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2008-06-13 14:47:06 +01:00 |
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Nick Gasson
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9fbb449e06
|
Optimise away empty (VHDL) processes
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2008-06-13 14:17:24 +01:00 |
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Nick Gasson
|
be3c4cf268
|
Generate signal initial values from `initial' processes
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2008-06-13 14:10:28 +01:00 |
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Nick Gasson
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0a8fd50c4a
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Find assignments that could be initializers
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2008-06-13 13:59:48 +01:00 |
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Nick Gasson
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70db096b6d
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Clean up the edge detector code a bit
|
2008-06-13 12:52:20 +01:00 |
|
Nick Gasson
|
005df31a0d
|
Use renamed signal in expressions, if there is one
|
2008-06-13 12:39:18 +01:00 |
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Nick Gasson
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d6193c1622
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Add _Reg internal signal if output is registered
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2008-06-13 12:34:27 +01:00 |
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Nick Gasson
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b8c1f9ab67
|
A system for linking ivl_signal_t to entities
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2008-06-12 20:26:23 +01:00 |
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Nick Gasson
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0df3eabe26
|
Convert `if (foo) ..' to `if foo = '1' then ..'
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2008-06-12 11:36:21 +01:00 |
|
Nick Gasson
|
8fe2211e2b
|
Generate `after' modifier instead of `wait' statements
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2008-06-12 11:24:43 +01:00 |
|
Nick Gasson
|
645ee2003f
|
Translation for unary not
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2008-06-12 10:56:28 +01:00 |
|
Nick Gasson
|
d6f1162547
|
Generate correct VHDL signal values
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2008-06-12 10:50:46 +01:00 |
|
Nick Gasson
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46991aa65c
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Generate process bodies in the right place
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2008-06-12 10:47:52 +01:00 |
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Nick Gasson
|
7eb41304e6
|
Generate rising/falling edge detectors
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2008-06-12 10:36:38 +01:00 |
|
Nick Gasson
|
19e60b698f
|
Translate if statements
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2008-06-11 14:20:05 +01:00 |
|
Nick Gasson
|
a7cfdc3a87
|
Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
|
Nick Gasson
|
b010b8e3ca
|
Use `assert false' as initial translation of $finish
|
2008-06-11 13:37:21 +01:00 |
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Nick Gasson
|
26a2c69c2e
|
Change architecture name to `FromVerilog'
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2008-06-11 11:31:43 +01:00 |
|
Nick Gasson
|
5a7cfd8c02
|
Clean up vhdl_comp_inst
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2008-06-10 14:00:15 +01:00 |
|
Nick Gasson
|
babe694366
|
Generate port mappings
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2008-06-10 13:58:41 +01:00 |
|
Nick Gasson
|
7560b29fb9
|
Find signals to map together
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2008-06-10 12:21:48 +01:00 |
|
Nick Gasson
|
f6753a9013
|
Add ports to component declarations
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2008-06-10 11:24:16 +01:00 |
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Nick Gasson
|
191187ed1b
|
Cosmetic change to avoid useless `null' statement after delay
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2008-06-09 16:40:32 +01:00 |
|
Nick Gasson
|
1fb01d4d98
|
Emit port declarations
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2008-06-09 16:37:05 +01:00 |
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Nick Gasson
|
3106fe0ed6
|
Generate port declarations for entities.
But doesn't emit them yet!
|
2008-06-09 16:27:04 +01:00 |
|
Nick Gasson
|
e29954e03f
|
Generate concurrent assignments from logic gates
|
2008-06-09 15:05:32 +01:00 |
|
Nick Gasson
|
3b5d56e087
|
Allow n-ary expressions
|
2008-06-09 14:53:50 +01:00 |
|
Nick Gasson
|
aa91186119
|
Add AST elements for unary/binary expressions to model logic gates
|
2008-06-09 14:39:58 +01:00 |
|
Nick Gasson
|
d08f5af9c6
|
Add concurrent assignments
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2008-06-09 14:21:55 +01:00 |
|
Nick Gasson
|
b96e471fa2
|
Stub code for handling logic gates
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2008-06-09 14:08:27 +01:00 |
|
Nick Gasson
|
7120ab7b13
|
Expression type might be null in some cases
|
2008-06-09 12:54:21 +01:00 |
|
Nick Gasson
|
2f5dcda3b6
|
Delay statements now translated correctly
|
2008-06-09 12:49:38 +01:00 |
|
Nick Gasson
|
120b5dc80e
|
Add constant integers
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2008-06-09 12:46:55 +01:00 |
|
Nick Gasson
|
d762253f74
|
Wait statements
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2008-06-09 12:40:59 +01:00 |
|
Nick Gasson
|
1d28b935e8
|
Split vhdl_element.cc into multiple files
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2008-06-08 13:27:48 +01:00 |
|
Nick Gasson
|
4b4a1c6cac
|
Tidy up type casting
|
2008-06-08 12:55:18 +01:00 |
|
Nick Gasson
|
110a1b2ac7
|
Replace type classes with enumeration
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2008-06-08 12:48:56 +01:00 |
|
Nick Gasson
|
79558910d1
|
Catch case where NULL return wasn't detected
|
2008-06-07 16:44:01 +01:00 |
|
Nick Gasson
|
fbf85398da
|
Support converting bit strings to std_logic
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2008-06-07 16:19:10 +01:00 |
|
Nick Gasson
|
1e4b96aa0a
|
Simplify code a bit as rval type is never needed
|
2008-06-07 14:57:20 +01:00 |
|
Nick Gasson
|
c064ae6bc3
|
Generate VHDL for non-blocking assignments
|
2008-06-07 14:54:00 +01:00 |
|
Nick Gasson
|
39228f3495
|
VHDL AST element for non-blocking assignment
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2008-06-07 14:31:33 +01:00 |
|
Nick Gasson
|
12e2237131
|
Add Type'Image cast to $display parameters
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2008-06-07 14:21:50 +01:00 |
|
Nick Gasson
|
066a9b7a61
|
Add AST element for function call expressions
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2008-06-07 13:29:27 +01:00 |
|
Nick Gasson
|
cdb180e1d4
|
Associate a type with each VHDL expression node
|
2008-06-07 13:23:21 +01:00 |