I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
BOOL values have a specific cast from LOGIC, this node takes care
of it. Also arrange for the elaboration to insert them in the right
planes and for the code generator to generate them.
This patch adds -Wextra to the compilation flags for C++ files in
the vvp and vpi subdirectories. It also fixes all the problems
found while adding -Wextra. This mostly entailed removing some of
the unused arguments, removing the name for others and using the
correct number of initializers.
This patch adds support for running cppcheck from the Makefile. It also
standardizes the order of some of the targets. It renames vpip_format.c
to vpip_format.cc and fixes the size of the array tables to make room
for the trailing NULL. Found when using a C++ compiler.
This patch adds a few missing initializations to various constructors
in the vvp directory. It also enhances the array alias code to copy
more values from the aliased array.
Starting in autoconf 2.68, "the macros AC_PREPROC_IFELSE,
AC_COMPILE_IFELSE, AC_LINK_IFELSE, and AC_RUN_IFELSE now warn if the
first argument failed to use AC_LANG_SOURCE or AC_LANG_PROGRAM to
generate the conftest file contents."
IVL_VT_BOOL variables at the code generator should generate
.var/2x records so that the run time can do 2-value optimizations
and otherwise support atom2 values.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
Create the .var/2u and .var/2s variable records and give them
basic implementations. Make available to VPI the proper types
for the SystemVerilog types that these variables represent.
Follow-up to "Brainless start to const-correct changes"
Still actually does nothing, but now if the #define ICARUS_VPI_CONST
in vpi_user.h is changed to const, Icarus is almost const-correct,
as checked with gcc flags -Wcast-qual -Wwrite-strings.
Choosing when to #define ICARUS_VPI_CONST const is left as an
exercise for the reader.
With these two patches applied, and the const define, there are
still about a dozen const problems left.
Results of running
cd vpi
for f in *.c *.h; do sed -i \
-e "s/_calltf(PLI_BYTE8/_calltf(ICARUS_VPI_CONST PLI_BYTE8/" \
-e "s/_compiletf(PLI_BYTE8/_compiletf(ICARUS_VPI_CONST PLI_BYTE8/" $f; done
and a trivial patch to vpi_user.h to, among other things, make
ICARUS_VPI_CONST blank.
Thus, this patch does absolutely nothing. Will be followed by a
(much shorter) patch that makes it do something. :-)
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
Conflicts:
tgt-vhdl/scope.cc
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Conflicts:
tgt-vhdl/cast.cc
tgt-vhdl/display.cc
tgt-vhdl/vhdl_syntax.cc
tgt-vhdl/vhdl_target.h
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
Conflicts:
tgt-vhdl/process.cc
tgt-vhdl/stmt.cc
tgt-vhdl/vhdl_target.h
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
An unsized signed constant that is smaller than integer_width needs
to be resized up to either the integer_width or the expression width
whichever is smaller.
Stephen Williams
Nick Gasson
Cary R
Jared Casper
Larry Doolittle