301e85a8ca
Merge pull request #122 from orsonmmz/resize_fix
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vhdlpp update
2016-09-02 10:01:02 -07:00
5dd2e6a7c8
vhdlpp: Corrected standard library function headers
2016-09-01 12:08:44 +02:00
8ba3d62071
vhdlpp: Better resize() implementation.
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Previous version did not work well with signed expressions or expressions that
were temporarily resized (e.g. a + 32'd42, where a is a[7:0]).
2016-09-01 12:08:44 +02:00
bab39dae19
vhdlpp: Some of the standard library functions are imported only on request
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Previously they have been always enabled, now it is required to put a
'use' directive.
2016-09-01 12:08:44 +02:00
089dd037d6
vhdlpp: Use the wider variable size for arith operations on (un)signed
2016-09-01 12:08:44 +02:00
25f4a54852
vhdlpp: Subprograms are matched once. ExpFunc::probe_type() return exact type
2016-09-01 12:08:44 +02:00
8f86004100
vhdlpp: Clearer error messages
2016-09-01 12:08:44 +02:00
07543315cf
vhdlpp: Stricter array type matching
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Arrays type match if they have a common parent, instead of the
element type. Now (un)signed & std_logic_vector types do not match,
as it should be in VHDL.
2016-09-01 12:08:43 +02:00
fe77b0ac87
vhdlpp: VTypeArray::dimensions() returns std::vector<range_t>
2016-09-01 12:08:43 +02:00
643a3f2f2c
vhdlpp: Do not evaluate generics.
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They might change depending on the instance, so they cannot be evaluated using the default value.
2016-09-01 12:08:43 +02:00
ed3e67926f
vhdlpp: Evaluate conditional signal assignments upon simulation start.
2016-09-01 12:08:43 +02:00
798adc9863
vhdlpp: Support for unary sign operator.
2016-09-01 12:08:43 +02:00
9e95ae5859
vhdlpp: Moved Exp*::dump() methods from debug.cc to expression_debug.cc.
2016-09-01 12:08:39 +02:00
d44c814bab
Remove .alias records from vvp generated code.
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Net arrays can be handled by nets directly, instead of creating
.alias records.
2016-08-31 14:05:09 -07:00
41075a45e6
Fix for GitHub issue #121 - correctly determine ivl_root.
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Pull request #116 added the ability for the iverilog driver to determine
ivl_root from the location of the iverilog executable (this is needed to
support relocation at the time iverilog is installed). However, the code
did not support the possible variations in the library path name.
2016-08-24 00:00:24 +01:00
a2fbdeff78
Add some pass by reference to vvp
2016-08-14 22:26:16 -07:00
ad5a7f7ca3
Update cppcheck vvp suppression file
2016-08-14 21:18:55 -07:00
d0e0776910
Make the base class match the derived classes regarding passing by reference
2016-08-14 21:18:44 -07:00
255701a787
Fix space issue
2016-08-14 20:55:55 -07:00
5f1e63604c
Update cppcheck vpi suppression file
2016-08-14 20:53:57 -07:00
9cf23b4c3b
Make getting ivl_root more robust
2016-08-14 19:41:35 -07:00
446e825ed3
Fix space issues
2016-08-14 19:37:40 -07:00
1d4230472a
Fix getting timeunit outside of module to use a defined check value
2016-08-14 17:26:23 -07:00
13189f7431
Update fstapi.c to latest from GTKWave
2016-08-14 12:46:48 -07:00
b51e58fa9d
Fix for br1007 - out-of-range constant bit select should be a warning.
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An out-of-range constant bit select on the LHS of an assignment was being
treated as an error, whereas an out-of range constant part select would
only result in a warning. In any other context, either case would result
in a warning, so convert the error to a warning.
In addition, all warnings for out-of-range or undefined constant bit/part
selects should be controlled by -Wselect-range.
2016-08-08 22:10:16 +01:00
8461e1d9c4
Fix vlog95 target to handle hierarchical references in root-level tasks.
2016-07-26 22:01:22 +01:00
2bc42fc6e2
Fix for GitHub issue #104 - assigning hierarchical signal from top level task.
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When emitting a design, all scopes must be emitted before emitting any
top level task/function/method definitions, otherwise hierarchical
references can't always be resolved.
2016-07-26 22:01:22 +01:00
7d5f6c551a
Fix unused variable warning and assumed buffer size from last merge.
2016-07-23 12:01:58 +01:00
191811f78f
Merge branch 'conda-fix' of https://github.com/tfors/iverilog
2016-07-23 11:40:09 +01:00
b1b91f49c8
Update vlog95 target to handle timescales for root scope tasks/functions.
2016-07-23 00:10:01 +01:00
27213f2af8
Fix for GitHub issue #115 - synthesis aborts on case with max guard of 0.
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The calculation of the required multiplexer width was incorrect for
the corner case of a single guard value of zero.
2016-07-22 23:09:36 +01:00
7bed181f68
Support timescales in design units that aren't inside a module.
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SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
e316cc708b
Fix assignment of outputs from class methods.
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As for inputs, skip over the implicit 'this' parameter.
2016-07-21 19:06:21 +01:00
b8f9ed27c5
Fix for br1003 - prevent segfault when delays are used outside a module.
2016-07-21 08:40:45 +01:00
cada40ebd1
Updated comments
2016-07-18 08:10:41 -05:00
3afbb903d6
Use /proc/self/exe on linux, if it exists, to find ivl_root
2016-07-18 08:05:16 -05:00
43cd693fe0
Put start events to proper queue.
2016-07-17 09:47:08 -07:00
c37d6ac3ac
Merge branch 'master' of github.com:steveicarus/iverilog
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Conflicts:
vhdlpp/parse_misc.cc
vhdlpp/vtype.cc
2016-07-17 09:36:34 -07:00
ad1101cc80
Fix for br1005 - segfault when SV queue is declared inside a class.
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For now, output a "sorry" message to indicate this is not yet
supported.
2016-07-11 20:04:24 +01:00
ad87704809
Partial fix for br1006 - allow part selects in path declarations.
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This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
2016-07-10 20:00:39 +01:00
7f612270b3
Improved fix for GitHub issue #112 .
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This does a better job of setting the intermediate expression types
and widths when calculating the canonical index into a packed array.
It still doesn't properly handle out-of-bound indices (br953).
2016-07-10 13:30:58 +01:00
1448210f28
Fix for GitHub issue 112 - index calculation for >2D packed arrays.
2016-07-09 23:33:33 +01:00
d496b095ff
Fix vector width calculation for multi-dimensional packed arrays.
2016-07-09 17:10:22 +01:00
e1ec23d160
Merge pull request #114 from wzab/master
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Changes necessary to compile with gcc on Debian/Linux testing
2016-07-09 09:04:24 +01:00
2c52fd65d3
Changes necessary to compile with gcc on Debian/Linux testing
2016-07-07 23:01:02 +02:00
6c7495c93e
Merge branch 'master' of github.com:steveicarus/iverilog
2016-07-05 07:59:29 -07:00
f03e9d4180
Merge pull request #113 from CastMi/original_master
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Checks for pointers
2016-07-05 07:59:16 -07:00
540bb5afa6
Revert "Update parse_misc.cc"
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This reverts commit 6d06e9351a
2016-07-05 07:56:18 -07:00
f657d1d7d7
Revert "Update vtype.cc"
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This reverts commit 49515ff62b
2016-07-05 07:56:06 -07:00
70031c9d0f
Merge pull request #111 from forflo/master
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Resolved #110
2016-07-05 07:50:52 -07:00
Stephen Williams
Maciej Suminski
Martin Whitaker
Cary R
Thomas Fors
Yury Gribov
martinwhitaker
Wojciech M. Zabolotny