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8505 Commits

Author SHA1 Message Date
steve 47a444fb92 Calculate expression widths at elaboration time. 1998-11-07 19:17:10 +00:00
steve b118634189 Handle procedural conditional, and some 
of the conditional expressions.

 Elaborate signals and identifiers differently,
 allowing the netlist to hold signal information.
 1998-11-07 17:05:05 +00:00
steve 5836c8aa4b Properly dump 0 length numbers. 1998-11-07 17:04:48 +00:00
steve 43c20f33c8 Make sure dep is a directory. 1998-11-07 17:01:36 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00