0aa5487214
Check pointers before dereferencing
2016-06-30 17:47:34 +02:00
3aa9d535f1
Avoid out of bounds
2016-06-30 17:47:34 +02:00
9ad46044b4
Cleanup
2016-06-30 17:47:34 +02:00
2d7534b005
Implement barrel shifter LPM for BLIF target
2016-06-13 10:55:38 -07:00
31482cbceb
Implement sign extension LPM for BLIF target
2016-06-13 10:51:46 -07:00
2d5a48c579
Support PULLUP/DOWN and BUFZ in BLIF backend
2016-06-13 10:26:46 -07:00
6d06e9351a
Update parse_misc.cc
...
Fixed bug described in #110
2016-06-13 00:56:43 +02:00
49515ff62b
Update vtype.cc
...
Fixed bug described in #110
2016-06-13 00:55:28 +02:00
8234f1845d
Fix for GitHub issue #106 - prevent VPI writes during read-only synch.
2016-06-09 21:27:20 +01:00
332170d36b
Fix for GitHub issue #105 - fully support SV macro escape sequences.
...
The existing support for ``, `", and `\`" did not work in nested macro
definitions. Note that the new implementation only detects and replaces
these sequences inside the macro text (as required by the IEEE standard),
whereas the old implementation would detect and replace them anywhere in
the source files.
2016-06-06 20:12:04 +01:00
45fbf55806
Add basic support for parameters using typedefs
2016-05-14 10:34:50 -07:00
61c82d2cb0
Handle mixed continuous and non-blocking assignments to same vector.
...
SystemVerilog allows a mixture of procedural and continuous assignments
to be applied to different parts of the same vector. The previous attempt
to make this work for non-blocking assignments was flawed (see preceding
fix for vvp_fun_part_pv::recv_vec4_pv). Instead, handle this case by
converting the non-blocking assignment into a delayed force statement,
which matches the way mixed continuous and blocking assignments are
handled.
2016-05-10 22:16:40 +01:00
0c66116f51
Fix for GitHub issue #103 - vvp assertion failure on part select propagation.
...
The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.
2016-05-10 21:59:21 +01:00
a219df2f18
Merge pull request #95 from orsonmmz/automatic_rebased
...
vhdlpp: Specify lifetime for variables.
2016-05-04 08:05:01 -07:00
6e5ed73b09
Extended fix for GitHub issue #99 .
...
Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.
2016-04-18 23:47:43 +01:00
b2f7d09f0d
Fix GitHub issue #99 - recv_vec4_pv not implemented for arithmetic functors.
...
Also initialise the stored operand values to 'bz instead of 'bx to get
the correct results when bits are not driven.
2016-04-04 22:29:54 +01:00
6ba2bee977
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 20:40:30 +01:00
9f88b26a67
Fix vlog95 target to handle delayed CA to vector part select.
2016-04-02 22:24:14 +01:00
20104c92c8
Fix for GitHub issue #96 - support mixed constant/variable delays in vvp.
...
If all three rise/fall/decay delay values are constant, we can use
the vvp .delay statement variant that takes three literal numbers.
If not, we have to use the variant that takes three net inputs. If
some of the delay values are constant, we need to create constant
drivers for those delay inputs.
2016-04-02 19:55:56 +01:00
4521be4510
More spelling, comments only
2016-04-01 11:02:34 -07:00
89edf62206
Capitalize Verilog in a few places
2016-04-01 11:02:24 -07:00
163a913559
vhdlpp: Specify lifetime for variables.
2016-03-29 11:27:14 +02:00
b7d263462c
vhdlpp: Fixed automatic variables initalization in subprograms.
2016-03-29 11:27:14 +02:00
4c82352229
vhdlpp: Corrected the comment mark from the previous commit.
2016-03-29 11:27:14 +02:00
97e31ec9fa
vhdlpp: Workaround to make subprograms work as if they were automatic.
2016-03-29 11:27:14 +02:00
d6ef813a20
vhdlpp: Emit subprograms as automatic by default.
2016-03-29 11:27:14 +02:00
7f475d4210
Refactor to use new pad_to_width/cast_to_width functions.
2016-03-25 22:23:45 +00:00
dc1c3a4043
Fix for GitHub issue #94 - enhance support for SystemVerilog size casting.
...
Allow the size expression to be any constant expression. Also ensure that
the expression width and type are correctly calculated and applied.
2016-03-25 21:49:28 +00:00
b5324c7ba2
Fix reference to undefined value (valgrind)
2016-03-24 23:43:07 -07:00
fb77cc4000
Fix a cppcheck warning
2016-03-24 20:23:47 -07:00
9538c81d34
Add check for explicit lifetime when initialising static variables.
...
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.
Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
2016-03-19 20:44:36 +00:00
6e718c2e0c
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 17:27:27 +00:00
7c3cee5f7a
Updated comment in tgt-vlog95 to reflect changes in variable initialization.
2016-03-19 14:47:38 +00:00
0dcb46e4c4
Fix shadow warning.
2016-03-19 14:42:34 +00:00
72bb63cf42
Variable initialization blocks should be unamed.
...
Also add file/line info to initial process.
2016-03-19 14:21:10 +00:00
54feb89bf5
For SystemVerilog, run variable initialization before main simulation starts.
2016-03-19 13:46:09 +00:00
635adfc01e
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 13:04:38 +00:00
28b446ca30
Use correct type when printing supply pull message
2016-03-15 03:49:20 -07:00
78a49eacef
Merge branch 'master' of github.com:steveicarus/iverilog
2016-03-14 12:26:12 -07:00
1784488096
Spelling and whitespace
2016-03-14 12:25:50 -07:00
dbaf2471f2
Fix for br1001 - connect undriven wand/wor to 'bz in tgt-vvp.
2016-03-13 16:38:55 +00:00
a5dac08a50
tgt-vlog95: Find the original signal when a port connection is cast.
2016-03-12 23:22:14 +00:00
c4b3f256af
Don't mislabel signals as ports when casting port connections.
...
The original signal should retain the port type. Moving it to the cast
signal was confusing the vlog95 and stub targets.
2016-03-12 23:17:54 +00:00
081f5e6960
tgt-vlog95: Fix infinite loop caused by searching the wrong scope.
2016-03-12 23:11:11 +00:00
5d9a196819
tgt-vlog95: Handle variable initialisation in named blocks.
2016-03-12 23:06:54 +00:00
dc189fec8c
Added new vvp latch statement to README file.
2016-03-12 12:14:03 +00:00
9d487c6951
vhdlpp: Fixed a few shadow warnings.
2016-03-12 12:03:17 +00:00
708a7d0621
Move some redundant initialisation of bitmasks in synthesis.
...
These are made obsolete by an earlier bugfix.
2016-03-12 12:02:22 +00:00
b4d438ea9f
Fixed bug in vlog95 dff output when using asynchronous set.
2016-03-12 11:39:32 +00:00
22bc798696
Added warning when a latch enable is a synthesised expression.
2016-03-12 11:21:23 +00:00
Michele Castellana
Yury Gribov
anon
Martin Whitaker
Cary R
Stephen Williams
Larry Doolittle
Maciej Suminski