651d208451
Remove some uneccessary zero-time waits from VHDL outputs
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This patch optimises away straight line sequences like:
wait for 0 ns;
wait for X ns;
to:
wait for X ns;
This tidies up the output a bit.
It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
2008-12-07 16:53:47 -08:00
1cc5586c4d
Add debugging output to VHDL target
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Prints progress when -pdebug=1 specified.
Adds a new debug_msg function to print progress messages.
2008-11-29 20:16:09 -08:00
a60216ec15
Use ivl_process_* functions for file/line number information
2008-08-02 10:44:03 +01:00
5d0df8d880
Change format of line file/line numbers
2008-08-02 10:42:00 +01:00
bb80b432e6
Add comments file/line number comments
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Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
9f6f711f8d
Remove unused variable
2008-07-29 21:08:50 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
39717989a8
Call set_active_entity in the right places
2008-07-29 13:04:29 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
d343db34fd
Fix initialisation order
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Initial processes set a magic flag in the code generator
which allows it to push constant assignments into the
VHDL signal initialisation and omit the assignment.
However, it should only do this if the signal has not
already been read (otherwise the previous read would
not get the undefined value as expected)
2008-07-16 12:00:11 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
899a70908e
Fix small bug with initialisation and ammend comments
2008-06-24 20:13:18 +01:00
db992e808f
Start using vhdl_procedural instead of vhdl_process
2008-06-24 19:54:22 +01:00
75631bd8f1
Move is_inital code out of vhdl_process into vhdl_scope
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Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
f81129aa68
Fix some bugs with blocking assignment
2008-06-23 13:36:28 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
c926454a41
Statements might be emitted in wrong order
2008-06-21 16:33:05 +01:00
be12f56856
Document blocking assignment behaviour
2008-06-18 14:04:16 +01:00
e0f41198d6
Blocking assignment working correctly
2008-06-18 13:49:03 +01:00
fb31a88c51
Blocking assignment nearly working
2008-06-18 13:30:19 +01:00
254ccb9ccb
First passing at blocking assignment
2008-06-18 13:06:27 +01:00
d2bebee9d9
Refactor before adding blocking assignment
2008-06-18 12:51:11 +01:00
9fbb449e06
Optimise away empty (VHDL) processes
2008-06-13 14:17:24 +01:00
0a8fd50c4a
Find assignments that could be initializers
2008-06-13 13:59:48 +01:00
a7cfdc3a87
Add VHDL if statement to AST types
2008-06-11 14:11:37 +01:00
d762253f74
Wait statements
2008-06-09 12:40:59 +01:00
c3ac1aac8c
Remove debugging messages from output
2008-06-04 21:07:50 +01:00
6e448da90d
Emit Write() calls for parameters of $display
2008-06-04 15:19:44 +01:00
4bf2e1669d
Store packages required with entity rather than globally
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Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
4211e651d0
Stub file for processing statements
2008-06-03 18:26:36 +01:00
a09b4e3b92
Initial process have wait at the end
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(do it properly this time rather than a hack :-)
2008-06-03 17:39:24 +01:00
ab6ae621cb
Remove useless comments in output
2008-06-02 20:24:25 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
7c9d154461
Forgot source files for entity generation
2008-05-31 15:31:48 +01:00
Nick Gasson