Commit Graph

4117 Commits

Author SHA1 Message Date
Cary R d43cda3def Add port checks for primitives.
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
2007-09-06 18:50:02 -07:00
Cary R 7c852aa075 Add cmos/rcmos primitives.
This patch adds the cmos and rcmos primitives.
2007-09-06 18:46:22 -07:00
Stephen Williams 203cb0f730 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-09-04 16:42:45 -07:00
Cary R b55e3c11dc mingw needs fseeko/ftello redefinitions in lxt_write.h
These redefinitions were in lxt2_write.h, but missing in lxt_write.h.
This patch adds them to lxt_write.h.
2007-09-04 16:32:52 -07:00
Stephen Williams 7290489e1a Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2007-09-04 16:24:19 -07:00
Cary R 7bf4b64c0a Check that logic gates are not given null ports.
Logic gates do not handle null ports so check for this and
issue an error message when it happens.
2007-09-04 16:13:46 -07:00
Stephen Williams 083b9b6ee6 Handle repeat concatenation in continuous assign
When a repeat concatenation expression is translated to a netlist,
get the repeat expression right. This comes up when an elab_and_eval
elaboration contains a repeat concationation, and the expression is
ultimately turned into a netlist by expr_synth.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-01 17:36:57 -07:00
Martin Whitaker 963b26283a Generate scopes are more like begin-end scopes
Apparently making generate scopes look like module instances
confuses some 3rd party tools that see this information in the
VCD dump.
2007-09-01 15:06:53 -07:00
Martin Whitaker 59af5d08b7 More portable encoding of vectors
Slight modification to the description of a vector vareable in the
declarations section for the convenience of 3rd party VCD viewers.
2007-09-01 15:00:53 -07:00
Stephen Williams 4af28c7526 Signed divide of 32bit values
Signed divide of 32bit values can overflow if done in a 32bit long
due to the truncation of sign bits. So use the large value algorithm
if the values are >= 31 bits (63 bits on 64bit machines).

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-01 14:38:57 -07:00
Cary R 4f6b47b345 Check that functions do not call invalid statements.
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
2007-08-30 20:41:45 -07:00
Cary R 3f6ea1d587 Make C style comments work in false/suppressed ifdef/etc. blocks.
C style comments were not recognized as comments in false or
suppressed sections of ifdef/etc. blocks. This prohibited an
unneeded endif/else/etc. from being commented out with this
style of comment.
2007-08-30 19:01:10 -07:00
Cary R 347ba8bc29 Comment out routines that pr1779647 made obsolete.
I decided not to delete these since we may at some point in time want
this functionality back. For now they are commented out with an
explanation so we know what is going on.
2007-08-30 19:00:07 -07:00
Cary R c7538386fc Start of simulation event needed to be run after initialization events.
This patch splits the end of compile and the start of simulation call
backs code into two different procedures. The end of compile events are
still executed at the same time they alway were. The start of simulation
events are now run after initialization.
2007-08-29 20:20:03 -07:00
Cary R fa1c0ae2a2 $finish() now stops at the end of the time step not immediately.
The event loop used to check for $finish at every iteration. This patch
alters this behavior to only check just before you advance to the next
time step. This allows events for the current time step to complete.
2007-08-29 20:07:55 -07:00
Cary R 81a45cdc5f Make vpi_put_value to a real accept an integer value and add diagnostic code.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
2007-08-29 20:02:12 -07:00
Cary R 23ce6c39ab Make vpi_put_value to a real accept an integer value and add diagnostic code.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
2007-08-29 19:50:07 -07:00
Cary R 3fda7e323a Relax the requirement on list of port declarations for implicit ports.
Previously list of port declarations were considered a complete
definition of the port. This caused problems for some, so this patch
allows implicitly defined ports (no wire/reg/etc.) to have net
declarations in the body.
2007-08-29 18:38:36 -07:00
Cary R 35df445db1 Initialize all range variables in the constructor to avoid false asserts.
This would have never been a problem with the actual circuit generated.
The problem was that the assert was checking values that had never been
set. The constructor now explicitly sets these values to zero and while
I was at it I added a couple more asserts.
2007-08-29 18:12:29 -07:00
Cary R b69c4c9a2c Fix range handling/checking and add a flag to allow deprecated port syntax.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.

When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).

The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
2007-08-29 18:10:18 -07:00
Cary R d08817aec1 [PATCH] Search for include files relative to the current files path first.
This patch add the current files path to the start of the list used
when search for include files.
2007-08-29 17:45:55 -07:00
Cary R ca924639a8 [PATCH] Better error message when an endmodule is missing (nested modules).
This patch adds better checking for a missing endmodule or an attempt
to nest modules. A more descriptive message is printed and the location
of the original module definition is printed.
2007-08-28 17:49:34 -07:00
Stephen Williams 76b7346ee0 forgot to check it initialization calls
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-28 17:32:04 -07:00
Stephen Williams bef55d4426 Nets initialize with z value.
At time zero, nets (not variables) need to be initialized with z
instead of x.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-28 16:56:01 -07:00
Stephen Williams 11ec505697 Logic gates can take part select inputs
It is possible for the compiler to generate logic gates that have
inputs from part select nodes. This implements the part select
input methods.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-28 16:52:44 -07:00
Cary R 86e6817505 Fix missing warning when port is unsized.
This patch fixes an incorrect optimization that was skipping a
call to set the port width when there was no width (a scalar).
The problem with this is that since a (0,0) pair was not added
to the list, later when the width was define to (1,0) the checking
code did not have the (0,0) to tell that there was a mismatch in
the port size. Section 12.3.3 States that the two sizes shall be
identical, so yes this is an error even though it is very minor.
2007-08-17 11:48:47 -07:00
Cary R 15058a31b9 vpiFullName for real variables will now return the correct value.
This patch makes vpiFullName for real variables return the correct
value. A Scope reference was added to the base structure along with
the relevant code to support generating the full name. A couple of
memory leaks were plugged and some formatting fixed as well.
2007-08-17 11:40:01 -07:00
Cary R 6653202e91 Enhance vpi_handle_by_name to accept either a scope or a module.
It appears that other simulators allow the second argument to
vpi_handle_by_name to be either a scope or a module. Allowing
a module in addition to a scope significantly increases the
usability of this function.
2007-08-16 14:36:06 -07:00
Cary R 951f9f2bbf Add vpiType to the vpi_get_str() function.
vpi_get_str() can now return a reasonable value for most of the
types used in vvp. I'm not certain I got all of them, but they
are easy to add if any are missing. I also fixed a couple of
typos that I found while looking for all the different types.
2007-08-16 10:48:28 -07:00
Stephen Williams 30273a1172 Real value constants have width 1
Real value constants have width 1 in Icarus Verilog. This is not
the same as the output from $bitstoreal, which is *not* a real
valued expression but a logic vector that losslessly carries the
real value.

Also remove unused CVS markings.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-15 22:01:59 -07:00
Cary R c71b9797ca Make %t with real values use specified width if given.
The %t format did not use the width specified when displaying
real values. It should now work the same as the integer version.
2007-08-15 13:39:28 -07:00
Cary R dd6a441312 [PATCH] Fixed the display of real values with the %t format.
Add a calculation to compute the required width for real values
when displayed with the %t formet.
2007-08-15 13:31:29 -07:00
Cary R 06c15862e8 Add the vpiFullName property to binary and string parameters.
This patch adds the missing vpiFullName property to binary and
string parameters (FYI real parameters are not currently supported
by the VPI interface).
2007-08-15 10:06:41 -07:00
Cary R 35e19ccbd3 Add a cast to remove a warning.
This patch adds a cast to get around the warning produced when the tf
size call back (int *) is placed into the vpi structure (PLI_INT32 *).
2007-08-15 10:04:50 -07:00
Cary R 239523b3c7 Implement the swrite* and sformat system tasks plus a few other fixes.
This patch implements the swrite* and sformat system tasks. It also
makes $simtime distinguishable from the other integer time tasks.
This was needed to get the correct time units when $simtime was given
as an argument to $swrite*. The string constant code was also modified
to allow a string to be returned as a vector (0/1 bit pattern).

Here are some more specifics about the swrite* changes.
1. They do not share formatting code with the other display functions,
   so they may/will produce different results.
2. All %{alpha} codes allow a width and justification. Others have been
   enhanced (%t allows the default width and precision to be overridden,
   time functions print with time formatting, better error checking and
   messages, etc.).
3. %u and %z formatting codes have been added. It is important to note
   that these two formats can produce embedded NULLs, since these
   functions are returning a string anything after the first NULL will
   not be reachable! memcpy is used instead of regular string processing
   where needed so that the original string will contain the total
   result. The size returned when the string is created is the true
   length.  A warning will be printed if a string with embedded NULLs is
   produced (strlen() does not match the true length).
4. Real numbers are printed with %g instead of %f.

Once this new formatting code has been evaluated we should incorporate
the changes/fixes into the formatting code for the other functions or
the other functions could be modified to use this new code. The true
string length is available so we should be able to work around the
embedded NULL problem.
2007-08-13 20:07:12 -07:00
Stephen Williams 268e2df011 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-08-13 19:58:56 -07:00
Cary R 632685d830 Check that $timeformat is not given more than four arguments.
Add a check that $timeformat is not given more than four arguments.
2007-08-13 19:52:38 -07:00
Stephen Williams 9b807c78d3 Prepare for 20070812 snapshot 2007-08-12 20:27:38 -07:00
Stephen Williams 1942899a3f Fix return of net strength value.
The calculated return value for the calculated strength value of
a net was left dangling. This patch fixes that. See pr1770199 in
the regression test suite.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-10 21:51:13 -07:00
Stephen Williams 5e385e901d Fix missing endif 2007-08-10 10:14:00 -07:00
Stephen Williams 3b94c122b7 Constant concat operands are self determined
distinguish between self-determined and value-preserving when
evaluating constants that are arguments to concatenations.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-09 22:08:54 -07:00
Stephen Williams f46be09914 Initialize assignments of reals
Support initialization assignments of real value variables. In the
process, clean up the processing of real variable declarations in
the parser.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-04 21:50:06 -07:00
Cary R 1aa4394d75 Check the random function seed type and a fix to handle time variables.
The standard states that the seed for the random functions should be
an integer/time variable or a register. This patch fixes the compiletf
routines to check for this. There is also a small patch to
vvp/vpi_signal.cc that removes an assert that was failing and replaces
it with appropriate code. The assert was verifying that the source was
not bigger than an integer. The problem with this is that a time
variable or register may be bigger than an integer. I altered the code
to remove the assert and copy only the lower (8 * sizeof integer) bits.
The potential overflow/loss of precision is not checked. This passes
the regression tests.
2007-07-25 21:36:06 -07:00
Stephen Williams 8dc23dad59 Delay compiletf until bindings are complete
Delat the compiletf calls until after all the label references
are resolved and link bindings are complete. Otherwise, there may
be dangling references.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-07-24 18:24:24 -07:00
Cary R b23eb1b917 [PATCH] Add compiletf routine for deposit system task and fix string constants.
This patch adds a compiletf routine to the $deposit system task and
simplifies the calltf routine. It also patches the constant string code
to return an appropriate integer value when needed. A number of compiletf
routines that check for this can now be simplified since this (string
constants) no longer causes an assert in an integer environment.
2007-07-23 21:23:55 -07:00
Stephen Williams 824f29a7d2 Better errors for invalid scope path
Better handle cases where the scope part of a heirarchical name does
not match any existing scope, or where scope index expressions are
not correct.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-07-22 21:55:35 -07:00
Stephen Williams a6bd1ff3ce Vector parts into reduction nets
In rare cases, the reduction logic nodes may get vector part inputs.
This patch adds support for vector parts entering a reduction node.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-07-22 21:52:28 -07:00
Stephen Williams fa05344738 Parameter names in generate blocks from containing scopes.
Parameter names used in generate blocks can look in containing
scopes (but not past the containing module) for their definitions.
2007-07-21 17:47:37 -07:00
Martin Whitaker 42fe46a7db Elaborate memory references with non-zero bases.
This fixes r-value type references to memory words for memories
that have a non-zero base address. Elaborate the expression
needed to get the canonical word index.
2007-07-21 17:19:24 -07:00
Stephen Williams 3d51810f01 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-07-20 19:35:22 -07:00