af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
338240c37b
Give anonymous modules a name when elaborated.
1998-11-21 19:19:44 +00:00
ac71df5257
Add -f flags for generic flag key/values.
1998-11-18 04:25:22 +00:00
4661006e4b
Add the sigfold function that unlinks excess
...
signal nodes, and add the XNF target.
1998-11-16 05:03:52 +00:00
3d6d334f80
Introduce netlist optimizations with the
...
cprop function to do constant propogation.
1998-11-13 06:23:17 +00:00
6b2fa19429
Handle while loops.
1998-11-11 03:13:04 +00:00
d27f260bc1
Check net ranges in declarations.
1998-11-11 00:01:51 +00:00
7859de1e4e
Add support it vvm target for level-sensitive
...
triggers (i.e. the Verilog wait).
Fix display of $time is format strings.
1998-11-10 00:48:31 +00:00
8705aa94c6
Add vvm library.
1998-11-09 23:44:10 +00:00
d189165ae9
Oops, forgot return from operator<<
1998-11-09 19:03:26 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
9a93912ce7
Ignore generated dep directory.
1998-11-09 18:50:16 +00:00
47a444fb92
Calculate expression widths at elaboration time.
1998-11-07 19:17:10 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
5836c8aa4b
Properly dump 0 length numbers.
1998-11-07 17:04:48 +00:00
43c20f33c8
Make sure dep is a directory.
1998-11-07 17:01:36 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve