8f519531f3
Optimize load-add with load/add instruction
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Where and expression is an immediate value added to a signal value,
it is possible to optimize them to a single instruction that combines
the load with an add at the same time.
2007-12-04 19:15:15 -08:00
68a9526fec
Minor performance tweak of vector_to_array function.
2007-12-02 19:00:12 -08:00
e5381feb85
Clean up functor counters
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The functor counters were left over from the v0.8 release. Rework
the counters to be relevent to the current state of vvp.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-12-02 08:47:06 -08:00
7e59186f1e
Fixes for wide division/modulus.
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Wide division/modulus (more bits than unsigned long) gave incorrect
results when both the divisor and dividend where the same. They also
did not produce an error message when dividing by zero.
2007-11-05 20:24:33 -08:00
d186f2da04
Ambiguous resolution needs to preserve the MSB for StL/etc. signals.
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The MSB was not being preserved for L strength signals. This caused
undefined signals (x) to become defined (0).
2007-09-24 17:20:01 -07:00
bcc034f634
Compile time warnings
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Fix compile time warnings detected by gccc 4.2.
2007-09-20 17:20:48 -07:00
81a45cdc5f
Make vpi_put_value to a real accept an integer value and add diagnostic code.
...
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
2007-08-29 20:02:12 -07:00
bef55d4426
Nets initialize with z value.
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At time zero, nets (not variables) need to be initialized with z
instead of x.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-28 16:56:01 -07:00
a6bd1ff3ce
Vector parts into reduction nets
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In rare cases, the reduction logic nodes may get vector part inputs.
This patch adds support for vector parts entering a reduction node.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-07-22 21:52:28 -07:00
b327b86e4a
Propagate real values properly
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Be careful to include bitwise differences in double values, because
it is the bit pattern we are passing aroung, not the arithmetic value.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-07-13 18:42:35 -07:00
ae82eccdc4
handle constant inf values.
2007-06-12 02:36:58 +00:00
089bdefad1
Fix div/mod calculation that caused a hang for some divisions.
2007-04-15 02:07:24 +00:00
611d2c81b3
Spelling fixes from Larry
2007-03-22 16:08:14 +00:00
74ac5dbf58
Cast to remove ambiguities calling pow function.
2007-03-07 03:55:42 +00:00
ae88f5cc68
Lint fixes.
2007-03-07 00:38:15 +00:00
fc9a90c9e0
Add support for edge sensitive spec paths.
2007-03-02 06:13:22 +00:00
d958a4a5af
Handle relink of continuous assignment.
2007-02-05 01:08:10 +00:00
0ae45e5644
Fix build error overloading pow function.
2006-12-10 17:15:48 +00:00
316422d93b
Handle vpiRealVal reads of signals, and real anyedge events.
2006-12-09 19:06:53 +00:00
2ac30824ac
Fix spurious event from net8 that is forced.
2006-11-22 06:10:05 +00:00
5348ac14a5
Delay object supports real valued delays.
2006-07-08 21:48:00 +00:00
80f30be9d0
Add support for system functions in continuous assignments.
2006-06-18 04:15:50 +00:00
dabdcf0fc9
const/non-const clash.
2006-03-15 19:15:34 +00:00
6f46d12e07
Add support for logic parameters.
2006-03-08 05:29:42 +00:00
e1ce72e245
Support wide divide nodes.
2006-01-03 06:19:31 +00:00
2b8fd28a95
Force instruction that can be indexed.
2005-11-26 17:16:05 +00:00
35951510c5
Put vec8 and vec4 nets into seperate net classes.
2005-11-25 17:55:26 +00:00
bebcc05aab
Handle very wide % and / operations using expanded vector2 support.
2005-11-10 13:27:16 +00:00
2842a65fd1
Make sure the new size sticks in resize method.
2005-10-04 04:41:07 +00:00
3ff2488d4f
Clean up a few overflowed shifts.
2005-08-30 00:49:42 +00:00
70f146924a
Safe handling of C left shift.
2005-08-29 04:46:52 +00:00
73453996a9
Be more cautios about accessing out-of-range bits.
2005-08-27 03:28:16 +00:00
bc489a7761
Bring threads into the vvp_vector4_t structure.
2005-08-27 02:34:42 +00:00
3ac79c294a
Implement real valued signals and arith nodes.
2005-07-06 04:29:25 +00:00
60b9121c6c
Make vector2 multiply more portable.
2005-06-27 21:13:14 +00:00
de1dd2f2b3
Make bit masks of vector4_t 64bit aware.
2005-06-26 01:57:22 +00:00
6c8e1f7834
inline the vvp_send_vec4_pv function.
2005-06-24 02:16:42 +00:00
b58705b829
Inline more simple stuff, and more vector4_t by const reference for performance.
2005-06-22 18:30:12 +00:00
7091915b73
Reduce vvp_vector4 copies by using const references.
2005-06-22 00:04:48 +00:00
5513974b78
Optimize vvp_scalar_t handling, and fun_buf Z handling.
2005-06-21 22:48:23 +00:00
ad78af2f91
Inline some commonly called vvp_vector4_t methods.
2005-06-20 01:28:14 +00:00
1b30bac9f3
Optimize the LOAD_VEC implementation.
2005-06-19 18:42:00 +00:00
466ab5c2c7
Resolv do not propogate inputs that do not change.
2005-06-15 00:47:15 +00:00
80cac983c6
More unified vec4 to hex string functions.
2005-06-13 00:54:04 +00:00
668781788b
Support resistive mos devices.
2005-06-12 15:13:37 +00:00
42433f4df9
Add support for notif0/1 gates.
...
Make delay nodes support inertial delay.
Add the %force/link instruction.
2005-06-02 16:02:11 +00:00
3a8e2e688d
Clean up definition of vvp_vector4_t insertion into ostream.
2005-05-17 20:54:56 +00:00
f6da64e2ec
ostream insert for vvp_vector4_t objects.
2005-05-07 03:14:50 +00:00
99aff5f10b
Remove dead functor code.
2005-04-28 04:59:53 +00:00
e9bf021f6c
vvp_fun_signal eliminates duplicate propagations.
2005-04-25 04:42:17 +00:00
a3f696cd06
Add vvp driver functor for logic outputs,
...
Add ostream output operators for debugging.
2005-04-13 06:34:20 +00:00
061fdf5a0d
scalars with 0-drivers are hiZ by definition.
2005-04-09 06:00:58 +00:00
fe91ebe77c
Default behavior for recv_vec8 methods.
2005-04-09 05:30:38 +00:00
573e07225d
Rework the vvp_delay_t class.
2005-04-03 05:45:51 +00:00
b7ef2fcb0a
Reimplement combinational UDPs.
2005-04-01 06:02:45 +00:00
53da6e9a33
Add support for LPM_UFUNC user defined functions.
2005-03-18 02:56:03 +00:00
313502f360
Implement VPI access to signal strengths,
...
Fix resolution of ambiguous drive pairs,
Fix spelling of scalar.
2005-03-12 04:27:42 +00:00
c5e7e2ec0a
Signals may receive part vectors from %set/x0
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instructions. Re-implement the %set/x0 to do
just that. Remove the useless %set/x0/x instruction.
2005-02-14 01:50:23 +00:00
355ead0002
Add debug dumps for vectors, and fix vvp_scaler_t make from BIT4_X values.
2005-02-12 06:13:22 +00:00
a0583ef124
Simplify vvp_scaler strength representation.
2005-02-10 04:54:41 +00:00
ca1bbc79a3
Add .repeat functor and BIFIF functors.
2005-02-07 22:42:42 +00:00
b48abb2148
Add wide .arith/mult, and vvp_vector2_t vectors.
2005-02-04 05:13:02 +00:00
018014368b
Add support for reduction logic gates.
2005-02-03 04:55:13 +00:00
84b3e8e2dc
Get .arith/sub working.
2005-01-30 05:06:49 +00:00
d51503ffd8
move AND to buitin instead of table.
2005-01-29 17:52:06 +00:00
a121e703f3
Add vector4 implementation of .arith/mult.
2005-01-28 05:34:25 +00:00
6a23f16860
.cmp/x supports signed magnitude compare.
2005-01-22 17:36:15 +00:00
1d1dda5a5d
Implement the %load/x instruction.
2005-01-22 00:58:22 +00:00
1c3668ea7f
Reimplement comparators as vvp_vector4_t nodes.
2005-01-16 04:19:08 +00:00
9735b0e8b3
Add the .part/pv node and related functionality.
2005-01-09 20:11:15 +00:00
d5c33420ab
vvp_fun_signal propagates vvp_vector8_t vectors when appropriate.
2005-01-01 02:12:34 +00:00
34a14b983b
Implement .resolv functors, and stub signals recv_vec8 method.
2004-12-31 06:00:06 +00:00
36f36bd2ac
Add basic force/release capabilities.
2004-12-15 17:16:08 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
...
of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
Stephen Williams
Cary R
Larry Doolittle
steve