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iverilog/tgt-vvp/eval_expr.c

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Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
/*
Rework ivl_file_table_* interface and fix most vvp/examples. Rework the ivl_file_table_* interface to be more generic and easier to use. Also all the vvp examples except for memory.vvp have been fixed to run correctly with the current vvp. Someone with a bit more experience will need to fix memory.vvp.
2008-01-02 19:42:23 +01:00
* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vvp_priv.h"
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
# include <string.h>
Make configure detect malloc.h
2001-09-15 20:27:04 +02:00
#ifdef HAVE_MALLOC_H
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
# include <malloc.h>
Make configure detect malloc.h
2001-09-15 20:27:04 +02:00
#endif
# include <stdlib.h>
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
# include <assert.h>
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
static void draw_eval_expr_dest(ivl_expr_t exp, struct vector_info dest,
int ok_flags);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
static void draw_signal_dest(ivl_expr_t exp, struct vector_info res,
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
int add_index, long immediate);
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
int number_is_unknown(ivl_expr_t ex)
{
const char*bits;
unsigned idx;
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
if (ivl_expr_type(ex) == IVL_EX_ULONG)
return 0;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
assert(ivl_expr_type(ex) == IVL_EX_NUMBER);
bits = ivl_expr_bits(ex);
for (idx = 0 ; idx < ivl_expr_width(ex) ; idx += 1)
if ((bits[idx] != '0') && (bits[idx] != '1'))
return 1;
return 0;
}
/*
* This function returns TRUE if the number can be represented in a
* 16bit immediate value. This amounts to looking for non-zero bits
* above bitX. The maximum size of the immediate may vary, so use
* lim_wid at the width limit to use.
*/
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
int number_is_immediate(ivl_expr_t ex, unsigned lim_wid, int negative_ok_flag)
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
{
const char*bits;
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
unsigned nbits = ivl_expr_width(ex);
char pad_bit = '0';
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
unsigned idx;
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
if (ivl_expr_type(ex) != IVL_EX_NUMBER
&& ivl_expr_type(ex) != IVL_EX_ULONG)
return 0;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
bits = ivl_expr_bits(ex);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (ivl_expr_signed(ex) && bits[nbits-1]=='1')
pad_bit = '1';
if (pad_bit == '1' && !negative_ok_flag)
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
return 0;
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
for (idx = lim_wid ; idx < nbits ; idx += 1)
if (bits[idx] != pad_bit)
return 0;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
return 1;
}
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
long get_number_immediate(ivl_expr_t ex)
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
{
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
long imm = 0;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
unsigned idx;
switch (ivl_expr_type(ex)) {
case IVL_EX_ULONG:
imm = ivl_expr_uvalue(ex);
break;
case IVL_EX_NUMBER: {
const char*bits = ivl_expr_bits(ex);
unsigned nbits = ivl_expr_width(ex);
for (idx = 0 ; idx < nbits ; idx += 1) switch (bits[idx]){
case '0':
break;
case '1':
Check range of immediate value.
2008-05-29 23:00:32 +02:00
assert(idx < 8*sizeof(imm));
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
imm |= 1L << idx;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
break;
default:
assert(0);
}
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
if (ivl_expr_signed(ex) && bits[nbits-1]=='1' && nbits < 8*sizeof(imm))
imm |= -1L << nbits;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
break;
}
default:
assert(0);
}
return imm;
}
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
static void eval_logic_into_integer(ivl_expr_t expr, unsigned ix)
{
switch (ivl_expr_type(expr)) {
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
case IVL_EX_NUMBER:
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
case IVL_EX_ULONG:
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
{
long imm = get_number_immediate(expr);
if (imm >= 0) {
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%ix/load %u, %ld;\n", ix, imm);
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
} else {
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%ix/load %u, 0; loading %ld\n", ix, imm);
fprintf(vvp_out, " %%ix/sub %u, %ld;\n", ix, -imm);
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
}
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
/* This can not have have a X/Z value so clear bit 4. */
fprintf(vvp_out, " %%mov 4, 0, 1;\n");
Allow canonical part select of net vectors to be larger then the vector The part select of a vector is converted by the compiler during elaboration to a 0-based canonical address. But since it is legal to address bits below the LSB, the canonical address can be negative. So make the part select base for selecting from signals work with signed arithmetic and make the code generator generate negative indices when needed.
2008-06-13 06:41:11 +02:00
}
break;
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
case IVL_EX_SIGNAL: {
ivl_signal_t sig = ivl_expr_signal(expr);
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
unsigned word = 0;
Use ivl_signal_dimensions to detect that signal is an array. It is possible for an array to have 1 word in it, so using the array count to detect an array is incorrect. Use the ivl_signal_dimensions function, which is there exactly for that purpose.
2008-05-19 20:31:40 +02:00
if (ivl_signal_dimensions(sig) > 0) {
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
/* Detect the special case that this is a
variable array. In this case, the ix/getv
will not work, so do it the hard way. */
if (ivl_signal_type(sig) == IVL_SIT_REG) {
struct vector_info rv;
rv = draw_eval_expr(expr, 0);
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%ix/get %u, %u, %u;\n",
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
ix, rv.base, rv.wid);
clr_vector(rv);
break;
}
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
ivl_expr_t ixe = ivl_expr_oper1(expr);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(ixe, 8*sizeof(unsigned long), 0))
Evaluate non-immediate signal selection. This patch adds code to treat non-immediate signal selection the same as the default logic evaluation
2008-01-15 00:57:01 +01:00
word = get_number_immediate(ixe);
else {
struct vector_info rv;
rv = draw_eval_expr(expr, 0);
fprintf(vvp_out, " %%ix/get %u, %u, %u;\n",
ix, rv.base, rv.wid);
clr_vector(rv);
break;
}
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
}
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
char*type = ivl_signal_signed(sig) ? "/s" : "";
fprintf(vvp_out, " %%ix/getv%s %u, v%p_%u;\n", type, ix,
sig, word);
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
break;
}
default: {
struct vector_info rv;
rv = draw_eval_expr(expr, 0);
Evaluate non-immediate signal selection. This patch adds code to treat non-immediate signal selection the same as the default logic evaluation
2008-01-15 00:57:01 +01:00
fprintf(vvp_out, " %%ix/get %u, %u, %u;\n",
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
ix, rv.base, rv.wid);
clr_vector(rv);
break;
}
}
}
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
/*
* This function, in addition to setting the value into index 0, sets
* bit 4 to 1 if the value is unknown.
*/
void draw_eval_expr_into_integer(ivl_expr_t expr, unsigned ix)
{
int word;
switch (ivl_expr_value(expr)) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
eval_logic_into_integer(expr, ix);
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
break;
case IVL_VT_REAL:
word = draw_eval_real(expr);
clr_word(word);
fprintf(vvp_out, " %%cvt/ir %u, %u;\n", ix, word);
break;
default:
fprintf(stderr, "XXXX ivl_expr_value == %d\n",
ivl_expr_value(expr));
assert(0);
}
}
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
/*
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
* The STUFF_OK_XZ bit is true if the output is going to be further
Spelling fixes (larry doolittle)
2007-02-26 20:49:48 +01:00
* processed so that x and z values are equivalent. This may allow for
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
* new optimizations.
*/
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
static struct vector_info draw_eq_immediate(ivl_expr_t exp, unsigned ewid,
ivl_expr_t le,
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
ivl_expr_t re,
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
int stuff_ok_flag)
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
{
unsigned wid;
struct vector_info lv;
unsigned long imm = get_number_immediate(re);
wid = ivl_expr_width(le);
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr_wid(le, wid, stuff_ok_flag);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
switch (ivl_expr_opcode(exp)) {
case 'E': /* === */
fprintf(vvp_out, " %%cmpi/u %u, %lu, %u;\n",
lv.base, imm, wid);
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if (lv.base >= 8)
clr_vector(lv);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
lv.base = 6;
lv.wid = 1;
break;
case 'e': /* == */
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
/* If this is a single bit being compared to 1, and the
output doesn't care about x vs z, then just return
the value itself. */
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if ((stuff_ok_flag&STUFF_OK_XZ) && (lv.wid == 1) && (imm == 1))
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
break;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
fprintf(vvp_out, " %%cmpi/u %u, %lu, %u;\n",
lv.base, imm, wid);
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if (lv.base >= 8)
clr_vector(lv);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
lv.base = 4;
lv.wid = 1;
break;
case 'N': /* !== */
fprintf(vvp_out, " %%cmpi/u %u, %lu, %u;\n",
lv.base, imm, wid);
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if (lv.base >= 8)
clr_vector(lv);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
lv.base = 6;
lv.wid = 1;
fprintf(vvp_out, " %%inv 6, 1;\n");
break;
case 'n': /* != */
single bit optimization for != in expressions, and expand ++ and != results if needed.
2002-09-13 06:09:51 +02:00
/* If this is a single bit being compared to 0, and the
output doesn't care about x vs z, then just return
the value itself. */
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if ((stuff_ok_flag&STUFF_OK_XZ) && (lv.wid == 1) && (imm == 0))
single bit optimization for != in expressions, and expand ++ and != results if needed.
2002-09-13 06:09:51 +02:00
break;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
fprintf(vvp_out, " %%cmpi/u %u, %lu, %u;\n",
lv.base, imm, wid);
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if (lv.base >= 8)
clr_vector(lv);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
lv.base = 4;
lv.wid = 1;
fprintf(vvp_out, " %%inv 4, 1;\n");
break;
default:
assert(0);
}
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
/* In the special case that 47 bits are ok, and this really is
a single bit value, then we are done. */
if ((lv.wid == 1) && (ewid == 1) && (stuff_ok_flag&STUFF_OK_47))
return lv;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
/* Move the result out out the 4-7 bit that the compare
uses. This is because that bit may be clobbered by other
expressions. */
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
if (lv.base < 8) {
Remove short int restrictions from vvp opcodes.
2003-06-17 21:17:42 +02:00
unsigned base = allocate_vector(ewid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of equality compare.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
fprintf(vvp_out, " %%mov %u, %u, 1;\n", base, lv.base);
lv.base = base;
lv.wid = ewid;
if (ewid > 1)
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base+1, ewid-1);
single bit optimization for != in expressions, and expand ++ and != results if needed.
2002-09-13 06:09:51 +02:00
} else if (lv.wid < ewid) {
Remove short int restrictions from vvp opcodes.
2003-06-17 21:17:42 +02:00
unsigned base = allocate_vector(ewid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of equality compare.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
if (lv.base >= 8)
clr_vector(lv);
single bit optimization for != in expressions, and expand ++ and != results if needed.
2002-09-13 06:09:51 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n", base,
lv.base, lv.wid);
fprintf(vvp_out, " %%mov %u, 0, %u;\n",
base+lv.wid, ewid-lv.wid);
lv.base = base;
lv.wid = ewid;
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
}
return lv;
}
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
/*
* This handles the special case that the operands of the comparison
* are real valued expressions.
*/
static struct vector_info draw_binary_expr_eq_real(ivl_expr_t exp)
{
struct vector_info res;
int lword, rword;
res.base = allocate_vector(1);
res.wid = 1;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
lword = draw_eval_real(ivl_expr_oper1(exp));
rword = draw_eval_real(ivl_expr_oper2(exp));
clr_word(lword);
clr_word(rword);
fprintf(vvp_out, " %%cmp/wr %d, %d;\n", lword, rword);
switch (ivl_expr_opcode(exp)) {
case 'e':
fprintf(vvp_out, " %%mov %u, 4, 1;\n", res.base);
break;
case 'n': /* != */
fprintf(vvp_out, " %%mov %u, 4, 1;\n", res.base);
fprintf(vvp_out, " %%inv %u, 1;\n", res.base);
break;
default:
assert(0);
}
return res;
}
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
static struct vector_info draw_binary_expr_eq(ivl_expr_t exp,
unsigned ewid,
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
int stuff_ok_flag)
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
{
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
unsigned wid;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
struct vector_info lv;
struct vector_info rv;
Watch out for real compared to constant. Handle as real.
2004-06-30 05:07:32 +02:00
if ((ivl_expr_value(le) == IVL_VT_REAL)
||(ivl_expr_value(re) == IVL_VT_REAL)) {
return draw_binary_expr_eq_real(exp);
}
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(re,16,0) && !number_is_unknown(re))
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
return draw_eq_immediate(exp, ewid, le, re, stuff_ok_flag);
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
Support bool expressions and compares handle them optimally.
2005-09-14 04:53:13 +02:00
assert(ivl_expr_value(le) == IVL_VT_LOGIC
|| ivl_expr_value(le) == IVL_VT_BOOL);
assert(ivl_expr_value(re) == IVL_VT_LOGIC
|| ivl_expr_value(re) == IVL_VT_BOOL);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
Generate %cmpi/u where appropriate.
2002-06-02 20:57:17 +02:00
wid = ivl_expr_width(le);
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
if (ivl_expr_width(re) > wid)
wid = ivl_expr_width(re);
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
lv = draw_eval_expr_wid(le, wid, stuff_ok_flag&~STUFF_OK_47);
rv = draw_eval_expr_wid(re, wid, stuff_ok_flag&~STUFF_OK_47);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
switch (ivl_expr_opcode(exp)) {
Evaluate === and !==
2001-03-27 08:43:27 +02:00
case 'E': /* === */
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/u %u, %u, %u;\n", lv.base,
rv.base, lv.wid);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
if (lv.base >= 8)
clr_vector(lv);
if (rv.base >= 8)
clr_vector(rv);
Evaluate === and !==
2001-03-27 08:43:27 +02:00
lv.base = 6;
lv.wid = 1;
break;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
case 'e': /* == */
Fix the size of unsized constant operants to compare (PR#274)
2001-09-29 03:53:22 +02:00
if (lv.wid != rv.wid) {
fprintf(stderr,"internal error: operands of == "
" have different widths: %u vs %u\n",
lv.wid, rv.wid);
}
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/u %u, %u, %u;\n", lv.base,
rv.base, lv.wid);
clr_vector(lv);
clr_vector(rv);
lv.base = 4;
lv.wid = 1;
break;
Evaluate === and !==
2001-03-27 08:43:27 +02:00
case 'N': /* !== */
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
if (lv.wid != rv.wid) {
fprintf(stderr,"internal error: operands of !== "
" have different widths: %u vs %u\n",
lv.wid, rv.wid);
}
Evaluate === and !==
2001-03-27 08:43:27 +02:00
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/u %u, %u, %u;\n", lv.base,
rv.base, lv.wid);
fprintf(vvp_out, " %%inv 6, 1;\n");
clr_vector(lv);
clr_vector(rv);
lv.base = 6;
lv.wid = 1;
break;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
case 'n': /* != */
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
if (lv.wid != rv.wid) {
fprintf(stderr,"internal error: operands of != "
" have different widths: %u vs %u\n",
lv.wid, rv.wid);
}
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/u %u, %u, %u;\n", lv.base,
rv.base, lv.wid);
fprintf(vvp_out, " %%inv 4, 1;\n");
clr_vector(lv);
clr_vector(rv);
lv.base = 4;
lv.wid = 1;
break;
default:
assert(0);
}
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if ((stuff_ok_flag&STUFF_OK_47) && (wid == 1)) {
return lv;
}
Comparisons cant leave their results in the opcode result area or their values will be clobbered by other parts of a complex expression.
2001-05-01 04:07:34 +02:00
/* Move the result out out the 4-7 bit that the compare
uses. This is because that bit may be clobbered by other
expressions. */
Remove short int restrictions from vvp opcodes.
2003-06-17 21:17:42 +02:00
{ unsigned base = allocate_vector(ewid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of equality compare.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Comparisons cant leave their results in the opcode result area or their values will be clobbered by other parts of a complex expression.
2001-05-01 04:07:34 +02:00
fprintf(vvp_out, " %%mov %u, %u, 1;\n", base, lv.base);
lv.base = base;
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
lv.wid = ewid;
if (ewid > 1)
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base+1, ewid-1);
Comparisons cant leave their results in the opcode result area or their values will be clobbered by other parts of a complex expression.
2001-05-01 04:07:34 +02:00
}
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
return lv;
}
Evaluate the logical AND operator.
2001-04-01 08:49:32 +02:00
static struct vector_info draw_binary_expr_land(ivl_expr_t exp, unsigned wid)
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
struct vector_info lv;
struct vector_info rv;
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr(le, STUFF_OK_XZ);
Support vectors as operands to logical and.
2001-10-10 06:47:43 +02:00
if ((lv.base >= 4) && (lv.wid > 1)) {
struct vector_info tmp;
clr_vector(lv);
tmp.base = allocate_vector(1);
tmp.wid = 1;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(tmp.base);
Support vectors as operands to logical and.
2001-10-10 06:47:43 +02:00
fprintf(vvp_out, " %%or/r %u, %u, %u;\n", tmp.base,
lv.base, lv.wid);
lv = tmp;
}
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
rv = draw_eval_expr(re, STUFF_OK_XZ);
Support vectors as operands to logical and.
2001-10-10 06:47:43 +02:00
if ((rv.base >= 4) && (rv.wid > 1)) {
struct vector_info tmp;
clr_vector(rv);
tmp.base = allocate_vector(1);
tmp.wid = 1;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(tmp.base);
Support vectors as operands to logical and.
2001-10-10 06:47:43 +02:00
fprintf(vvp_out, " %%or/r %u, %u, %u;\n", tmp.base,
rv.base, rv.wid);
rv = tmp;
}
Evaluate the logical AND operator.
2001-04-01 08:49:32 +02:00
if (lv.base < 4) {
if (rv.base < 4) {
unsigned lb = lv.base;
unsigned rb = rv.base;
if ((lb == 0) || (rb == 0)) {
lv.base = 0;
} else if ((lb == 1) && (rb == 1)) {
lv.base = 1;
} else {
lv.base = 2;
}
Support vectors as operands to logical and.
2001-10-10 06:47:43 +02:00
lv.wid = 1;
Evaluate the logical AND operator.
2001-04-01 08:49:32 +02:00
} else {
fprintf(vvp_out, " %%and %u, %u, 1;\n", rv.base, lv.base);
lv = rv;
}
} else {
fprintf(vvp_out, " %%and %u, %u, 1;\n", lv.base, rv.base);
clr_vector(rv);
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* If we only want the single bit result, then we are done. */
if (wid == 1)
return lv;
/* Write the result into a zero-padded result. */
Remove short int restrictions from vvp opcodes.
2003-06-17 21:17:42 +02:00
{ unsigned base = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of padded logical AND.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%mov %u, %u, 1;\n", base, lv.base);
clr_vector(lv);
lv.base = base;
lv.wid = wid;
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base+1, wid-1);
}
Evaluate the logical AND operator.
2001-04-01 08:49:32 +02:00
return lv;
}
Evalulate logical or (||)
2001-04-29 22:47:39 +02:00
static struct vector_info draw_binary_expr_lor(ivl_expr_t exp, unsigned wid)
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
struct vector_info lv;
struct vector_info rv;
Proper width handling of || expressions.
2003-05-10 04:38:49 +02:00
lv = draw_eval_expr(le, STUFF_OK_XZ);
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* if the left operand has width, then evaluate the single-bit
Spelling fixes (larry doolittle)
2007-02-26 20:49:48 +01:00
logical equivalent. */
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
if ((lv.base >= 4) && (lv.wid > 1)) {
struct vector_info tmp;
clr_vector(lv);
tmp.base = allocate_vector(1);
tmp.wid = 1;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(tmp.base);
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%or/r %u, %u, %u;\n", tmp.base,
lv.base, lv.wid);
lv = tmp;
}
Proper width handling of || expressions.
2003-05-10 04:38:49 +02:00
rv = draw_eval_expr(re, STUFF_OK_XZ);
Evalulate logical or (||)
2001-04-29 22:47:39 +02:00
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* if the right operand has width, then evaluate the single-bit
Spelling fixes (larry doolittle)
2007-02-26 20:49:48 +01:00
logical equivalent. */
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
if ((rv.base >= 4) && (rv.wid > 1)) {
struct vector_info tmp;
clr_vector(rv);
tmp.base = allocate_vector(1);
tmp.wid = 1;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(tmp.base);
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%or/r %u, %u, %u;\n", tmp.base,
rv.base, rv.wid);
rv = tmp;
}
Evalulate logical or (||)
2001-04-29 22:47:39 +02:00
if (lv.base < 4) {
if (rv.base < 4) {
unsigned lb = lv.base;
unsigned rb = rv.base;
if ((lb == 0) && (rb == 0)) {
lv.base = 0;
} else if ((lb == 1) || (rb == 1)) {
lv.base = 1;
} else {
lv.base = 2;
}
} else {
fprintf(vvp_out, " %%or %u, %u, 1;\n", rv.base, lv.base);
lv = rv;
}
} else {
OR is %or. Get this right.
2001-04-30 07:11:18 +02:00
fprintf(vvp_out, " %%or %u, %u, 1;\n", lv.base, rv.base);
Evalulate logical or (||)
2001-04-29 22:47:39 +02:00
clr_vector(rv);
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* If we only want the single bit result, then we are done. */
if (wid == 1)
return lv;
/* Write the result into a zero-padded result. */
Remove short int restrictions from vvp opcodes.
2003-06-17 21:17:42 +02:00
{ unsigned base = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of padded logical OR.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%mov %u, %u, 1;\n", base, lv.base);
clr_vector(lv);
lv.base = base;
lv.wid = wid;
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base+1, wid-1);
}
Evalulate logical or (||)
2001-04-29 22:47:39 +02:00
return lv;
}
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
static struct vector_info draw_binary_expr_le_real(ivl_expr_t exp)
{
struct vector_info res;
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
int lword = draw_eval_real(le);
int rword = draw_eval_real(re);
res.base = allocate_vector(1);
res.wid = 1;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
clr_word(lword);
clr_word(rword);
switch (ivl_expr_opcode(exp)) {
case '<':
fprintf(vvp_out, " %%cmp/wr %d, %d;\n", lword, rword);
fprintf(vvp_out, " %%mov %u, 5, 1;\n", res.base);
break;
Handle real value subtract and comparisons.
2003-02-07 03:46:16 +01:00
case 'L': /* <= */
fprintf(vvp_out, " %%cmp/wr %d, %d;\n", lword, rword);
fprintf(vvp_out, " %%or 5, 4, 1;\n");
fprintf(vvp_out, " %%mov %u, 5, 1;\n", res.base);
break;
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
case '>':
fprintf(vvp_out, " %%cmp/wr %d, %d;\n", rword, lword);
fprintf(vvp_out, " %%mov %u, 5, 1;\n", res.base);
break;
Handle real value subtract and comparisons.
2003-02-07 03:46:16 +01:00
case 'G': /* >= */
fprintf(vvp_out, " %%cmp/wr %d, %d;\n", rword, lword);
fprintf(vvp_out, " %%or 5, 4, 1;\n");
fprintf(vvp_out, " %%mov %u, 5, 1;\n", res.base);
break;
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
default:
assert(0);
}
return res;
}
Support bool expressions and compares handle them optimally.
2005-09-14 04:53:13 +02:00
static struct vector_info draw_binary_expr_le_bool(ivl_expr_t exp,
unsigned wid)
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
int lw, rw;
struct vector_info tmp;
char s_flag = (ivl_expr_signed(le) && ivl_expr_signed(re)) ? 's' : 'u';
assert(ivl_expr_value(le) == IVL_VT_BOOL);
assert(ivl_expr_value(re) == IVL_VT_BOOL);
lw = draw_eval_bool64(le);
rw = draw_eval_bool64(re);
switch (ivl_expr_opcode(exp)) {
case 'G':
fprintf(vvp_out, " %%cmp/w%c %u, %u;\n", s_flag, rw, lw);
fprintf(vvp_out, " %%or 5, 4, 1;\n");
break;
case 'L':
fprintf(vvp_out, " %%cmp/w%c %u, %u;\n", s_flag, lw, rw);
fprintf(vvp_out, " %%or 5, 4, 1;\n");
break;
case '<':
fprintf(vvp_out, " %%cmp/w%c %u, %u;\n", s_flag, lw, rw);
break;
case '>':
fprintf(vvp_out, " %%cmp/w%c %u, %u;\n", s_flag, rw, lw);
break;
default:
assert(0);
}
clr_word(lw);
clr_word(rw);
/* Move the result out out the 4-7 bit that the compare
uses. This is because that bit may be clobbered by other
expressions. */
{ unsigned base = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of padded inequality compare.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Support bool expressions and compares handle them optimally.
2005-09-14 04:53:13 +02:00
fprintf(vvp_out, " %%mov %u, 5, 1;\n", base);
tmp.base = base;
tmp.wid = wid;
if (wid > 1)
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base+1, wid-1);
}
return tmp;
}
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
static struct vector_info draw_binary_expr_le(ivl_expr_t exp,
unsigned wid,
int stuff_ok_flag)
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
struct vector_info lv;
struct vector_info rv;
Get signed compares working correctly in vvp.
2001-04-05 03:12:27 +02:00
char s_flag = (ivl_expr_signed(le) && ivl_expr_signed(re)) ? 's' : 'u';
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
unsigned owid = ivl_expr_width(le);
if (ivl_expr_width(re) > owid)
owid = ivl_expr_width(re);
Handle real value subtract and comparisons.
2003-02-07 03:46:16 +01:00
if (ivl_expr_value(le) == IVL_VT_REAL)
return draw_binary_expr_le_real(exp);
if (ivl_expr_value(re) == IVL_VT_REAL)
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
return draw_binary_expr_le_real(exp);
Support bool expressions and compares handle them optimally.
2005-09-14 04:53:13 +02:00
/* Detect the special case that we can do this with integers. */
if (ivl_expr_value(le) == IVL_VT_BOOL
&& ivl_expr_value(re) == IVL_VT_BOOL
&& owid < 64) {
return draw_binary_expr_le_bool(exp, wid);
}
assert(ivl_expr_value(le) == IVL_VT_LOGIC
|| ivl_expr_value(le) == IVL_VT_BOOL);
assert(ivl_expr_value(re) == IVL_VT_LOGIC
|| ivl_expr_value(re) == IVL_VT_BOOL);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
More lint removal tgt-vvp/eval_expr.c uninitialized variables vpi/sys_display.c uninitialized variables vvp/vpi_priv.cc deprecated string constant usage vvp/vpi_vthr_vector.cc deprecated string constant usage the last entry invokes vpip_name_string() and uses const char * in the same way as the other 9 callers in vvp/*.cc, the only difference is that the argument is static instead of computed.
2008-01-04 21:25:16 +01:00
lv.wid = 0; lv.base=0;
rv.wid = 0; rv.base=0;
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
switch (ivl_expr_opcode(exp)) {
Get signed compares working correctly in vvp.
2001-04-05 03:12:27 +02:00
case 'G':
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
rv = draw_eval_expr_wid(re, owid, STUFF_OK_XZ);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(le,16,0) && !number_is_unknown(le)) {
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
unsigned imm = get_number_immediate(le);
assert(imm >= 0);
fprintf(vvp_out, " %%cmpi/%c %u, %u, %u;\n", s_flag,
rv.base, imm, rv.wid);
} else {
lv = draw_eval_expr_wid(le, owid, STUFF_OK_XZ);
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/%c %u, %u, %u;\n", s_flag,
rv.base, lv.base, lv.wid);
}
Get signed compares working correctly in vvp.
2001-04-05 03:12:27 +02:00
fprintf(vvp_out, " %%or 5, 4, 1;\n");
break;
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
case 'L':
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
lv = draw_eval_expr_wid(le, owid, STUFF_OK_XZ);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(re,16,0) && !number_is_unknown(re)) {
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
unsigned imm = get_number_immediate(re);
assert(imm >= 0);
fprintf(vvp_out, " %%cmpi/%c %u, %u, %u;\n", s_flag,
lv.base, imm, lv.wid);
} else {
rv = draw_eval_expr_wid(re, owid, STUFF_OK_XZ);
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/%c %u, %u, %u;\n", s_flag,
lv.base, rv.base, lv.wid);
}
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
fprintf(vvp_out, " %%or 5, 4, 1;\n");
break;
case '<':
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
lv = draw_eval_expr_wid(le, owid, STUFF_OK_XZ);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(re,16,0) && !number_is_unknown(re)) {
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
unsigned imm = get_number_immediate(re);
assert(imm >= 0);
fprintf(vvp_out, " %%cmpi/%c %u, %u, %u;\n", s_flag,
lv.base, imm, lv.wid);
} else {
rv = draw_eval_expr_wid(re, owid, STUFF_OK_XZ);
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/%c %u, %u, %u;\n", s_flag,
lv.base, rv.base, lv.wid);
}
Get signed compares working correctly in vvp.
2001-04-05 03:12:27 +02:00
break;
case '>':
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
rv = draw_eval_expr_wid(re, owid, STUFF_OK_XZ);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(le,16,0) && !number_is_unknown(le)) {
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
unsigned imm = get_number_immediate(le);
assert(imm >= 0);
fprintf(vvp_out, " %%cmpi/%c %u, %u, %u;\n", s_flag,
rv.base, imm, rv.wid);
} else {
lv = draw_eval_expr_wid(le, owid, STUFF_OK_XZ);
assert(lv.wid == rv.wid);
fprintf(vvp_out, " %%cmp/%c %u, %u, %u;\n", s_flag,
rv.base, lv.base, lv.wid);
}
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
break;
default:
assert(0);
}
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
if (lv.wid > 0) clr_vector(lv);
if (rv.wid > 0) clr_vector(rv);
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
if ((stuff_ok_flag&STUFF_OK_47) && (wid == 1)) {
lv.base = 5;
lv.wid = wid;
return lv;
}
Comparisons cant leave their results in the opcode result area or their values will be clobbered by other parts of a complex expression.
2001-05-01 04:07:34 +02:00
/* Move the result out out the 4-7 bit that the compare
uses. This is because that bit may be clobbered by other
expressions. */
Remove short int restrictions from vvp opcodes.
2003-06-17 21:17:42 +02:00
{ unsigned base = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of padded inequality compare.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Comparisons cant leave their results in the opcode result area or their values will be clobbered by other parts of a complex expression.
2001-05-01 04:07:34 +02:00
fprintf(vvp_out, " %%mov %u, 5, 1;\n", base);
lv.base = base;
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
lv.wid = wid;
if (wid > 1)
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base+1, wid-1);
Comparisons cant leave their results in the opcode result area or their values will be clobbered by other parts of a complex expression.
2001-05-01 04:07:34 +02:00
}
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
return lv;
}
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
static struct vector_info draw_logic_immediate(ivl_expr_t exp,
ivl_expr_t le,
ivl_expr_t re,
unsigned wid)
{
struct vector_info lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
unsigned long imm = get_number_immediate(re);
assert(lv.base >= 4);
switch (ivl_expr_opcode(exp)) {
case '&':
fprintf(vvp_out, " %%andi %u, %lu, %u;\n", lv.base, imm, lv.wid);
break;
default:
assert(0);
break;
}
return lv;
}
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
static struct vector_info draw_binary_expr_logic(ivl_expr_t exp,
unsigned wid)
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
if (ivl_expr_opcode(exp) == '&') {
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(re, IMM_WID, 0) && !number_is_unknown(re))
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
return draw_logic_immediate(exp, le, re, wid);
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(le, IMM_WID, 0) && !number_is_unknown(le))
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
return draw_logic_immediate(exp, re, le, wid);
}
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
struct vector_info lv;
struct vector_info rv;
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
rv = draw_eval_expr_wid(re, wid, STUFF_OK_XZ);
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
Add support for behavioral xnor.
2001-04-15 06:07:56 +02:00
/* The result goes into the left operand, and that is returned
as the result. The instructions do not allow the lv value
to be a constant bit, so we either switch the operands, or
copy the vector into a new area. */
if (lv.base < 4) {
if (rv.base > 4) {
struct vector_info tmp = lv;
lv = rv;
rv = tmp;
} else {
struct vector_info tmp;
tmp.base = allocate_vector(lv.wid);
tmp.wid = lv.wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of binary logic.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Add support for behavioral xnor.
2001-04-15 06:07:56 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, lv.base, tmp.wid);
lv = tmp;
}
}
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
switch (ivl_expr_opcode(exp)) {
case '&':
Generate mixed real/vector expressions when needed. When generating a real expression you can have bits of the expression that use vector only operands. When this happens evaluate that part of the expression as a vector and then convert it to a real value.
2008-04-21 22:45:32 +02:00
fprintf(vvp_out, " %%and %u, %u, %u;\n",
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
lv.base, rv.base, wid);
break;
case '|':
Generate mixed real/vector expressions when needed. When generating a real expression you can have bits of the expression that use vector only operands. When this happens evaluate that part of the expression as a vector and then convert it to a real value.
2008-04-21 22:45:32 +02:00
fprintf(vvp_out, " %%or %u, %u, %u;\n",
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
lv.base, rv.base, wid);
break;
add XOR support.
2001-04-15 18:37:48 +02:00
case '^':
Generate mixed real/vector expressions when needed. When generating a real expression you can have bits of the expression that use vector only operands. When this happens evaluate that part of the expression as a vector and then convert it to a real value.
2008-04-21 22:45:32 +02:00
fprintf(vvp_out, " %%xor %u, %u, %u;\n",
add XOR support.
2001-04-15 18:37:48 +02:00
lv.base, rv.base, wid);
break;
Add support for binary nand operator.
2002-09-12 17:49:43 +02:00
case 'A': /* NAND (~&) */
fprintf(vvp_out, " %%nand %u, %u, %u;\n",
lv.base, rv.base, wid);
break;
Add support for binary NOR operator.
2002-09-18 06:29:55 +02:00
case 'O': /* NOR (~|) */
fprintf(vvp_out, " %%nor %u, %u, %u;\n",
lv.base, rv.base, wid);
break;
Add support for behavioral xnor.
2001-04-15 06:07:56 +02:00
case 'X': /* exclusive nor (~^) */
fprintf(vvp_out, " %%xnor %u, %u, %u;\n",
lv.base, rv.base, wid);
break;
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
default:
assert(0);
}
clr_vector(rv);
return lv;
}
Generate %shiftl instructions for shift.
2001-06-23 20:40:34 +02:00
/*
* Draw code to evaluate the << expression. Use the %shiftl/i0
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
* or %shiftr/i0 instruction to do the real work of shifting. This
* means that I can handle both left and right shifts in this
* function, with the only difference the opcode I generate at the
* end.
Generate %shiftl instructions for shift.
2001-06-23 20:40:34 +02:00
*/
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
static struct vector_info draw_binary_expr_lrs(ivl_expr_t exp, unsigned wid)
Left shift by a constant amount.
2001-04-21 03:49:17 +02:00
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
Evaluate shift index after shift operand because the chift operand may use the index register itself.
2002-12-20 02:11:14 +01:00
const char*opcode = "?";
Left shift by a constant amount.
2001-04-21 03:49:17 +02:00
struct vector_info lv;
Evaluate shift index after shift operand because the chift operand may use the index register itself.
2002-12-20 02:11:14 +01:00
/* Evaluate the expression that is to be shifted. */
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
switch (ivl_expr_opcode(exp)) {
Right shift by constant.
2001-04-21 05:26:23 +02:00
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
case 'l': /* << (left shift) */
Allow right values of right shift to shift in.
2002-11-21 23:42:48 +01:00
lv = draw_eval_expr_wid(le, wid, 0);
Careful of left operands to shift that are constant.
2002-11-22 01:01:50 +01:00
/* shifting 0 gets 0. */
if (lv.base == 0)
break;
if (lv.base < 4) {
struct vector_info tmp;
tmp.base = allocate_vector(lv.wid);
tmp.wid = lv.wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of left shift (<<).\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Careful of left operands to shift that are constant.
2002-11-22 01:01:50 +01:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, lv.base, lv.wid);
lv = tmp;
}
Evaluate shift index after shift operand because the chift operand may use the index register itself.
2002-12-20 02:11:14 +01:00
opcode = "%shiftl";
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
break;
Right shift by constant.
2001-04-21 05:26:23 +02:00
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
case 'r': /* >> (unsigned right shift) */
Allow right values of right shift to shift in.
2002-11-21 23:42:48 +01:00
/* with the right shift, there may be high bits that are
shifted into the desired width of the expression, so
we let the expression size itself, if it is bigger
then what is requested of us. */
if (wid > ivl_expr_width(le)) {
lv = draw_eval_expr_wid(le, wid, 0);
} else {
lv = draw_eval_expr_wid(le, ivl_expr_width(le), 0);
}
Careful of left operands to shift that are constant.
2002-11-22 01:01:50 +01:00
/* shifting 0 gets 0. */
if (lv.base == 0)
break;
if (lv.base < 4) {
struct vector_info tmp;
tmp.base = allocate_vector(lv.wid);
tmp.wid = lv.wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of right shift (>>).\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), lv.wid);
vvp_errors += 1;
}
Careful of left operands to shift that are constant.
2002-11-22 01:01:50 +01:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, lv.base, lv.wid);
lv = tmp;
}
Evaluate shift index after shift operand because the chift operand may use the index register itself.
2002-12-20 02:11:14 +01:00
opcode = "%shiftr";
Right shift by constant.
2001-04-21 05:26:23 +02:00
break;
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
Add arithmetic shift operators.
2003-06-18 05:55:18 +02:00
case 'R': /* >>> (signed right shift) */
/* with the right shift, there may be high bits that are
shifted into the desired width of the expression, so
we let the expression size itself, if it is bigger
then what is requested of us. */
if (wid > ivl_expr_width(le)) {
lv = draw_eval_expr_wid(le, wid, 0);
} else {
lv = draw_eval_expr_wid(le, ivl_expr_width(le), 0);
}
/* shifting 0 gets 0. */
if (lv.base == 0)
break;
/* Sign extend any constant begets itself, if this
expression is signed. */
if ((lv.base < 4) && (ivl_expr_signed(exp)))
break;
if (lv.base < 4) {
struct vector_info tmp;
tmp.base = allocate_vector(lv.wid);
tmp.wid = lv.wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of right shift (>>>).\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), lv.wid);
vvp_errors += 1;
}
Add arithmetic shift operators.
2003-06-18 05:55:18 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, lv.base, lv.wid);
lv = tmp;
}
if (ivl_expr_signed(exp))
opcode = "%shiftr/s";
else
opcode = "%shiftr";
break;
Right shift by constant.
2001-04-21 05:26:23 +02:00
default:
assert(0);
}
Evaluate shift index after shift operand because the chift operand may use the index register itself.
2002-12-20 02:11:14 +01:00
/* Figure out the shift amount and load that into the index
register. The value may be a constant, or may need to be
evaluated at run time. */
Add %ix/getv instruction The %ix/getv instruction loads an integer register directly from a signal vector. This is an optimization that an index register is loaded from an expression is only a signal. It avoids the thread vector space.
2007-12-07 22:12:19 +01:00
eval_logic_into_integer(re,0);
Evaluate shift index after shift operand because the chift operand may use the index register itself.
2002-12-20 02:11:14 +01:00
fprintf(vvp_out, " %s/i0 %u, %u;\n", opcode, lv.base, lv.wid);
if (lv.base >= 8)
save_expression_lookaside(lv.base, exp, lv.wid);
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
return lv;
Right shift by constant.
2001-04-21 05:26:23 +02:00
}
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
static struct vector_info draw_load_add_immediate(ivl_expr_t le,
ivl_expr_t re,
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
unsigned wid,
int signed_flag)
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
{
struct vector_info lv;
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
long imm = get_number_immediate(re);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
lv.base = allocate_vector(wid);
lv.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (lv.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of addition.\n",
ivl_expr_file(le), ivl_expr_lineno(le), wid);
vvp_errors += 1;
}
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
Add %load/avp0 opcode and fix %load/vp0. This patch adds a new opcode %load/avp0 that is used to load a word from an array and add a value to it. %load/vp0 was changed/fixed to do the summation at the result width not the vector width. This allows small vectors to index large arrays with an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 03:22:46 +01:00
/* Load the signal value with a %load that adds the index
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
register to the value being loaded. */
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
draw_signal_dest(le, lv, signed_flag, imm);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
return lv;
}
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
static struct vector_info draw_add_immediate(ivl_expr_t le,
ivl_expr_t re,
unsigned wid)
{
struct vector_info lv;
unsigned long imm;
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
assert(lv.wid == wid);
imm = get_number_immediate(re);
Fix handling of 32bit IMM in %addi on 32bit machines The handling of immediate add used to do 16bits at a time. When it went up to 32bits, the need to work in chunks vanished, but the chunk handling was still there, this time shifting by 32, which causes problems on 32bit machines. Simplify the %addi handling to avoid this.
2008-05-28 17:47:28 +02:00
/* This shouldn't generally happen, because the elaborator
should take care of simple constant propagation like this,
but it doesn't have to and it is easy to catch here. */
if (imm == 0)
return lv;
switch (lv.base) {
case 0: /* Left expression is 0. */
lv.base = allocate_vector(wid);
if (lv.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of addition.\n",
ivl_expr_file(re), ivl_expr_lineno(re), wid);
vvp_errors += 1;
}
fprintf(vvp_out, " %%movi %u, %lu %u;\n", lv.base, imm, wid);
break;
case 1: /* Left expression is 1...1 (i.e. -1) */
imm -= 1;
if (imm == 0) {
lv.base = 0;
} else {
lv.base = allocate_vector(wid);
if (lv.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of addition.\n",
ivl_expr_file(re), ivl_expr_lineno(re), wid);
vvp_errors += 1;
}
fprintf(vvp_out, " %%movi %u, %lu %u;\n", lv.base, imm, wid);
}
break;
case 2: /* Left expression is X or Z */
case 3:
lv.base = 2;
break;
default: /* The regular case. */
fprintf(vvp_out, " %%addi %u, %lu, %u;\n", lv.base, imm, wid);
break;
Use addi with wide immediate values.
2002-05-30 03:57:23 +02:00
}
Add %addi, which is faster to simulate.
2002-05-29 18:29:34 +02:00
return lv;
}
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
/*
* The subi is restricted to imm operands that are <= 16 bits wide.
*/
static struct vector_info draw_sub_immediate(ivl_expr_t le,
ivl_expr_t re,
unsigned wid)
{
struct vector_info lv;
unsigned long imm;
Subtract from constant values.
2003-08-03 05:53:38 +02:00
unsigned tmp;
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
assert(lv.wid == wid);
imm = get_number_immediate(re);
Fix handling of 32bit IMM in %addi on 32bit machines The handling of immediate add used to do 16bits at a time. When it went up to 32bits, the need to work in chunks vanished, but the chunk handling was still there, this time shifting by 32, which causes problems on 32bit machines. Simplify the %addi handling to avoid this.
2008-05-28 17:47:28 +02:00
if (imm == 0)
return lv;
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
Subtract from constant values.
2003-08-03 05:53:38 +02:00
switch (lv.base) {
case 0:
case 1:
tmp = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of subtraction.\n",
ivl_expr_file(le), ivl_expr_lineno(le), wid);
vvp_errors += 1;
}
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n", tmp, lv.base, wid);
Subtract from constant values.
2003-08-03 05:53:38 +02:00
lv.base = tmp;
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%subi %u, %lu, %u;\n", lv.base, imm, wid);
Fix handling of 32bit IMM in %addi on 32bit machines The handling of immediate add used to do 16bits at a time. When it went up to 32bits, the need to work in chunks vanished, but the chunk handling was still there, this time shifting by 32, which causes problems on 32bit machines. Simplify the %addi handling to avoid this.
2008-05-28 17:47:28 +02:00
break;
Subtract from constant values.
2003-08-03 05:53:38 +02:00
case 2:
case 3:
lv.base = 2;
Fix handling of 32bit IMM in %addi on 32bit machines The handling of immediate add used to do 16bits at a time. When it went up to 32bits, the need to work in chunks vanished, but the chunk handling was still there, this time shifting by 32, which causes problems on 32bit machines. Simplify the %addi handling to avoid this.
2008-05-28 17:47:28 +02:00
break;
Subtract from constant values.
2003-08-03 05:53:38 +02:00
default:
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%subi %u, %lu, %u;\n", lv.base, imm, wid);
Fix handling of 32bit IMM in %addi on 32bit machines The handling of immediate add used to do 16bits at a time. When it went up to 32bits, the need to work in chunks vanished, but the chunk handling was still there, this time shifting by 32, which causes problems on 32bit machines. Simplify the %addi handling to avoid this.
2008-05-28 17:47:28 +02:00
break;
Subtract from constant values.
2003-08-03 05:53:38 +02:00
}
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
return lv;
}
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
static struct vector_info draw_mul_immediate(ivl_expr_t le,
ivl_expr_t re,
unsigned wid)
{
struct vector_info lv;
unsigned long imm;
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
assert(lv.wid == wid);
imm = get_number_immediate(re);
Fix handling of 32bit IMM in %addi on 32bit machines The handling of immediate add used to do 16bits at a time. When it went up to 32bits, the need to work in chunks vanished, but the chunk handling was still there, this time shifting by 32, which causes problems on 32bit machines. Simplify the %addi handling to avoid this.
2008-05-28 17:47:28 +02:00
if (imm == 0)
return lv;
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%muli %u, %lu, %u;\n", lv.base, imm, lv.wid);
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
return lv;
}
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
static struct vector_info draw_binary_expr_arith(ivl_expr_t exp, unsigned wid)
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
{
ivl_expr_t le = ivl_expr_oper1(exp);
ivl_expr_t re = ivl_expr_oper2(exp);
struct vector_info lv;
struct vector_info rv;
Arithmetic operands can do unsigned work and have signed result. It is a quirk of the $signed() system function that the argument is converted to signed, but the operation that is performed is not changed. So arithmetic operators on unsigned arguments inside a $signed() expression still perform unsigned arithmetic.
2008-05-14 20:51:53 +02:00
const char*sign_string = ivl_expr_signed(le) && ivl_expr_signed(re)? "/s" : "";
Support signed integer division.
2002-04-14 20:41:34 +02:00
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
int signed_flag = ivl_expr_signed(exp)? 1 : 0;
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
if ((ivl_expr_opcode(exp) == '+')
&& (ivl_expr_type(le) == IVL_EX_SIGNAL)
&& (ivl_expr_type(re) == IVL_EX_ULONG))
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
return draw_load_add_immediate(le, re, wid, signed_flag);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
if ((ivl_expr_opcode(exp) == '+')
&& (ivl_expr_type(le) == IVL_EX_SIGNAL)
&& (ivl_expr_type(re) == IVL_EX_NUMBER))
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
return draw_load_add_immediate(le, re, wid, signed_flag);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
if ((ivl_expr_opcode(exp) == '+')
&& (ivl_expr_type(re) == IVL_EX_SIGNAL)
&& (ivl_expr_type(le) == IVL_EX_ULONG))
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
return draw_load_add_immediate(re, le, wid, signed_flag);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
if ((ivl_expr_opcode(exp) == '+')
&& (ivl_expr_type(re) == IVL_EX_SIGNAL)
&& (ivl_expr_type(le) == IVL_EX_NUMBER))
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
return draw_load_add_immediate(re, le, wid, signed_flag);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
Add %addi, which is faster to simulate.
2002-05-29 18:29:34 +02:00
if ((ivl_expr_opcode(exp) == '+')
&& (ivl_expr_type(re) == IVL_EX_ULONG))
return draw_add_immediate(le, re, wid);
if ((ivl_expr_opcode(exp) == '+')
Use addi with wide immediate values.
2002-05-30 03:57:23 +02:00
&& (ivl_expr_type(re) == IVL_EX_NUMBER)
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
&& (! number_is_unknown(re))
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
&& number_is_immediate(re, 8*sizeof(unsigned long), 0))
Add %addi, which is faster to simulate.
2002-05-29 18:29:34 +02:00
return draw_add_immediate(le, re, wid);
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
if ((ivl_expr_opcode(exp) == '-')
&& (ivl_expr_type(re) == IVL_EX_ULONG))
return draw_sub_immediate(le, re, wid);
if ((ivl_expr_opcode(exp) == '-')
&& (ivl_expr_type(re) == IVL_EX_NUMBER)
&& (! number_is_unknown(re))
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
&& number_is_immediate(re, IMM_WID, 0))
Add the %subi instruction, and use it where possible.
2002-08-28 20:38:07 +02:00
return draw_sub_immediate(le, re, wid);
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
if ((ivl_expr_opcode(exp) == '*')
&& (ivl_expr_type(re) == IVL_EX_NUMBER)
&& (! number_is_unknown(re))
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
&& number_is_immediate(re, IMM_WID, 0))
Generate %muli instructions when possible.
2002-05-31 22:04:57 +02:00
return draw_mul_immediate(le, re, wid);
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
rv = draw_eval_expr_wid(re, wid, STUFF_OK_XZ|STUFF_OK_RO);
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
if (lv.wid != wid) {
fprintf(stderr, "XXXX ivl_expr_opcode(exp) = %c,"
" lv.wid=%u, wid=%u\n", ivl_expr_opcode(exp),
lv.wid, wid);
}
Add support for structural multiply in t-dll. Add code generators and vvp support for both structural and behavioral multiply.
2001-06-17 01:45:05 +02:00
assert(lv.wid == wid);
assert(rv.wid == wid);
Handle constant bits in arithmetic expressions.
2001-10-14 05:24:35 +02:00
/* The arithmetic instructions replace the left operand with
the result. If the left operand is a replicated constant,
Spelling fixes (larry doolittle)
2007-02-26 20:49:48 +01:00
then I need to make a writable copy so that the
Handle constant bits in arithmetic expressions.
2001-10-14 05:24:35 +02:00
instruction can operate. */
if (lv.base < 4) {
struct vector_info tmp;
tmp.base = allocate_vector(wid);
tmp.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of arithmetic expression.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Handle constant bits in arithmetic expressions.
2001-10-14 05:24:35 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n", tmp.base,
lv.base, wid);
lv = tmp;
}
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
switch (ivl_expr_opcode(exp)) {
case '+':
Support behavioral subtraction.
2001-05-02 03:57:25 +02:00
fprintf(vvp_out, " %%add %u, %u, %u;\n", lv.base, rv.base, wid);
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
break;
case '-':
fprintf(vvp_out, " %%sub %u, %u, %u;\n", lv.base, rv.base, wid);
break;
Add support for structural multiply in t-dll. Add code generators and vvp support for both structural and behavioral multiply.
2001-06-17 01:45:05 +02:00
case '*':
fprintf(vvp_out, " %%mul %u, %u, %u;\n", lv.base, rv.base, wid);
break;
Generate %div instructions for binary /.
2001-10-16 03:27:17 +02:00
case '/':
Support signed integer division.
2002-04-14 20:41:34 +02:00
fprintf(vvp_out, " %%div%s %u, %u, %u;\n", sign_string,
lv.base, rv.base, wid);
Generate %div instructions for binary /.
2001-10-16 03:27:17 +02:00
break;
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
case '%':
Generate signed modulus if appropriate.
2004-06-19 18:17:37 +02:00
fprintf(vvp_out, " %%mod%s %u, %u, %u;\n", sign_string,
lv.base, rv.base, wid);
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
break;
Catch that we do not currently support unsigned bit based power. This patch adds a check and prints a warning message when the power operator is used with unsigned bit based values. It also fixes a couple of typos and adds an asserts if the above power operator happens to get to the tgt-vvp back end.
2008-02-04 22:04:20 +01:00
case 'p':
Add unsigned bit based power support to normal expressions. This patch adds bit based power support to normal expressions. It also pushes the constant unsigned bit based calculation to the runtime until the bit based method can be copied to the compiler. Continuous assignments also need to use this type of calculation.
2008-02-05 04:43:50 +01:00
fprintf(vvp_out, " %%pow%s %u, %u, %u;\n", sign_string,
lv.base, rv.base, wid);
Catch that we do not currently support unsigned bit based power. This patch adds a check and prints a warning message when the power operator is used with unsigned bit based values. It also fixes a couple of typos and adds an asserts if the above power operator happens to get to the tgt-vvp back end.
2008-02-04 22:04:20 +01:00
break;
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
default:
assert(0);
}
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
clr_vector(rv);
return lv;
}
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
static struct vector_info draw_binary_expr(ivl_expr_t exp,
unsigned wid,
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
int stuff_ok_flag)
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
{
struct vector_info rv;
Properly set or clear expression lookaside for binary expressions.
2002-10-20 04:55:37 +02:00
int stuff_ok_used_flag = 0;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
switch (ivl_expr_opcode(exp)) {
Evaluate the logical AND operator.
2001-04-01 08:49:32 +02:00
case 'a': /* && (logical and) */
rv = draw_binary_expr_land(exp, wid);
break;
Evaluate === and !==
2001-03-27 08:43:27 +02:00
case 'E': /* === */
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
case 'e': /* == */
Evaluate === and !==
2001-03-27 08:43:27 +02:00
case 'N': /* !== */
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
case 'n': /* != */
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
rv = draw_binary_expr_eq(exp, wid, stuff_ok_flag);
Properly set or clear expression lookaside for binary expressions.
2002-10-20 04:55:37 +02:00
stuff_ok_used_flag = 1;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
break;
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
case '<':
Get signed compares working correctly in vvp.
2001-04-05 03:12:27 +02:00
case '>':
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
case 'L': /* <= */
Get signed compares working correctly in vvp.
2001-04-05 03:12:27 +02:00
case 'G': /* >= */
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
rv = draw_binary_expr_le(exp, wid, stuff_ok_flag);
Properly set or clear expression lookaside for binary expressions.
2002-10-20 04:55:37 +02:00
stuff_ok_used_flag = 1;
Generate code for < and <=.
2001-04-01 09:22:42 +02:00
break;
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
case '+':
Support behavioral subtraction.
2001-05-02 03:57:25 +02:00
case '-':
Add support for structural multiply in t-dll. Add code generators and vvp support for both structural and behavioral multiply.
2001-06-17 01:45:05 +02:00
case '*':
Generate %div instructions for binary /.
2001-10-16 03:27:17 +02:00
case '/':
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
case '%':
Catch that we do not currently support unsigned bit based power. This patch adds a check and prints a warning message when the power operator is used with unsigned bit based values. It also fixes a couple of typos and adds an asserts if the above power operator happens to get to the tgt-vvp back end.
2008-02-04 22:04:20 +01:00
case 'p':
Add behavioral modulus.
2001-05-24 06:20:10 +02:00
rv = draw_binary_expr_arith(exp, wid);
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
break;
Right shift by constant.
2001-04-21 05:26:23 +02:00
case 'l': /* << */
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
case 'r': /* >> */
Add arithmetic shift operators.
2003-06-18 05:55:18 +02:00
case 'R': /* >>> */
Support non-const right shift (unsigned).
2001-06-30 23:07:26 +02:00
rv = draw_binary_expr_lrs(exp, wid);
Left shift by a constant amount.
2001-04-21 03:49:17 +02:00
break;
Evalulate logical or (||)
2001-04-29 22:47:39 +02:00
case 'o': /* || (logical or) */
rv = draw_binary_expr_lor(exp, wid);
break;
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
case '&':
case '|':
add XOR support.
2001-04-15 18:37:48 +02:00
case '^':
Add support for binary nand operator.
2002-09-12 17:49:43 +02:00
case 'A': /* NAND (~&) */
Add support for binary NOR operator.
2002-09-18 06:29:55 +02:00
case 'O': /* NOR (~|) */
Add support for binary nand operator.
2002-09-12 17:49:43 +02:00
case 'X': /* XNOR (~^) */
Evaluate binary & and | operators.
2001-04-02 05:47:49 +02:00
rv = draw_binary_expr_logic(exp, wid);
break;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
default:
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
fprintf(stderr, "vvp.tgt error: unsupported binary (%c)\n",
ivl_expr_opcode(exp));
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
assert(0);
}
Properly set or clear expression lookaside for binary expressions.
2002-10-20 04:55:37 +02:00
/* Mark in the lookaside that this value is done. If any OK
flags besides the STUFF_OK_47 flag are set, then the result
may not be a pure one, so clear the lookaside for the range
instead of setting in to the new expression result.
The stuff_ok_used_flag tells me if the stuff_ok_flag was
even used by anything. If not, then I can ignore it in the
following logic. */
if (rv.base >= 8) {
if (stuff_ok_used_flag && (stuff_ok_flag & ~STUFF_OK_47))
save_expression_lookaside(rv.base, 0, wid);
else
save_expression_lookaside(rv.base, exp, wid);
}
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
return rv;
}
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
/*
* The concatenation operator is evaluated by evaluating each sub-
Spelling fixes (larry doolittle)
2007-02-26 20:49:48 +01:00
* expression, then copying it into the contiguous vector of the
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
* result. Do this until the result vector is filled.
*/
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
static struct vector_info draw_concat_expr(ivl_expr_t exp, unsigned wid,
int stuff_ok_flag)
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
{
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
unsigned off, rep;
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
struct vector_info res;
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
int alloc_exclusive = (stuff_ok_flag&STUFF_OK_RO) ? 0 : 1;
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
/* Allocate a vector to hold the result. */
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for result of concatenation.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
/* Get the repeat count. This must be a constant that has been
evaluated at compile time. The operands will be repeated to
form the result. */
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
rep = ivl_expr_repeat(exp);
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
off = 0;
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
while (rep > 0) {
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
/* Each repeat, evaluate the sub-expressions, from lsb
to msb, and copy each into the result vector. The
expressions are arranged in the concatenation from
MSB to LSB, to go through them backwards.
Abort the loop if the result vector gets filled up. */
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
unsigned idx = ivl_expr_parms(exp);
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
while ((idx > 0) && (off < wid)) {
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
ivl_expr_t arg = ivl_expr_parm(exp, idx-1);
unsigned awid = ivl_expr_width(arg);
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
unsigned trans;
struct vector_info avec;
/* Try to locate the subexpression in the
lookaside map. */
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
avec.base = allocate_vector_exp(arg, awid, alloc_exclusive);
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
avec.wid = awid;
trans = awid;
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
if ((off + awid) > wid)
trans = wid - off;
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
if (avec.base != 0) {
assert(awid == avec.wid);
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
res.base+off,
avec.base, trans);
clr_vector(avec);
} else {
struct vector_info dest;
dest.base = res.base+off;
dest.wid = trans;
draw_eval_expr_dest(arg, dest, 0);
}
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
idx -= 1;
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
off += trans;
Handle repeat for concatenation expressions.
2001-07-22 21:33:51 +02:00
assert(off <= wid);
}
rep -= 1;
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
}
Handle short l-values to concatenation.
2001-09-20 05:46:38 +02:00
/* Pad the result with 0, if necessary. */
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
if (off < wid) {
fprintf(vvp_out, " %%mov %u, 0, %u;\n",
res.base+off, wid-off);
}
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
/* Save the accumulated result in the lookaside map. */
if (res.base >= 8)
save_expression_lookaside(res.base, exp, wid);
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
return res;
}
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
/*
* A number in an expression is made up by copying constant bits into
* the allocated vector.
*/
static struct vector_info draw_number_expr(ivl_expr_t exp, unsigned wid)
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
{
unsigned idx;
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
unsigned nwid;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
struct vector_info res;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
const char*bits = ivl_expr_bits(exp);
res.wid = wid;
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
nwid = wid;
if (ivl_expr_width(exp) < nwid)
nwid = ivl_expr_width(exp);
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
/* If all the bits of the number have the same value, then we
can use a constant bit. There is no need to allocate wr
bits, and there is no need to generate any code. */
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
for (idx = 1 ; idx < nwid ; idx += 1) {
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
if (bits[idx] != bits[0])
break;
}
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
if (idx >= res.wid) {
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
switch (bits[0]) {
case '0':
res.base = 0;
break;
case '1':
res.base = 1;
break;
case 'x':
res.base = 2;
break;
case 'z':
res.base = 3;
break;
Fix warnings about uninitialized variables.
2005-09-19 22:18:20 +02:00
default:
assert(0);
res.base = 0;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
}
return res;
}
/* The number value needs to be represented as an allocated
vector. Allocate the vector and use %mov instructions to
load the constant bit values. */
res.base = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for number value.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
/* Detect the special case that the entire number fits in an
immediate. In this case we generate a single %movi
instruction. */
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if ((!number_is_unknown(exp)) && number_is_immediate(exp, IMM_WID,0)) {
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
unsigned long val = get_number_immediate(exp);
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%movi %u, %lu, %u;\n", res.base, val, wid);
Optomize runtime using immediate compare Implement compare-immediate instructions and generate code to use these new instructions to improve runtime performance. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-04 05:58:40 +02:00
return res;
}
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
/* Use %movi as much as possible to build the value into the
destination. Use the %mov to handle the remaining general
bits. */
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
idx = 0;
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
unsigned long val = 0;
unsigned val_bits = 0;
unsigned val_addr = res.base;
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
while (idx < nwid) {
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
char src = 0;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
switch (bits[idx]) {
case '0':
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
val_bits += 1;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
break;
case '1':
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
val |= 1UL << val_bits;
val_bits += 1;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
break;
case 'x':
src = '2';
break;
case 'z':
src = '3';
break;
}
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
if (val_bits >= IMM_WID
|| (val_bits>0 && src != 0)
|| (val_bits>0 && idx+1==nwid)) {
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%movi %u, %lu, %u;\n",
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
val_addr, val, val_bits);
val_addr += val_bits;
val_bits = 0;
val = 0;
}
if (src != 0) {
assert(val_bits == 0);
unsigned cnt;
for (cnt = 1 ; idx+cnt < nwid ; cnt += 1)
if (bits[idx+cnt] != bits[idx])
break;
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%mov %u, %c, %u;\n", val_addr, src, cnt);
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
val_addr += cnt;
idx += cnt-1;
}
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
Better optimization of constants in expressions Be more sophisticated with the code generated for constant values. When values are large, use an optimal mix of %movi and %mov instructions to get the desired value, no matter what the content.
2008-08-28 03:22:23 +02:00
idx += 1;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
}
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
/* Pad the number up to the expression width. */
Proper pad of signed constants.
2003-06-11 04:23:45 +02:00
if (idx < wid) {
if (ivl_expr_signed(exp) && bits[nwid-1] == '1')
fprintf(vvp_out, " %%mov %u, 1, %u;\n",
res.base+idx, wid-idx);
else if (bits[nwid-1] == 'x')
fprintf(vvp_out, " %%mov %u, 2, %u;\n",
res.base+idx, wid-idx);
else if (bits[nwid-1] == 'z')
fprintf(vvp_out, " %%mov %u, 3, %u;\n",
res.base+idx, wid-idx);
else
fprintf(vvp_out, " %%mov %u, 0, %u;\n",
res.base+idx, wid-idx);
}
Handle truncation/padding of numbers.
2001-03-29 07:16:25 +02:00
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
if (res.base >= 8)
save_expression_lookaside(res.base, exp, wid);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
return res;
}
Start handling pad of expressions in code generators.
2003-07-26 05:34:42 +02:00
/*
* The PAD expression takes a smaller node and pads it out to a larger
* value. It will zero extend or sign extend depending on the
* signedness of the expression.
*/
static struct vector_info draw_pad_expr(ivl_expr_t exp, unsigned wid)
{
struct vector_info subv;
struct vector_info res;
subv = draw_eval_expr(ivl_expr_oper1(exp), 0);
Relaxed width constraint on pad_expression output.
2004-09-10 02:14:31 +02:00
if (wid <= subv.wid) {
Start handling pad of expressions in code generators.
2003-07-26 05:34:42 +02:00
if (subv.base >= 8)
Relaxed width constraint on pad_expression output.
2004-09-10 02:14:31 +02:00
save_expression_lookaside(subv.base, exp, subv.wid);
res.base = subv.base;
res.wid = wid;
return res;
Start handling pad of expressions in code generators.
2003-07-26 05:34:42 +02:00
}
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"to pad expression.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Start handling pad of expressions in code generators.
2003-07-26 05:34:42 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
res.base, subv.base, subv.wid);
assert(wid > subv.wid);
if (ivl_expr_signed(exp)) {
unsigned idx;
for (idx = subv.wid ; idx < res.wid ; idx += 1)
fprintf(vvp_out, " %%mov %u, %u, 1;\n",
res.base+idx, subv.base+subv.wid-1);
} else {
fprintf(vvp_out, " %%mov %u, 0, %u;\n",
res.base+subv.wid, res.wid - subv.wid);
}
save_expression_lookaside(res.base, exp, wid);
return res;
}
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
static struct vector_info draw_realnum_expr(ivl_expr_t exp, unsigned wid)
{
struct vector_info res;
double val = ivl_expr_dvalue(exp);
Handle real constants in vector expressions.
2007-01-19 06:24:53 +01:00
long ival = val;
unsigned addr, run, idx;
int bit;
fprintf(vvp_out, "; draw_realnum_expr(%f, %u) as %ld\n",
val, wid, ival);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
Handle real constants in vector expressions.
2007-01-19 06:24:53 +01:00
addr = res.base;
run = 1;
bit = ival & 1;
ival >>= 1LL;
for (idx = 1 ; idx < wid ; idx += 1) {
int next_bit = ival & 1;
ival >>= 1LL;
if (next_bit == bit) {
run += 1;
continue;
}
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%mov %u, %d, %u;\n", addr, bit, run);
Handle real constants in vector expressions.
2007-01-19 06:24:53 +01:00
addr += run;
run = 1;
bit = next_bit;
}
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%mov %u, %d, %u;\n", addr, bit, run);
Handle real constants in vector expressions.
2007-01-19 06:24:53 +01:00
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
return res;
}
Process expression strings with octal constants correctly (tgt-vvp) tgt-vvp was taking strings and processing them as is, but the strings could contain octal constants. These constants needed to be converted to binary form before they could be turned into a bit pattern.
2007-11-14 04:51:20 +01:00
static char *process_octal_codes(const char *in, unsigned width)
{
unsigned idx = 0;
unsigned ridx = 0;
unsigned str_len = strlen(in);
char *out = (char *)malloc(str_len+1);
/* If we do not have any octal codes just return the input. */
if (width/8 == str_len) {
strcpy(out, in);
return out;
}
Fix two comparisons in tgt-vvp/eval_expr.c to use correct variable. This patch fixes two comparison that were using the wrong variable to determine when the end of the object had been reached.
2008-04-02 05:23:08 +02:00
while (ridx < str_len) {
Process expression strings with octal constants correctly (tgt-vvp) tgt-vvp was taking strings and processing them as is, but the strings could contain octal constants. These constants needed to be converted to binary form before they could be turned into a bit pattern.
2007-11-14 04:51:20 +01:00
/* An octal constant always has three digits. */
if (in[ridx] == '\\') {
out[idx] = (in[ridx+1]-'0')*64 + (in[ridx+2]-'0')*8 +
(in[ridx+3]-'0');
idx += 1;
ridx += 4;
} else {
out[idx] = in[ridx];
idx += 1;
ridx += 1;
}
}
out[idx] = '\0';
return out;
}
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
/*
* A string in an expression is made up by copying constant bits into
* the allocated vector.
*/
static struct vector_info draw_string_expr(ivl_expr_t exp, unsigned wid)
{
struct vector_info res;
Process expression strings with octal constants correctly (tgt-vvp) tgt-vvp was taking strings and processing them as is, but the strings could contain octal constants. These constants needed to be converted to binary form before they could be turned into a bit pattern.
2007-11-14 04:51:20 +01:00
char *p, *fp;
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
unsigned ewid, nwid;
Use movi to load string values. String values are known to be 2-value bits, so they are natural candidates for using the movi instruction to load the value in far fewer instructions. With this patch, up to 16bits (two bytes) at a time can be loaded per instruction. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-11-14 06:14:07 +01:00
unsigned idx;
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
res.wid = wid;
nwid = wid;
ewid = ivl_expr_width(exp);
if (ewid < nwid)
nwid = ewid;
Process expression strings with octal constants correctly (tgt-vvp) tgt-vvp was taking strings and processing them as is, but the strings could contain octal constants. These constants needed to be converted to binary form before they could be turned into a bit pattern.
2007-11-14 04:51:20 +01:00
/* Our string may have embedded \xxx sequences so they need
to be removed before we proceed. Returns a new string. */
fp = process_octal_codes(ivl_expr_string(exp), ewid);
p = fp;
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
p += (ewid / 8) - 1;
/* The string needs to be represented as an allocated
vector. Allocate the vector and use %mov instructions to
load the constant bit values. */
res.base = allocate_vector(wid);
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"for string value.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
Use movi to load string values. String values are known to be 2-value bits, so they are natural candidates for using the movi instruction to load the value in far fewer instructions. With this patch, up to 16bits (two bytes) at a time can be loaded per instruction. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-11-14 06:14:07 +01:00
/* Since this is a string, we know that all the bits are
defined and each character represents exactly 8 bits. Use
the %movi instruction to more efficiently move the string
around. */
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
idx = 0;
while (idx < nwid) {
Use movi to load string values. String values are known to be 2-value bits, so they are natural candidates for using the movi instruction to load the value in far fewer instructions. With this patch, up to 16bits (two bytes) at a time can be loaded per instruction. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-11-14 06:14:07 +01:00
unsigned bits;
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
unsigned trans = IMM_WID;
if (nwid-idx < trans)
Use movi to load string values. String values are known to be 2-value bits, so they are natural candidates for using the movi instruction to load the value in far fewer instructions. With this patch, up to 16bits (two bytes) at a time can be loaded per instruction. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-11-14 06:14:07 +01:00
trans = nwid-idx;
bits = *p;
p -= 1;
if (trans > 8) {
bits |= *p << 8;
p -= 1;
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
if (trans > 16) {
bits |= *p << 16;
p -= 1;
if (trans > 24) {
bits |= *p << 24;
p -= 1;
}
}
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
}
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%movi %u, %u, %u;\n", res.base+idx,bits,trans);
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
Use movi to load string values. String values are known to be 2-value bits, so they are natural candidates for using the movi instruction to load the value in far fewer instructions. With this patch, up to 16bits (two bytes) at a time can be loaded per instruction. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-11-14 06:14:07 +01:00
idx += trans;
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
}
/* Pad the number up to the expression width. */
if (idx < wid)
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%mov %u, 0, %u;\n", res.base+idx, wid-idx);
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
if (res.base >= 8)
save_expression_lookaside(res.base, exp, wid);
Process expression strings with octal constants correctly (tgt-vvp) tgt-vvp was taking strings and processing them as is, but the strings could contain octal constants. These constants needed to be converted to binary form before they could be turned into a bit pattern.
2007-11-14 04:51:20 +01:00
free(fp);
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
return res;
}
Get padding right when loading array word into big vector.
2007-02-12 05:37:58 +01:00
/*
* This function is given an expression, the preallocated vector
* result, and the swid that is filled in so far. The caller has
* already calculated the load swid bits of exp into the beginning of
* the res vector. This function just calculates the pad to fill out
* the res area.
*/
Pad type-punned user functions properly When user defined function calls are withing a $signed, the result needs to be properly padded. To make this work, handle padding of a function result exactly type the padding of a signal vector. this is natural in that the function return value *is* in a signal vector. This fixes pr1841300.
2007-12-16 07:05:56 +01:00
void pad_expr_in_place(ivl_expr_t exp, struct vector_info res, unsigned swid)
Get padding right when loading array word into big vector.
2007-02-12 05:37:58 +01:00
{
if (res.wid <= swid)
return;
if (ivl_expr_signed(exp)) {
unsigned idx;
for (idx = swid ; idx < res.wid ; idx += 1)
fprintf(vvp_out, " %%mov %u, %u, 1;\n",
res.base+idx, res.base+swid-1);
} else {
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
unsigned base = res.base+swid;
unsigned count = res.wid-swid;
/* The %movi is faster for larger widths, but for very
small counts, the %mov is faster. */
if (count > 4)
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%movi %u, 0, %u;\n", base, count);
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
else
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%mov %u, 0, %u;\n", base, count);
Get padding right when loading array word into big vector.
2007-02-12 05:37:58 +01:00
}
}
Handle part select expressions as variants of NetESignal/IVL_EX_SIGNAL objects, instead of creating new and useless temporary signals.
2001-07-27 06:51:44 +02:00
/*
* Evaluating a signal expression means loading the bits of the signal
* into the thread bits. Remember to account for the part select by
* offsetting the read from the lsi (least significant index) of the
* signal.
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
*
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
* If the add_index is 0, then generate a %load/vp0 to add the
* word0 value to the loaded value before storing it into the
* destination. If the add_index is 1, then generate a %load/vp0/s to
* do a signed load.
Handle part select expressions as variants of NetESignal/IVL_EX_SIGNAL objects, instead of creating new and useless temporary signals.
2001-07-27 06:51:44 +02:00
*/
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
static void draw_signal_dest(ivl_expr_t exp, struct vector_info res,
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
int add_index, long immediate)
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
{
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
unsigned swid = ivl_expr_width(exp);
Eliminate use of ivl_signal_name for signal labels.
2002-08-04 00:30:48 +02:00
ivl_signal_t sig = ivl_expr_signal(exp);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
unsigned word = 0;
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
if (swid > res.wid)
swid = res.wid;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
Add vpiFile and vpiLineNo for system functions. Add the vpiFile and vpiLineNo properties to system functions. Most other objects have stubs that return "N/A"/0. Interactive functions (called from the debugger) use <interactive> for the file name.
2008-01-01 18:45:02 +01:00
/* If this is an access to an array, handle that by emitting a
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
load/av instruction. */
Use ivl_signal_dimensions to detect that signal is an array. It is possible for an array to have 1 word in it, so using the array count to detect an array is incorrect. Use the ivl_signal_dimensions function, which is there exactly for that purpose.
2008-05-19 20:31:40 +02:00
if (ivl_signal_dimensions(sig) > 0) {
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
ivl_expr_t ix = ivl_expr_oper1(exp);
Add %load/avp0 opcode and fix %load/vp0. This patch adds a new opcode %load/avp0 that is used to load a word from an array and add a value to it. %load/vp0 was changed/fixed to do the summation at the result width not the vector width. This allows small vectors to index large arrays with an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 03:22:46 +01:00
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
draw_eval_expr_into_integer(ix, 3);
if (add_index < 0) {
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%load/av %u, v%p, %u;\n",
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
res.base, sig, swid);
Signed load-and-add for arrays. The load-and-add for vectors %load/vp0/s can be combined with the load-and-add for array words, and the %load/avp0/s added to round out the combinations. This can make for fewer instructions when words are padded in arithmetic expressions.
2008-06-15 04:59:57 +02:00
pad_expr_in_place(exp, res, swid);
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
} else {
Signed load-and-add for arrays. The load-and-add for vectors %load/vp0/s can be combined with the load-and-add for array words, and the %load/avp0/s added to round out the combinations. This can make for fewer instructions when words are padded in arithmetic expressions.
2008-06-15 04:59:57 +02:00
const char*sign_flag = (add_index>0)? "/s" : "";
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
/* Add an immediate value to an array value. */
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%ix/load 0, %lu;\n", immediate);
fprintf(vvp_out, " %%load/avp0%s %u, v%p, %u;\n",
Signed load-and-add for arrays. The load-and-add for vectors %load/vp0/s can be combined with the load-and-add for array words, and the %load/avp0/s added to round out the combinations. This can make for fewer instructions when words are padded in arithmetic expressions.
2008-06-15 04:59:57 +02:00
sign_flag, res.base, sig, res.wid);
Rework variable arrays to not have vpi handles for every word. Save tons of space per memory word by not creating a vpi handle for each and every word of a variable array. (Net arrays still get a vpiHandle for every word.) The consequence of this is that all accesses to a variable array need to go through the indexing. This commit handles the most common places where this impacts, but there are still problems.
2008-05-16 19:38:32 +02:00
}
return;
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
}
Fix code generation for real expressions Real value are vector width of 1, fix real literal to reflect this. fix leaking real registers in code generation for function arguments. Load of signal should handle conversion from real to vector. Function arguments, type vector passed a real value, are an example where this comes up. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-30 06:10:37 +02:00
if (ivl_signal_data_type(sig) == IVL_VT_REAL) {
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
assert(add_index < 0);
Fix code generation for real expressions Real value are vector width of 1, fix real literal to reflect this. fix leaking real registers in code generation for function arguments. Load of signal should handle conversion from real to vector. Function arguments, type vector passed a real value, are an example where this comes up. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-30 06:10:37 +02:00
int tmp = allocate_word();
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%load/wr %d, v%p_%u;\n", tmp, sig, word);
fprintf(vvp_out, " %%cvt/vr %u, %d, %u;\n", res.base, tmp, res.wid);
Fix code generation for real expressions Real value are vector width of 1, fix real literal to reflect this. fix leaking real registers in code generation for function arguments. Load of signal should handle conversion from real to vector. Function arguments, type vector passed a real value, are an example where this comes up. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-30 06:10:37 +02:00
clr_word(tmp);
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
} else if (add_index >= 0) {
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
const char*sign_flag = add_index==1? "/s" : "";
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
/* If this is a REG (a variable) then I can do a vector read. */
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
if (immediate >= 0) {
fprintf(vvp_out, " %%ix/load 0, %lu;\n", immediate);
} else {
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%ix/load 0, 0; immediate=%ld\n", immediate);
fprintf(vvp_out, " %%ix/sub 0, %ld;\n", -immediate);
Load_add_immediate to work with signed expressions The %load/vp0 instruction adds a signed value to the signal value being loaded, but it doesn't allow for a signed source vector. Add the %load/vp0/s instruction that pads the loaded vector, and add the code generator details to properly use it.
2008-06-14 05:23:40 +02:00
}
fprintf(vvp_out, " %%load/vp0%s %u, v%p_%u, %u;\n", sign_flag,
res.base, sig,word, res.wid);
Add %load/avp0 opcode and fix %load/vp0. This patch adds a new opcode %load/avp0 that is used to load a word from an array and add a value to it. %load/vp0 was changed/fixed to do the summation at the result width not the vector width. This allows small vectors to index large arrays with an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 03:22:46 +01:00
swid = res.wid;
Optimize load-add with load/add instruction Where and expression is an immediate value added to a signal value, it is possible to optimize them to a single instruction that combines the load with an add at the same time.
2007-12-05 04:15:15 +01:00
Fix code generation for real expressions Real value are vector width of 1, fix real literal to reflect this. fix leaking real registers in code generation for function arguments. Load of signal should handle conversion from real to vector. Function arguments, type vector passed a real value, are an example where this comes up. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-30 06:10:37 +02:00
} else {
/* If this is a REG (a variable) then I can do a vector read. */
fprintf(vvp_out, " %%load/v %u, v%p_%u, %u;\n",
res.base, sig, word, swid);
}
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
Get padding right when loading array word into big vector.
2007-02-12 05:37:58 +01:00
pad_expr_in_place(exp, res, swid);
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
}
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
static struct vector_info draw_signal_expr(ivl_expr_t exp, unsigned wid,
int stuff_ok_flag)
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
{
struct vector_info res;
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
int alloc_exclusive = (stuff_ok_flag&STUFF_OK_RO) ? 0 : 1;
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
/* Already in the vector lookaside? */
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
res.base = allocate_vector_exp(exp, wid, alloc_exclusive);
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
res.wid = wid;
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
if (res.base != 0) {
fprintf(vvp_out, "; Reuse signal base=%u wid=%u from lookaside.\n",
res.base, res.wid);
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
return res;
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
}
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"to load variable/wire.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
save_expression_lookaside(res.base, exp, wid);
Add %load/avp0 opcode and fix %load/vp0. This patch adds a new opcode %load/avp0 that is used to load a word from an array and add a value to it. %load/vp0 was changed/fixed to do the summation at the result width not the vector width. This allows small vectors to index large arrays with an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 03:22:46 +01:00
draw_signal_dest(exp, res, -1, 0L);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
return res;
}
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
static struct vector_info draw_select_array(ivl_expr_t sube,
ivl_expr_t bit_idx,
unsigned bit_width,
unsigned wid)
{
unsigned idx;
ivl_signal_t sig = ivl_expr_signal(sube);
Fix optimization of base==0 part select Some patch caused a variable that held the constant base of a part select to become unassigned. This led to unexplained failures to part select a signal. Fix by properly detecting the case of a constant base of 0 for the part select.
2007-12-10 02:00:32 +01:00
/* unsigned sig_wid = ivl_expr_width(sube); */
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
ivl_expr_t ix = ivl_expr_oper1(sube);
struct vector_info shiv;
struct vector_info res;
shiv = draw_eval_expr(bit_idx, STUFF_OK_XZ|STUFF_OK_RO);
draw_eval_expr_into_integer(ix, 3);
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%ix/get 0, %u, %u;\n", shiv.base, shiv.wid);
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
if (shiv.base >= 8)
clr_vector(shiv);
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"to hold selected value.\n",
ivl_expr_file(sube), ivl_expr_lineno(sube), wid);
vvp_errors += 1;
}
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
for (idx = 0 ; idx < wid ; idx += 1) {
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%load/avx.p %u, v%p, 0;\n", res.base+idx, sig);
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
}
return res;
}
Support constant part select writes to l-values, and large part select reads from signals.
2005-02-15 08:12:55 +01:00
static struct vector_info draw_select_signal(ivl_expr_t sube,
ivl_expr_t bit_idx,
Pad part selects
2005-12-22 16:42:22 +01:00
unsigned bit_wid,
Support constant part select writes to l-values, and large part select reads from signals.
2005-02-15 08:12:55 +01:00
unsigned wid)
{
ivl_signal_t sig = ivl_expr_signal(sube);
struct vector_info res;
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
/* Use this word of the signal. */
unsigned use_word = 0;
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
/* If this is an access to an array, try to get the index as a
Careful that select signal does not try to select reg words directly.
2008-05-19 20:44:03 +02:00
constant. If it is (and the array is not a reg array then
this reduces to a signal access and we stay here. If it is
not constant, then give up and do an array index in front
of this part select. */
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
Use ivl_signal_dimensions to detect that signal is an array. It is possible for an array to have 1 word in it, so using the array count to detect an array is incorrect. Use the ivl_signal_dimensions function, which is there exactly for that purpose.
2008-05-19 20:31:40 +02:00
if (ivl_signal_dimensions(sig) > 0) {
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
ivl_expr_t ix = ivl_expr_oper1(sube);
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
Careful that select signal does not try to select reg words directly.
2008-05-19 20:44:03 +02:00
if (ivl_signal_type(sig)==IVL_SIT_REG
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
|| !number_is_immediate(ix, 8*sizeof(unsigned long),0))
Finish up part select of array words.
2007-04-14 06:43:01 +02:00
return draw_select_array(sube, bit_idx, bit_wid, wid);
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
/* The index is constant, so we can return to direct
readout with the specific word selected. */
use_word = get_number_immediate(ix);
}
Minor optimization of partial load/v When loading a part select from the least significant bits, it is OK to use the %load/v instruction to strip the high bits off. This allows the zero-based part select to work in one step, without loading excess bits.
2007-12-10 02:28:49 +01:00
/* Try the special case that the part is at the beginning of
the signal (or the entire width). Just load the early bits
in one go. */
Allow that sum immediate values can be signed. Actually, the immediate value handling is a little chaotic and should be cleaned up. This patch opens the door for allowing signed immediate values, and uses them in a few places where they are explicitly handled. We must go through the opcodes that can take immediate values and make explicit whether they are signed/unsigned/etc, and what their size limits are.
2008-06-13 22:32:06 +02:00
if (number_is_immediate(bit_idx, 32, 0)
Fix optimization of base==0 part select Some patch caused a variable that held the constant base of a part select to become unassigned. This led to unexplained failures to part select a signal. Fix by properly detecting the case of a constant base of 0 for the part select.
2007-12-10 02:00:32 +01:00
&& get_number_immediate(bit_idx) == 0
Correct bit widths and pad of certain part selects Zero-based part selects are a special case that is handled with optimized code. Properly handle the part select width to get the desired padding. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-12-26 17:22:33 +01:00
&& (ivl_expr_width(sube) >= bit_wid)) {
Minor optimization of partial load/v When loading a part select from the least significant bits, it is OK to use the %load/v instruction to strip the high bits off. This allows the zero-based part select to work in one step, without loading excess bits.
2007-12-10 02:28:49 +01:00
Improve loading of part selects when easy.
2005-09-17 06:01:32 +02:00
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%load/v %u, v%p_%u, %u; Only need %u of %u bits\n",
Correct bit widths and pad of certain part selects Zero-based part selects are a special case that is handled with optimized code. Properly handle the part select width to get the desired padding. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-12-26 17:22:33 +01:00
res.base, sig, use_word, bit_wid, bit_wid, ivl_expr_width(sube));
Non-controversial whitespace cleanup Nothing to do with tab width! Eliminates useless trailing spaces and tabs, and nearly all <space><tab> pairings. No change to derived files (e.g., .vvp), non-master files (e.g., lxt2_write.c) or the new tgt-vhdl directory. Low priority, simple entropy reduction. Please apply unless it deletes some steganographic content you want to keep.
2008-09-04 18:41:51 +02:00
Correct bit widths and pad of certain part selects Zero-based part selects are a special case that is handled with optimized code. Properly handle the part select width to get the desired padding. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-12-26 17:22:33 +01:00
save_signal_lookaside(res.base, sig, use_word, bit_wid);
/* Pad the part select to the desired width. Note that
this *should* always turn into an unsigned pad
because part selects are always unsigned. */
pad_expr_in_place(sube, res, bit_wid);
Improve loading of part selects when easy.
2005-09-17 06:01:32 +02:00
return res;
}
/* Alas, do it the hard way. */
Change bit select instruction to a part select. There is no point in having a bit select instruction and running it in a loop (always) when we can simply turn it into a part select instruction.
2008-06-11 02:29:47 +02:00
draw_eval_expr_into_integer(bit_idx, 1);
Support constant part select writes to l-values, and large part select reads from signals.
2005-02-15 08:12:55 +01:00
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Support constant part select writes to l-values, and large part select reads from signals.
2005-02-15 08:12:55 +01:00
Change bit select instruction to a part select. There is no point in having a bit select instruction and running it in a loop (always) when we can simply turn it into a part select instruction.
2008-06-11 02:29:47 +02:00
unsigned use_wid = res.wid;
if (use_wid > bit_wid)
use_wid = bit_wid;
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%load/x1p %u, v%p_%u, %u;\n",
Change bit select instruction to a part select. There is no point in having a bit select instruction and running it in a loop (always) when we can simply turn it into a part select instruction.
2008-06-11 02:29:47 +02:00
res.base, sig, use_word, use_wid);
if (use_wid < res.wid)
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%movi %u, 0, %u;\n",
Change bit select instruction to a part select. There is no point in having a bit select instruction and running it in a loop (always) when we can simply turn it into a part select instruction.
2008-06-11 02:29:47 +02:00
res.base + use_wid, res.wid - use_wid);
Support constant part select writes to l-values, and large part select reads from signals.
2005-02-15 08:12:55 +01:00
return res;
}
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
static struct vector_info draw_select_expr(ivl_expr_t exp, unsigned wid,
int stuff_ok_flag)
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
{
struct vector_info subv, shiv, res;
ivl_expr_t sube = ivl_expr_oper1(exp);
ivl_expr_t shift = ivl_expr_oper2(exp);
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
int alloc_exclusive = (stuff_ok_flag&STUFF_OK_RO)? 0 : 1;
Fix warnings about uninitialized variables.
2005-09-19 22:18:20 +02:00
res.wid = wid;
Better reuse of IVL_EX_SELECT expressions.
2005-09-15 04:49:47 +02:00
/* First look for the self expression in the lookaside, and
Add vpiFile and vpiLineNo for system functions. Add the vpiFile and vpiLineNo properties to system functions. Most other objects have stubs that return "N/A"/0. Interactive functions (called from the debugger) use <interactive> for the file name.
2008-01-01 18:45:02 +01:00
allocate that if possible. If I find it, then immediately
Better reuse of IVL_EX_SELECT expressions.
2005-09-15 04:49:47 +02:00
return that. */
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
if ( (res.base = allocate_vector_exp(exp, wid, alloc_exclusive)) != 0) {
Better reuse of IVL_EX_SELECT expressions.
2005-09-15 04:49:47 +02:00
fprintf(vvp_out, "; Reuse base=%u wid=%u from lookaside.\n",
res.base, wid);
return res;
}
if (ivl_expr_type(sube) == IVL_EX_SIGNAL) {
Pad part selects
2005-12-22 16:42:22 +01:00
res = draw_select_signal(sube, shift, ivl_expr_width(exp), wid);
Better reuse of IVL_EX_SELECT expressions.
2005-09-15 04:49:47 +02:00
fprintf(vvp_out, "; Save base=%u wid=%u in lookaside.\n",
res.base, wid);
save_expression_lookaside(res.base, exp, wid);
return res;
}
Support constant part select writes to l-values, and large part select reads from signals.
2005-02-15 08:12:55 +01:00
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
/* Evaluate the sub-expression. */
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
subv = draw_eval_expr(sube, 0);
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
/* Any bit select of a constant zero is another constant zero,
so short circuit and return the value we know. */
if (subv.base == 0) {
subv.wid = wid;
return subv;
}
/* Evaluate the bit select base expression and store the
result into index register 0. */
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
shiv = draw_eval_expr(shift, STUFF_OK_XZ);
Special handling of constant shift 0.
2005-01-28 06:37:48 +01:00
/* Detect and handle the special case that the shift is a
constant 0. Skip the shift, and return the subexpression
with the width trimmed down to the desired width. */
if (shiv.base == 0) {
assert(subv.wid >= wid);
res.base = subv.base;
return res;
}
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
fprintf(vvp_out, " %%ix/get 0, %u, %u;\n", shiv.base, shiv.wid);
clr_vector(shiv);
/* If the subv result is a magic constant, then make a copy in
Spelling fixes (larry doolittle)
2007-02-26 20:49:48 +01:00
writable vector space and work from there instead. */
Fix parameter bit select check for magic constants.
2002-02-03 06:53:00 +01:00
if (subv.base < 4) {
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
res.base = allocate_vector(subv.wid);
Keep bit select subexpression width if it is constant.
2002-12-20 00:11:29 +01:00
res.wid = subv.wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n", res.base,
subv.base, res.wid);
subv = res;
}
fprintf(vvp_out, " %%shiftr/i0 %u, %u;\n", subv.base, subv.wid);
if (subv.wid > wid) {
res.base = subv.base;
res.wid = wid;
subv.base += wid;
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
subv.wid -= wid;
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
clr_vector(subv);
Fix warnings about uninitialized variables.
2005-09-19 22:18:20 +02:00
} else {
assert(subv.wid == wid);
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
res = subv;
}
Better reuse of IVL_EX_SELECT expressions.
2005-09-15 04:49:47 +02:00
if (res.base >= 8) {
fprintf(vvp_out, "; Save expression base=%u wid=%u in lookaside\n",
res.base, wid);
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
save_expression_lookaside(res.base, exp, wid);
Better reuse of IVL_EX_SELECT expressions.
2005-09-15 04:49:47 +02:00
}
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
return res;
}
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
static struct vector_info draw_ternary_expr(ivl_expr_t exp, unsigned wid)
{
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
struct vector_info res, tru, fal, tst;
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
unsigned lab_true, lab_false, lab_out;
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
ivl_expr_t cond = ivl_expr_oper1(exp);
ivl_expr_t true_ex = ivl_expr_oper2(exp);
ivl_expr_t false_ex = ivl_expr_oper3(exp);
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
lab_true = local_count++;
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
lab_false = local_count++;
lab_out = local_count++;
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
/* Evaluate the condition expression, and if necessary reduce
it to a single bit. */
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
tst = draw_eval_expr(cond, STUFF_OK_XZ|STUFF_OK_RO);
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
if ((tst.base >= 4) && (tst.wid > 1)) {
struct vector_info tmp;
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
Use all bits of ?: condit expression.
2002-07-12 20:10:45 +02:00
fprintf(vvp_out, " %%or/r %u, %u, %u;\n",
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
tst.base, tst.base, tst.wid);
tmp = tst;
tmp.base += 1;
tmp.wid -= 1;
clr_vector(tmp);
tst.wid = 1;
Use all bits of ?: condit expression.
2002-07-12 20:10:45 +02:00
}
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, " %%jmp/0 T_%d.%d, %u;\n",
thread_count, lab_true, tst.base);
tru = draw_eval_expr_wid(true_ex, wid, 0);
/* The true result must be in a writable register, because the
blend might want to manipulate it. */
if (tru.base < 4) {
struct vector_info tmp;
tmp.base = allocate_vector(wid);
tmp.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(tmp.base);
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, tru.base, wid);
tru = tmp;
}
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
fprintf(vvp_out, " %%jmp/1 T_%d.%d, %u;\n",
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
thread_count, lab_out, tst.base);
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
Clear expression lookaside after true cause of ternary.
2003-09-24 22:46:20 +02:00
clear_expression_lookaside();
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, "T_%d.%d ; End of true expr.\n",
thread_count, lab_true);
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fal = draw_eval_expr_wid(false_ex, wid, 0);
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, " %%jmp/0 T_%d.%d, %u;\n",
thread_count, lab_false, tst.base);
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, " ; End of false expr.\n");
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
clr_vector(tst);
clr_vector(fal);
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, " %%blend %u, %u, %u; Condition unknown.\n",
tru.base, fal.base, wid);
fprintf(vvp_out, " %%jmp T_%d.%d;\n",
Fix fprintf warning.
2003-06-17 00:14:15 +02:00
thread_count, lab_out);
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
fprintf(vvp_out, "T_%d.%d ;\n", thread_count, lab_false);
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
fprintf(vvp_out, " %%mov %u, %u, %u; Return false value\n",
tru.base, fal.base, wid);
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
Fix behavioral eval of x?a:b expressions.
2002-08-22 05:38:40 +02:00
/* This is the out label. */
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
fprintf(vvp_out, "T_%d.%d ;\n", thread_count, lab_out);
Allow expression lookaside map to spam statements.
2002-09-27 22:24:42 +02:00
clear_expression_lookaside();
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
More efficient code for ternary expressions.
2003-06-16 00:49:32 +02:00
res = tru;
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
if (res.base >= 8)
save_expression_lookaside(res.base, exp, wid);
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
return res;
}
Initial support for system functions.
2001-05-20 03:02:55 +02:00
static struct vector_info draw_sfunc_expr(ivl_expr_t exp, unsigned wid)
{
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
unsigned parm_count = ivl_expr_parms(exp);
Initial support for system functions.
2001-05-20 03:02:55 +02:00
struct vector_info res;
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
/* If the function has no parameters, then use this short-form
to draw the statement. */
if (parm_count == 0) {
Support bool expressions and compares handle them optimally.
2005-09-14 04:53:13 +02:00
assert(ivl_expr_value(exp) == IVL_VT_LOGIC
|| ivl_expr_value(exp) == IVL_VT_BOOL);
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
res.base = allocate_vector(wid);
res.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Add vpiFile and vpiLineNo for system functions. Add the vpiFile and vpiLineNo properties to system functions. Most other objects have stubs that return "N/A"/0. Interactive functions (called from the debugger) use <interactive> for the file name.
2008-01-01 18:45:02 +01:00
fprintf(vvp_out, " %%vpi_func %u %u \"%s\", %u, %u;\n",
Rework ivl_file_table_* interface and fix most vvp/examples. Rework the ivl_file_table_* interface to be more generic and easier to use. Also all the vvp examples except for memory.vvp have been fixed to run correctly with the current vvp. Someone with a bit more experience will need to fix memory.vvp.
2008-01-02 19:42:23 +01:00
ivl_file_table_index(ivl_expr_file(exp)),
Add vpiFile and vpiLineNo for system functions. Add the vpiFile and vpiLineNo properties to system functions. Most other objects have stubs that return "N/A"/0. Interactive functions (called from the debugger) use <interactive> for the file name.
2008-01-01 18:45:02 +01:00
ivl_expr_lineno(exp), ivl_expr_name(exp),
res.base, res.wid);
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
return res;
}
Allow real-valued vpi functions to have arguments.
2003-03-15 05:45:18 +01:00
res = draw_vpi_func_call(exp, wid);
Pass parameters to system functions.
2001-07-07 22:20:10 +02:00
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
/* New basic block starts after VPI calls. */
clear_expression_lookaside();
Initial support for system functions.
2001-05-20 03:02:55 +02:00
return res;
}
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
static struct vector_info draw_unary_expr(ivl_expr_t exp, unsigned wid)
{
struct vector_info res;
ivl_expr_t sub = ivl_expr_oper1(exp);
Support vectors as operands to logical and.
2001-10-10 06:47:43 +02:00
const char *rop = 0;
More behavioral unary reduction operators. (Stephan Boettcher)
2001-06-18 03:09:32 +02:00
int inv = 0;
switch (ivl_expr_opcode(exp)) {
case '&': rop = "and"; break;
case '|': rop = "or"; break;
case '^': rop = "xor"; break;
case 'A': rop = "nand"; break;
case 'N': rop = "nor"; break;
case 'X': rop = "xnor"; break;
}
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
switch (ivl_expr_opcode(exp)) {
case '~':
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
res = draw_eval_expr_wid(sub, wid, STUFF_OK_XZ);
Handle update in place of repeat constants.
2001-08-31 03:37:56 +02:00
switch (res.base) {
case 0:
res.base = 1;
break;
case 1:
res.base = 0;
break;
case 2:
case 3:
res.base = 2;
break;
default:
fprintf(vvp_out, " %%inv %u, %u;\n", res.base, res.wid);
break;
}
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
break;
Generate code for unary minus (PR#272)
2001-09-29 06:37:44 +02:00
case '-':
/* Unary minus is implemented by generating the 2's
complement of the number. That is the 1's complement
(bitwise invert) with a 1 added in. Note that the
%sub subtracts -1 (1111...) to get %add of +1. */
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
res = draw_eval_expr_wid(sub, wid, STUFF_OK_XZ);
Generate code for unary minus (PR#272)
2001-09-29 06:37:44 +02:00
switch (res.base) {
case 0:
res.base = 0;
break;
case 1:
res.base = 1;
break;
case 2:
case 3:
res.base = 2;
break;
default:
fprintf(vvp_out, " %%inv %u, %u;\n", res.base, res.wid);
Slightly more efficient unary minus.
2003-10-01 19:44:20 +02:00
fprintf(vvp_out, " %%addi %u, 1, %u;\n",res.base,res.wid);
Generate code for unary minus (PR#272)
2001-09-29 06:37:44 +02:00
break;
}
break;
Implement the unary ! operator.
2001-04-01 23:47:29 +02:00
case '!':
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
res = draw_eval_expr(sub, STUFF_OK_XZ);
The ! expression returns 0 to x and z values.
2001-10-24 07:06:54 +02:00
if (res.wid > 1) {
/* a ! on a vector is implemented with a reduction
nor. Generate the result into the first bit of
the input vector and free the rest of the
vector. */
struct vector_info tmp;
assert(res.base >= 4);
tmp.base = res.base+1;
tmp.wid = res.wid - 1;
fprintf(vvp_out, " %%nor/r %u, %u, %u;\n",
res.base, res.base, res.wid);
clr_vector(tmp);
res.wid = 1;
Handle x case of unary ! properly.
2002-05-07 05:49:58 +02:00
} else switch (res.base) {
case 0:
res.base = 1;
break;
case 1:
res.base = 0;
break;
case 2:
case 3:
res.base = 2;
break;
default:
fprintf(vvp_out, " %%inv %u, 1;\n", res.base);
break;
The ! expression returns 0 to x and z values.
2001-10-24 07:06:54 +02:00
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* If the result needs to be bigger then the calculated
value, then write it into a padded vector. */
if (res.wid < wid) {
struct vector_info tmp;
tmp.base = allocate_vector(wid);
tmp.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
if (tmp.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits "
"to pad unary expression result.\n",
ivl_expr_file(exp), ivl_expr_lineno(exp), wid);
vvp_errors += 1;
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, res.base, res.wid);
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
fprintf(vvp_out, " %%movi %u, 0, %u;\n",
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
tmp.base+res.wid, tmp.wid-res.wid);
clr_vector(res);
res = tmp;
}
The ! expression returns 0 to x and z values.
2001-10-24 07:06:54 +02:00
break;
More behavioral unary reduction operators. (Stephan Boettcher)
2001-06-18 03:09:32 +02:00
case 'N':
case 'A':
case 'X':
inv = 1;
case '&':
case '|':
case '^':
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
res = draw_eval_expr(sub, 0);
Implement the unary ! operator.
2001-04-01 23:47:29 +02:00
if (res.wid > 1) {
struct vector_info tmp;
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* If the previous result is in the constant area
(and is a vector) then copy it out into some
temporary space. */
if (res.base < 4) {
tmp.base = allocate_vector(res.wid);
tmp.wid = res.wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, res.base, res.wid);
res = tmp;
}
Implement the unary ! operator.
2001-04-01 23:47:29 +02:00
tmp.base = res.base+1;
tmp.wid = res.wid - 1;
More behavioral unary reduction operators. (Stephan Boettcher)
2001-06-18 03:09:32 +02:00
fprintf(vvp_out, " %%%s/r %u, %u, %u;\n",
rop,
Implement the unary ! operator.
2001-04-01 23:47:29 +02:00
res.base, res.base, res.wid);
clr_vector(tmp);
res.wid = 1;
More behavioral unary reduction operators. (Stephan Boettcher)
2001-06-18 03:09:32 +02:00
} else if (inv) {
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
assert(res.base >= 4);
Implement the unary ! operator.
2001-04-01 23:47:29 +02:00
fprintf(vvp_out, " %%inv %u, 1;\n", res.base);
}
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
/* If the result needs to be bigger then the calculated
value, then write it into a passed vector. */
if (res.wid < wid) {
struct vector_info tmp;
tmp.base = allocate_vector(wid);
tmp.wid = wid;
Detect thread bit allocation failures Detect thread bit allocation failures and fail gracefully. Print an error message that points at the expression in question, and return with an error code so that the compiler exits with an error.
2008-04-16 06:51:03 +02:00
assert(res.base);
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
tmp.base, res.base, res.wid);
Better use of immediate operands. Clarify that operands are typically 32bits, and have the code generator make better use of this. Also improve the %movi implementation to work well with marger vectors. Add the %andi instruction to use immediate operands.
2008-05-28 02:51:28 +02:00
fprintf(vvp_out, " %%movi %u, 0, %u;\n",
Handle padding out of logical values.
2001-11-19 05:25:46 +01:00
tmp.base+res.wid, tmp.wid-res.wid);
clr_vector(res);
res = tmp;
}
Implement the unary ! operator.
2001-04-01 23:47:29 +02:00
break;
Add support for abs() in logic threads. Add the code generator code to handle the abs() function in signed logic. Handle some of the interesting special cases as well.
2008-05-05 07:00:01 +02:00
case 'm': /* abs() */
res = draw_eval_expr_wid(sub, wid, 0);
if (!ivl_expr_signed(sub))
break;
if (res.base == 0 || res.base == 2 || res.base == 3)
break;
/* Handle the special case of a -1 constant. Make the
result a 1. */
if (res.base == 1) {
res.base = allocate_vector(wid);
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%movi %d, 1, %u;\n",
Add support for abs() in logic threads. Add the code generator code to handle the abs() function in signed logic. Handle some of the interesting special cases as well.
2008-05-05 07:00:01 +02:00
res.base, res.wid);
break;
}
When evaluating a constant into an index make sure to clear bit 4. When evaluating an expression into an index register bit 4 is used to determine if the expression had any X/Z bits. In the case of a constant immediate value this can not happen so make sure the bit is cleared.
2008-09-18 01:18:17 +02:00
fprintf(vvp_out, " %%cmpi/s %d, 0, %u;\n", res.base, res.wid);
fprintf(vvp_out, " %%jmp/0xz T_%u.%u, 5;\n", thread_count, local_count);
fprintf(vvp_out, " %%inv %d, %u;\n", res.base, res.wid);
fprintf(vvp_out, " %%addi %d, 1, %u;\n", res.base, res.wid);
Add support for abs() in logic threads. Add the code generator code to handle the abs() function in signed logic. Handle some of the interesting special cases as well.
2008-05-05 07:00:01 +02:00
fprintf(vvp_out, "T_%u.%u ;\n", thread_count, local_count);
local_count += 1;
break;
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
default:
fprintf(stderr, "vvp error: unhandled unary: %c\n",
ivl_expr_opcode(exp));
assert(0);
}
Add thread expression lookaside map.
2002-09-27 18:33:34 +02:00
if (res.base >= 8)
save_expression_lookaside(res.base, exp, wid);
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
return res;
}
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
/*
* Sometimes we know ahead of time where we want the expression value
* to go. In that case, call this function. It will check to see if
* the expression can be preplaced, and if so it will evaluate it in
* place.
*/
static void draw_eval_expr_dest(ivl_expr_t exp, struct vector_info dest,
int stuff_ok_flag)
{
struct vector_info tmp;
switch (ivl_expr_type(exp)) {
case IVL_EX_SIGNAL:
Add %load/avp0 opcode and fix %load/vp0. This patch adds a new opcode %load/avp0 that is used to load a word from an array and add a value to it. %load/vp0 was changed/fixed to do the summation at the result width not the vector width. This allows small vectors to index large arrays with an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 03:22:46 +01:00
draw_signal_dest(exp, dest, -1, 0L);
Concatenation can evaluate sub-expressions in place.
2002-11-06 06:41:37 +01:00
return;
default:
break;
}
/* Fallback, is to draw the expression by width, and mov it to
the required dest. */
tmp = draw_eval_expr_wid(exp, dest.wid, stuff_ok_flag);
assert(tmp.wid == dest.wid);
fprintf(vvp_out, " %%mov %u, %u, %u;\n",
dest.base, tmp.base, dest.wid);
if (tmp.base >= 8)
save_expression_lookaside(tmp.base, exp, tmp.wid);
clr_vector(tmp);
}
Optimize ==1 when in context where x vs z doesnt matter.
2002-09-13 05:12:50 +02:00
struct vector_info draw_eval_expr_wid(ivl_expr_t exp, unsigned wid,
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
int stuff_ok_flag)
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
{
struct vector_info res;
switch (ivl_expr_type(exp)) {
default:
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
case IVL_EX_NONE:
Improve error message in tgt-vvp/eval_expr.c:draw_eval_expr_wid(). The IVL_EX_NONE type was not displaying any message and default did not use the new ivl_expr_{file,lineno} functions to get the source location. This patch remedies these problems.
2008-03-10 17:30:46 +01:00
fprintf(stderr, "%s:%u: vvp-tgt error: unhandled expr. type: "
"%u at %s:%d\n", ivl_expr_file(exp), ivl_expr_lineno(exp),
ivl_expr_type(exp), __FILE__, __LINE__);
NetESignal::dup_expr() was not passing the word_ information. The dup_expr() function for NetESignal was not copying the word_ expression. This would cause an individual array access to turn into an entire array access. The file and line information was also not being set correctly. An assert() in tgt-vvp/eval_expr.c was also replaced with an exit() since the appropriate information was already being printed.
2008-03-12 22:58:45 +01:00
exit(1);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
res.base = 0;
res.wid = 0;
break;
More detailed messages about unsupported things.
2001-08-03 19:06:10 +02:00
case IVL_EX_STRING:
Evaluate string expressions (Philip Blundell)
2001-10-18 18:41:49 +02:00
res = draw_string_expr(exp, wid);
More detailed messages about unsupported things.
2001-08-03 19:06:10 +02:00
break;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
case IVL_EX_BINARY:
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
res = draw_binary_expr(exp, wid, stuff_ok_flag);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
break;
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
case IVL_EX_CONCAT:
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
res = draw_concat_expr(exp, wid, stuff_ok_flag);
Generate code for + and concat expressions.
2001-03-31 04:00:44 +02:00
break;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
case IVL_EX_NUMBER:
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
res = draw_number_expr(exp, wid);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
break;
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
case IVL_EX_REALNUM:
res = draw_realnum_expr(exp, wid);
break;
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
case IVL_EX_SELECT:
Start handling pad of expressions in code generators.
2003-07-26 05:34:42 +02:00
if (ivl_expr_oper2(exp) == 0)
res = draw_pad_expr(exp, wid);
else
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
res = draw_select_expr(exp, wid, stuff_ok_flag);
Add support for bit select of parameters. This leads to a NetESelect node and the vvp code generator to support that.
2002-01-28 01:52:41 +01:00
break;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
case IVL_EX_SIGNAL:
More robust use of precalculated expressions, and Separate lookaside for written variables that can also be reused.
2005-09-17 03:01:00 +02:00
res = draw_signal_expr(exp, wid, stuff_ok_flag);
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
break;
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
Behavioral ternary operators for vvp.
2001-05-17 06:37:02 +02:00
case IVL_EX_TERNARY:
res = draw_ternary_expr(exp, wid);
break;
Initial support for system functions.
2001-05-20 03:02:55 +02:00
case IVL_EX_SFUNC:
res = draw_sfunc_expr(exp, wid);
break;
Generate vvp code for functions with ports.
2001-04-06 04:28:02 +02:00
case IVL_EX_UFUNC:
res = draw_ufunc_expr(exp, wid);
break;
Add unary ~ operator to tgt-vvp.
2001-03-29 04:52:39 +02:00
case IVL_EX_UNARY:
res = draw_unary_expr(exp, wid);
break;
Geneate code for conditional statements.
2001-03-22 06:06:21 +01:00
}
return res;
}
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
{
Allow results in register bits 47 in certain cases.
2002-09-24 06:20:32 +02:00
return draw_eval_expr_wid(exp, ivl_expr_width(exp), stuff_ok_flag);
Assure that operands are the correct width.
2001-03-23 02:10:24 +01:00
}