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5,961 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

45 Commits

Author SHA1 Message Date
tklam 9545b79e0e support primitive gates with names in Verilog netlist 2025-05-12 10:20:13 -04:00
Alan Mishchenko 24d9ce6baf Special case in Verilog parser. 2019-12-06 02:19:50 -08:00
Alan Mishchenko ee1bd8f0be Fixing some update gcc. 2019-07-24 11:44:28 +07:00
Alan Mishchenko 68467cfff7 Fixed a typo in variable names. 2015-02-07 22:29:14 -08:00
Alan Mishchenko 259d53ca3e Simplifying AIG with barrier buffers. 2014-12-19 22:02:28 -08:00
Alan Mishchenko 62bc45d1fb Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, such as [7:7], which seems to help in some cases. 2014-08-02 17:00:24 -07:00
Alan Mishchenko c5b620b9bf Fixed printout of in the hierarchy log file. 2014-06-05 11:17:32 -07:00
Alan Mishchenko 3abc3fb4ff Fixed printout of in the hierarchy log file. 2014-06-05 10:57:04 -07:00
Alan Mishchenko 54d3c1ab42 Fixed printout of in the hierarchy log file. 2014-06-05 10:46:43 -07:00
Alan Mishchenko 7c8e1b8de6 Fixed printout of in the hierarchy log file. 2014-06-05 10:45:59 -07:00
Alan Mishchenko 46ab68ba17 Cleanup and bug fixing in hierarchy handling. 2014-04-09 12:51:08 -07:00
Alan Mishchenko b94b810297 Renamed Abc_Lib_t into Abc_Des_t and removed some dead code. 2014-04-09 10:16:07 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko 71bdfae941 Replacing 'st_table' by 'st__table' to resolve linker problems. 2012-09-29 17:11:03 -04:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00
Alan Mishchenko 723f85ef1b Extending Liberty parser to handle multi-output cells. 2012-09-19 20:21:27 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko 1c33107cbb Updating project settings to have simpler include paths. 2012-07-07 20:14:12 -07:00
Alan Mishchenko 97856d021a Silencing some of the gcc warnings. 2012-02-16 23:40:23 -08:00
Alan Mishchenko 8014f25f6d Major restructuring of the code. 2012-01-21 04:30:10 -08:00
Alan Mishchenko ac7e665bf6 Bug fixes in the Verilog parser. 2012-01-14 22:21:23 -08:00
Alan Mishchenko 6c01e8b9f0 Fixed a number of small bugs and memory leaks. 2011-03-27 14:17:12 -07:00
Alan Mishchenko 6130e39b18 initial commit of public abc 2010-11-01 01:35:04 -07:00
Alan Mishchenko df6fdd1dff Version abc90408 2009-04-08 08:01:00 -07:00
Alan Mishchenko 23fd11037a Version abc90329 2009-03-29 08:01:00 -07:00
Alan Mishchenko 32314347ba Version abc90310 2009-03-10 08:01:00 -07:00
Alan Mishchenko 0871bffae3 Version abc90215 2009-02-15 08:01:00 -08:00
Alan Mishchenko 303baf27cf Version abc80702 2008-07-02 08:01:00 -07:00
Alan Mishchenko 0c6505a26a Version abc80130_2 2008-01-30 20:01:00 -08:00
Alan Mishchenko 4d30a1e4f1 Version abc80130 2008-01-30 08:01:00 -08:00
Alan Mishchenko 369f008e69 Version abc71130 2007-11-30 08:01:00 -08:00
Alan Mishchenko 4812c90424 Version abc71001 2007-10-01 08:01:00 -07:00
Alan Mishchenko e54d969161 Version abc70930 2007-09-30 08:01:00 -07:00
Alan Mishchenko d47752011d Version abc70608 2007-06-08 08:01:00 -07:00
Alan Mishchenko 00dc0f3daa Version abc70406 2007-04-06 08:01:00 -07:00
Alan Mishchenko 4da784c049 Version abc70328 2007-03-28 08:01:00 -07:00
Alan Mishchenko 2696cf05e5 Version abc70313 2007-03-13 08:01:00 -07:00
Alan Mishchenko 93c05287f0 Version abc70302 2007-03-02 08:01:00 -08:00
Alan Mishchenko 81fae91a95 Version abc70225 2007-02-25 08:01:00 -08:00
Alan Mishchenko fb51057e4a Version abc70219 2007-02-19 08:01:00 -08:00
Alan Mishchenko 607c253cd2 Version abc70216 2007-02-16 08:01:00 -08:00
Alan Mishchenko 5f3e4c0fe2 Version abc70211 2007-02-11 08:01:00 -08:00
Alan Mishchenko b9e0c95b69 Version abc70209 2007-02-09 08:01:00 -08:00
Alan Mishchenko 6ad22b4d3b Version abc61122 2006-11-22 08:01:00 -08:00