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abc
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Version abc61122

This commit is contained in:
Alan Mishchenko 2006-11-22 08:01:00 -08:00
parent da5e0785df
commit 6ad22b4d3b
174 changed files with 6370 additions and 11232 deletions
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8
Makefile
View File

@ -6,13 +6,13 @@ CP := cp
PROG := abc
MODULES := src/base/abc src/base/abci src/base/cmd src/base/io src/base/main \
MODULES := src/base/abc src/base/abci src/base/cmd src/base/io src/base/main src/base/ver \
src/aig/ivy src/aig/hop src/aig/rwt src/aig/deco src/mem/deco src/aig/ec \
src/bdd/cudd src/bdd/dsd src/bdd/epd src/bdd/mtr src/bdd/parse src/bdd/reo \
src/map/fpga src/map/pga src/map/mapper src/map/mio src/map/super \
src/map/fpga src/map/pga src/map/mapper src/map/mio src/map/super src/map/if \
src/misc/extra src/misc/mvc src/misc/st src/misc/util src/misc/espresso src/misc/nm src/misc/vec src/misc/hash \
src/opt/cut src/opt/dec src/opt/fxu src/opt/rwr src/opt/sim src/opt/ret \
src/sat/asat src/sat/bsat src/sat/csat src/sat/msat src/sat/fraig \
src/temp/ivy src/temp/aig src/temp/rwt src/temp/deco src/temp/mem src/temp/ver
src/sat/asat src/sat/bsat src/sat/csat src/sat/msat src/sat/fraig
default: $(PROG)

506
abc.dsp
View File

@ -42,7 +42,7 @@ RSC=rc.exe
# PROP Ignore_Export_Lib 0
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\temp\ivy" /I "src\temp\esop" /I "src\temp\rwt" /I "src\temp\deco" /I "src\temp\mem" /I "src\temp\aig" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /FR /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\if" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\aig\ivy" /I "src\aig\hop" /I "src\aig\rwt" /I "src\aig\deco" /I "src\aig\mem" /I "src\temp\esop" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe
@ -66,7 +66,7 @@ LINK32=link.exe
# PROP Ignore_Export_Lib 0
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\temp\ivy" /I "src\temp\esop" /I "src\temp\rwt" /I "src\temp\deco" /I "src\temp\mem" /I "src\temp\aig" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /FR /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\if" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\aig\ivy" /I "src\aig\hop" /I "src\aig\rwt" /I "src\aig\deco" /I "src\aig\mem" /I "src\temp\esop" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /FR /YX /FD /GZ /c
# SUBTRACT CPP /X
# ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG"
@ -238,6 +238,10 @@ SOURCE=.\src\base\abci\abcGen.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcIf.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcIvy.c
# End Source File
# Begin Source File
@ -270,10 +274,6 @@ SOURCE=.\src\base\abci\abcOrder.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcPga.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcPrint.c
# End Source File
# Begin Source File
@ -505,6 +505,226 @@ SOURCE=.\src\base\main\mainInt.h
SOURCE=.\src\base\main\mainUtils.c
# End Source File
# End Group
# Begin Group "ver"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\base\ver\ver.h
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verCore.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verFormula.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verParse.c
# End Source File
# Begin Source File
SOURCE=.\src\base\ver\verStream.c
# End Source File
# End Group
# End Group
# Begin Group "aig"
# PROP Default_Filter ""
# Begin Group "hop"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\hop\hop.h
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopBalance.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopCheck.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopDfs.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopMan.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopMem.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopObj.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopOper.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopTable.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\hop\hopUtil.c
# End Source File
# End Group
# Begin Group "ivy"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\ivy\ivy.h
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyBalance.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyCanon.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyCheck.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyCut.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyCutTrav.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyDfs.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyDsd.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyFanout.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyFastMap.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyFpga.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyFraig.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyHaig.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyIsop.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyMan.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyMem.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyMulti.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyObj.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyOper.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyResyn.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyRwr.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivySeq.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyShow.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyTable.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\ivy\ivyUtil.c
# End Source File
# End Group
# Begin Group "rwt"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\rwt\rwt.h
# End Source File
# Begin Source File
SOURCE=.\src\aig\rwt\rwtDec.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\rwt\rwtMan.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\rwt\rwtUtil.c
# End Source File
# End Group
# Begin Group "deco"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\deco\deco.h
# End Source File
# End Group
# Begin Group "mem"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\aig\mem\mem.c
# End Source File
# Begin Source File
SOURCE=.\src\aig\mem\mem.h
# End Source File
# End Group
# Begin Group "ec"
# PROP Default_Filter ""
# End Group
# End Group
# Begin Group "bdd"
@ -1364,6 +1584,10 @@ SOURCE=.\src\opt\ret\retInit.c
SOURCE=.\src\opt\ret\retInt.h
# End Source File
# Begin Source File
SOURCE=.\src\opt\ret\retLvalue.c
# End Source File
# End Group
# End Group
# Begin Group "map"
@ -1577,32 +1801,32 @@ SOURCE=.\src\map\super\superInt.h
SOURCE=.\src\map\super\superWrite.c
# End Source File
# End Group
# Begin Group "pga"
# Begin Group "if"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\map\pga\pga.h
SOURCE=.\src\map\if\if.h
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaCore.c
SOURCE=.\src\map\if\ifCore.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaInt.h
SOURCE=.\src\map\if\ifCut.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaMan.c
SOURCE=.\src\map\if\ifMan.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaMatch.c
SOURCE=.\src\map\if\ifMap.c
# End Source File
# Begin Source File
SOURCE=.\src\map\pga\pgaUtil.c
SOURCE=.\src\map\if\ifUtil.c
# End Source File
# End Group
# End Group
@ -1774,6 +1998,10 @@ SOURCE=.\src\misc\vec\vec.h
# End Source File
# Begin Source File
SOURCE=.\src\misc\vec\vecAtt.h
# End Source File
# Begin Source File
SOURCE=.\src\misc\vec\vecFlt.h
# End Source File
# Begin Source File
@ -2025,258 +2253,6 @@ SOURCE=.\src\misc\hash\hashPtr.h
# Begin Group "temp"
# PROP Default_Filter ""
# Begin Group "ivy"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\ivy\ivy.h
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyBalance.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyCanon.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyCheck.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyCut.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyCutTrav.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyDfs.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyDsd.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyFanout.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyFastMap.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyFraig.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyHaig.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyIsop.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyMan.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyMem.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyMulti.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyObj.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyOper.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyResyn.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyRwr.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivySeq.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyShow.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyTable.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ivy\ivyUtil.c
# End Source File
# End Group
# Begin Group "player"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\player\player.h
# End Source File
# Begin Source File
SOURCE=.\src\temp\player\playerCore.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\player\playerMan.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\player\playerToAbc.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\player\playerUtil.c
# End Source File
# End Group
# Begin Group "esop"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\esop\esop.h
# End Source File
# Begin Source File
SOURCE=.\src\temp\esop\esopMan.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\esop\esopMin.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\esop\esopUtil.c
# End Source File
# End Group
# Begin Group "rwt"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\rwt\rwt.h
# End Source File
# Begin Source File
SOURCE=.\src\temp\rwt\rwtDec.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\rwt\rwtMan.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\rwt\rwtUtil.c
# End Source File
# End Group
# Begin Group "deco"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\deco\deco.h
# End Source File
# End Group
# Begin Group "mem"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\mem\mem.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\mem\mem.h
# End Source File
# End Group
# Begin Group "ver"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\ver\ver.h
# End Source File
# Begin Source File
SOURCE=.\src\temp\ver\verCore.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ver\verFormula.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ver\verParse.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\ver\verStream.c
# End Source File
# End Group
# Begin Group "aig"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\temp\aig\aig.h
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigBalance.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigCheck.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigDfs.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigMan.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigMem.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigObj.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigOper.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigTable.c
# End Source File
# Begin Source File
SOURCE=.\src\temp\aig\aigUtil.c
# End Source File
# End Group
# End Group
# End Group
# Begin Group "Header Files"

3
abc.rc
View File

@ -43,6 +43,9 @@ alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias r3 retime -M 3
alias r3f retime -M 3 -f
alias r3b retime -M 3 -b
alias ren renode
alias rl read_blif
alias rb read_bench

BIN
src/aig/aig-alan.tar.gz Normal file
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Binary file not shown.

0
src/temp/deco/deco.h → src/aig/deco/deco.h
View File

0
src/temp/deco/module.make → src/aig/deco/module.make
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1
src/aig/ec/module.make Normal file
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@ -0,0 +1 @@
SRC +=

2
src/temp/aig/cudd2.c → src/aig/hop/cudd2.c
View File

@ -18,7 +18,7 @@
***********************************************************************/
#include "aig.h"
#include "hop.h"
#include "st.h"
////////////////////////////////////////////////////////////////////////

0
src/temp/aig/cudd2.h → src/aig/hop/cudd2.h
View File

321
src/aig/hop/hop.h Normal file
View File

@ -0,0 +1,321 @@
/**CFile****************************************************************
FileName [hop.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Minimalistic And-Inverter Graph package.]
Synopsis [External declarations.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: hop.h,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#ifndef __HOP_H__
#define __HOP_H__
#ifdef __cplusplus
extern "C" {
#endif
////////////////////////////////////////////////////////////////////////
/// INCLUDES ///
////////////////////////////////////////////////////////////////////////
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <time.h>
#include "vec.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// BASIC TYPES ///
////////////////////////////////////////////////////////////////////////
typedef struct Hop_Man_t_ Hop_Man_t;
typedef struct Hop_Obj_t_ Hop_Obj_t;
typedef int Hop_Edge_t;
// object types
typedef enum {
AIG_NONE, // 0: non-existent object
AIG_CONST1, // 1: constant 1
AIG_PI, // 2: primary input
AIG_PO, // 3: primary output
AIG_AND, // 4: AND node
AIG_EXOR, // 5: EXOR node
AIG_VOID // 6: unused object
} Hop_Type_t;
// the AIG node
struct Hop_Obj_t_ // 4 words
{
void * pData; // misc
Hop_Obj_t * pFanin0; // fanin
Hop_Obj_t * pFanin1; // fanin
unsigned long Type : 3; // object type
unsigned long fPhase : 1; // value under 000...0 pattern
unsigned long fMarkA : 1; // multipurpose mask
unsigned long fMarkB : 1; // multipurpose mask
unsigned long nRefs : 26; // reference count (level)
};
// the AIG manager
struct Hop_Man_t_
{
// AIG nodes
Vec_Ptr_t * vPis; // the array of PIs
Vec_Ptr_t * vPos; // the array of POs
Hop_Obj_t * pConst1; // the constant 1 node
Hop_Obj_t Ghost; // the ghost node
// AIG node counters
int nObjs[AIG_VOID];// the number of objects by type
int nCreated; // the number of created objects
int nDeleted; // the number of deleted objects
// stuctural hash table
Hop_Obj_t ** pTable; // structural hash table
int nTableSize; // structural hash table size
// various data members
void * pData; // the temporary data
int nTravIds; // the current traversal ID
int fRefCount; // enables reference counting
int fCatchExor; // enables EXOR nodes
// memory management
Vec_Ptr_t * vChunks; // allocated memory pieces
Vec_Ptr_t * vPages; // memory pages used by nodes
Hop_Obj_t * pListFree; // the list of free nodes
// timing statistics
int time1;
int time2;
};
////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
#define AIG_MIN(a,b) (((a) < (b))? (a) : (b))
#define AIG_MAX(a,b) (((a) > (b))? (a) : (b))
#ifndef PRT
#define PRT(a,t) printf("%s = ", (a)); printf("%6.2f sec\n", (float)(t)/(float)(CLOCKS_PER_SEC))
#endif
static inline int Hop_BitWordNum( int nBits ) { return (nBits>>5) + ((nBits&31) > 0); }
static inline int Hop_TruthWordNum( int nVars ) { return nVars <= 5 ? 1 : (1 << (nVars - 5)); }
static inline int Hop_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (1<<((i) & 31))) > 0; }
static inline void Hop_InfoSetBit( unsigned * p, int i ) { p[(i)>>5] |= (1<<((i) & 31)); }
static inline void Hop_InfoXorBit( unsigned * p, int i ) { p[(i)>>5] ^= (1<<((i) & 31)); }
static inline Hop_Obj_t * Hop_Regular( Hop_Obj_t * p ) { return (Hop_Obj_t *)((unsigned long)(p) & ~01); }
static inline Hop_Obj_t * Hop_Not( Hop_Obj_t * p ) { return (Hop_Obj_t *)((unsigned long)(p) ^ 01); }
static inline Hop_Obj_t * Hop_NotCond( Hop_Obj_t * p, int c ) { return (Hop_Obj_t *)((unsigned long)(p) ^ (c)); }
static inline int Hop_IsComplement( Hop_Obj_t * p ) { return (int )(((unsigned long)p) & 01); }
static inline Hop_Obj_t * Hop_ManConst0( Hop_Man_t * p ) { return Hop_Not(p->pConst1); }
static inline Hop_Obj_t * Hop_ManConst1( Hop_Man_t * p ) { return p->pConst1; }
static inline Hop_Obj_t * Hop_ManGhost( Hop_Man_t * p ) { return &p->Ghost; }
static inline Hop_Obj_t * Hop_ManPi( Hop_Man_t * p, int i ) { return (Hop_Obj_t *)Vec_PtrEntry(p->vPis, i); }
static inline Hop_Edge_t Hop_EdgeCreate( int Id, int fCompl ) { return (Id << 1) | fCompl; }
static inline int Hop_EdgeId( Hop_Edge_t Edge ) { return Edge >> 1; }
static inline int Hop_EdgeIsComplement( Hop_Edge_t Edge ) { return Edge & 1; }
static inline Hop_Edge_t Hop_EdgeRegular( Hop_Edge_t Edge ) { return (Edge >> 1) << 1; }
static inline Hop_Edge_t Hop_EdgeNot( Hop_Edge_t Edge ) { return Edge ^ 1; }
static inline Hop_Edge_t Hop_EdgeNotCond( Hop_Edge_t Edge, int fCond ) { return Edge ^ fCond; }
static inline int Hop_ManPiNum( Hop_Man_t * p ) { return p->nObjs[AIG_PI]; }
static inline int Hop_ManPoNum( Hop_Man_t * p ) { return p->nObjs[AIG_PO]; }
static inline int Hop_ManAndNum( Hop_Man_t * p ) { return p->nObjs[AIG_AND]; }
static inline int Hop_ManExorNum( Hop_Man_t * p ) { return p->nObjs[AIG_EXOR]; }
static inline int Hop_ManNodeNum( Hop_Man_t * p ) { return p->nObjs[AIG_AND]+p->nObjs[AIG_EXOR];}
static inline int Hop_ManGetCost( Hop_Man_t * p ) { return p->nObjs[AIG_AND]+3*p->nObjs[AIG_EXOR]; }
static inline int Hop_ManObjNum( Hop_Man_t * p ) { return p->nCreated - p->nDeleted; }
static inline Hop_Type_t Hop_ObjType( Hop_Obj_t * pObj ) { return pObj->Type; }
static inline int Hop_ObjIsNone( Hop_Obj_t * pObj ) { return pObj->Type == AIG_NONE; }
static inline int Hop_ObjIsConst1( Hop_Obj_t * pObj ) { assert(!Hop_IsComplement(pObj)); return pObj->Type == AIG_CONST1; }
static inline int Hop_ObjIsPi( Hop_Obj_t * pObj ) { return pObj->Type == AIG_PI; }
static inline int Hop_ObjIsPo( Hop_Obj_t * pObj ) { return pObj->Type == AIG_PO; }
static inline int Hop_ObjIsAnd( Hop_Obj_t * pObj ) { return pObj->Type == AIG_AND; }
static inline int Hop_ObjIsExor( Hop_Obj_t * pObj ) { return pObj->Type == AIG_EXOR; }
static inline int Hop_ObjIsNode( Hop_Obj_t * pObj ) { return pObj->Type == AIG_AND || pObj->Type == AIG_EXOR; }
static inline int Hop_ObjIsTerm( Hop_Obj_t * pObj ) { return pObj->Type == AIG_PI || pObj->Type == AIG_PO || pObj->Type == AIG_CONST1; }
static inline int Hop_ObjIsHash( Hop_Obj_t * pObj ) { return pObj->Type == AIG_AND || pObj->Type == AIG_EXOR; }
static inline int Hop_ObjIsMarkA( Hop_Obj_t * pObj ) { return pObj->fMarkA; }
static inline void Hop_ObjSetMarkA( Hop_Obj_t * pObj ) { pObj->fMarkA = 1; }
static inline void Hop_ObjClearMarkA( Hop_Obj_t * pObj ) { pObj->fMarkA = 0; }
static inline void Hop_ObjSetTravId( Hop_Obj_t * pObj, int TravId ) { pObj->pData = (void *)TravId; }
static inline void Hop_ObjSetTravIdCurrent( Hop_Man_t * p, Hop_Obj_t * pObj ) { pObj->pData = (void *)p->nTravIds; }
static inline void Hop_ObjSetTravIdPrevious( Hop_Man_t * p, Hop_Obj_t * pObj ) { pObj->pData = (void *)(p->nTravIds - 1); }
static inline int Hop_ObjIsTravIdCurrent( Hop_Man_t * p, Hop_Obj_t * pObj ) { return (int )((int)pObj->pData == p->nTravIds); }
static inline int Hop_ObjIsTravIdPrevious( Hop_Man_t * p, Hop_Obj_t * pObj ) { return (int )((int)pObj->pData == p->nTravIds - 1); }
static inline int Hop_ObjTravId( Hop_Obj_t * pObj ) { return (int)pObj->pData; }
static inline int Hop_ObjPhase( Hop_Obj_t * pObj ) { return pObj->fPhase; }
static inline int Hop_ObjRefs( Hop_Obj_t * pObj ) { return pObj->nRefs; }
static inline void Hop_ObjRef( Hop_Obj_t * pObj ) { pObj->nRefs++; }
static inline void Hop_ObjDeref( Hop_Obj_t * pObj ) { assert( pObj->nRefs > 0 ); pObj->nRefs--; }
static inline void Hop_ObjClearRef( Hop_Obj_t * pObj ) { pObj->nRefs = 0; }
static inline int Hop_ObjFaninC0( Hop_Obj_t * pObj ) { return Hop_IsComplement(pObj->pFanin0); }
static inline int Hop_ObjFaninC1( Hop_Obj_t * pObj ) { return Hop_IsComplement(pObj->pFanin1); }
static inline Hop_Obj_t * Hop_ObjFanin0( Hop_Obj_t * pObj ) { return Hop_Regular(pObj->pFanin0); }
static inline Hop_Obj_t * Hop_ObjFanin1( Hop_Obj_t * pObj ) { return Hop_Regular(pObj->pFanin1); }
static inline Hop_Obj_t * Hop_ObjChild0( Hop_Obj_t * pObj ) { return pObj->pFanin0; }
static inline Hop_Obj_t * Hop_ObjChild1( Hop_Obj_t * pObj ) { return pObj->pFanin1; }
static inline Hop_Obj_t * Hop_ObjChild0Copy( Hop_Obj_t * pObj ) { assert( !Hop_IsComplement(pObj) ); return Hop_ObjFanin0(pObj)? Hop_NotCond(Hop_ObjFanin0(pObj)->pData, Hop_ObjFaninC0(pObj)) : NULL; }
static inline Hop_Obj_t * Hop_ObjChild1Copy( Hop_Obj_t * pObj ) { assert( !Hop_IsComplement(pObj) ); return Hop_ObjFanin1(pObj)? Hop_NotCond(Hop_ObjFanin1(pObj)->pData, Hop_ObjFaninC1(pObj)) : NULL; }
static inline int Hop_ObjLevel( Hop_Obj_t * pObj ) { return pObj->nRefs; }
static inline int Hop_ObjLevelNew( Hop_Obj_t * pObj ) { return 1 + Hop_ObjIsExor(pObj) + AIG_MAX(Hop_ObjFanin0(pObj)->nRefs, Hop_ObjFanin1(pObj)->nRefs); }
static inline void Hop_ObjClean( Hop_Obj_t * pObj ) { memset( pObj, 0, sizeof(Hop_Obj_t) ); }
static inline int Hop_ObjWhatFanin( Hop_Obj_t * pObj, Hop_Obj_t * pFanin )
{
if ( Hop_ObjFanin0(pObj) == pFanin ) return 0;
if ( Hop_ObjFanin1(pObj) == pFanin ) return 1;
assert(0); return -1;
}
static inline int Hop_ObjFanoutC( Hop_Obj_t * pObj, Hop_Obj_t * pFanout )
{
if ( Hop_ObjFanin0(pFanout) == pObj ) return Hop_ObjFaninC0(pObj);
if ( Hop_ObjFanin1(pFanout) == pObj ) return Hop_ObjFaninC1(pObj);
assert(0); return -1;
}
// create the ghost of the new node
static inline Hop_Obj_t * Hop_ObjCreateGhost( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1, Hop_Type_t Type )
{
Hop_Obj_t * pGhost;
assert( Type != AIG_AND || !Hop_ObjIsConst1(Hop_Regular(p0)) );
assert( p1 == NULL || !Hop_ObjIsConst1(Hop_Regular(p1)) );
assert( Type == AIG_PI || Hop_Regular(p0) != Hop_Regular(p1) );
pGhost = Hop_ManGhost(p);
pGhost->Type = Type;
pGhost->pFanin0 = p0 < p1? p0 : p1;
pGhost->pFanin1 = p0 < p1? p1 : p0;
return pGhost;
}
// internal memory manager
static inline Hop_Obj_t * Hop_ManFetchMemory( Hop_Man_t * p )
{
extern void Hop_ManAddMemory( Hop_Man_t * p );
Hop_Obj_t * pTemp;
if ( p->pListFree == NULL )
Hop_ManAddMemory( p );
pTemp = p->pListFree;
p->pListFree = *((Hop_Obj_t **)pTemp);
memset( pTemp, 0, sizeof(Hop_Obj_t) );
return pTemp;
}
static inline void Hop_ManRecycleMemory( Hop_Man_t * p, Hop_Obj_t * pEntry )
{
pEntry->Type = AIG_NONE; // distinquishes dead node from live node
*((Hop_Obj_t **)pEntry) = p->pListFree;
p->pListFree = pEntry;
}
////////////////////////////////////////////////////////////////////////
/// ITERATORS ///
////////////////////////////////////////////////////////////////////////
// iterator over the primary inputs
#define Hop_ManForEachPi( p, pObj, i ) \
Vec_PtrForEachEntry( p->vPis, pObj, i )
// iterator over the primary outputs
#define Hop_ManForEachPo( p, pObj, i ) \
Vec_PtrForEachEntry( p->vPos, pObj, i )
// iterator over all objects, including those currently not used
#define Hop_ManForEachNode( p, pObj, i ) \
for ( i = 0; i < p->nTableSize; i++ ) \
if ( ((pObj) = p->pTable[i]) == NULL ) {} else
////////////////////////////////////////////////////////////////////////
/// FUNCTION DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/*=== aigBalance.c ========================================================*/
extern Hop_Man_t * Hop_ManBalance( Hop_Man_t * p, int fUpdateLevel );
extern Hop_Obj_t * Hop_NodeBalanceBuildSuper( Hop_Man_t * p, Vec_Ptr_t * vSuper, Hop_Type_t Type, int fUpdateLevel );
/*=== aigCheck.c ========================================================*/
extern int Hop_ManCheck( Hop_Man_t * p );
/*=== aigDfs.c ==========================================================*/
extern Vec_Ptr_t * Hop_ManDfs( Hop_Man_t * p );
extern Vec_Ptr_t * Hop_ManDfsNode( Hop_Man_t * p, Hop_Obj_t * pNode );
extern int Hop_ManCountLevels( Hop_Man_t * p );
extern void Hop_ManCreateRefs( Hop_Man_t * p );
extern int Hop_DagSize( Hop_Obj_t * pObj );
extern void Hop_ConeUnmark_rec( Hop_Obj_t * pObj );
extern Hop_Obj_t * Hop_Transfer( Hop_Man_t * pSour, Hop_Man_t * pDest, Hop_Obj_t * pObj, int nVars );
extern Hop_Obj_t * Hop_Compose( Hop_Man_t * p, Hop_Obj_t * pRoot, Hop_Obj_t * pFunc, int iVar );
/*=== aigMan.c ==========================================================*/
extern Hop_Man_t * Hop_ManStart();
extern Hop_Man_t * Hop_ManDup( Hop_Man_t * p );
extern void Hop_ManStop( Hop_Man_t * p );
extern int Hop_ManCleanup( Hop_Man_t * p );
extern void Hop_ManPrintStats( Hop_Man_t * p );
/*=== aigMem.c ==========================================================*/
extern void Hop_ManStartMemory( Hop_Man_t * p );
extern void Hop_ManStopMemory( Hop_Man_t * p );
/*=== aigObj.c ==========================================================*/
extern Hop_Obj_t * Hop_ObjCreatePi( Hop_Man_t * p );
extern Hop_Obj_t * Hop_ObjCreatePo( Hop_Man_t * p, Hop_Obj_t * pDriver );
extern Hop_Obj_t * Hop_ObjCreate( Hop_Man_t * p, Hop_Obj_t * pGhost );
extern void Hop_ObjConnect( Hop_Man_t * p, Hop_Obj_t * pObj, Hop_Obj_t * pFan0, Hop_Obj_t * pFan1 );
extern void Hop_ObjDisconnect( Hop_Man_t * p, Hop_Obj_t * pObj );
extern void Hop_ObjDelete( Hop_Man_t * p, Hop_Obj_t * pObj );
extern void Hop_ObjDelete_rec( Hop_Man_t * p, Hop_Obj_t * pObj );
/*=== aigOper.c =========================================================*/
extern Hop_Obj_t * Hop_IthVar( Hop_Man_t * p, int i );
extern Hop_Obj_t * Hop_Oper( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1, Hop_Type_t Type );
extern Hop_Obj_t * Hop_And( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1 );
extern Hop_Obj_t * Hop_Or( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1 );
extern Hop_Obj_t * Hop_Exor( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1 );
extern Hop_Obj_t * Hop_Mux( Hop_Man_t * p, Hop_Obj_t * pC, Hop_Obj_t * p1, Hop_Obj_t * p0 );
extern Hop_Obj_t * Hop_Maj( Hop_Man_t * p, Hop_Obj_t * pA, Hop_Obj_t * pB, Hop_Obj_t * pC );
extern Hop_Obj_t * Hop_Miter( Hop_Man_t * p, Vec_Ptr_t * vPairs );
extern Hop_Obj_t * Hop_CreateAnd( Hop_Man_t * p, int nVars );
extern Hop_Obj_t * Hop_CreateOr( Hop_Man_t * p, int nVars );
extern Hop_Obj_t * Hop_CreateExor( Hop_Man_t * p, int nVars );
/*=== aigTable.c ========================================================*/
extern Hop_Obj_t * Hop_TableLookup( Hop_Man_t * p, Hop_Obj_t * pGhost );
extern void Hop_TableInsert( Hop_Man_t * p, Hop_Obj_t * pObj );
extern void Hop_TableDelete( Hop_Man_t * p, Hop_Obj_t * pObj );
extern int Hop_TableCountEntries( Hop_Man_t * p );
extern void Hop_TableProfile( Hop_Man_t * p );
/*=== aigUtil.c =========================================================*/
extern void Hop_ManIncrementTravId( Hop_Man_t * p );
extern void Hop_ManCleanData( Hop_Man_t * p );
extern void Hop_ObjCollectMulti( Hop_Obj_t * pFunc, Vec_Ptr_t * vSuper );
extern int Hop_ObjIsMuxType( Hop_Obj_t * pObj );
extern int Hop_ObjRecognizeExor( Hop_Obj_t * pObj, Hop_Obj_t ** ppFan0, Hop_Obj_t ** ppFan1 );
extern Hop_Obj_t * Hop_ObjRecognizeMux( Hop_Obj_t * pObj, Hop_Obj_t ** ppObjT, Hop_Obj_t ** ppObjE );
extern void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level );
extern void Hop_ObjPrintVerbose( Hop_Obj_t * pObj, int fHaig );
extern void Hop_ManPrintVerbose( Hop_Man_t * p, int fHaig );
extern void Hop_ManDumpBlif( Hop_Man_t * p, char * pFileName );
#ifdef __cplusplus
}
#endif
#endif
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

134
src/temp/aig/aigBalance.c → src/aig/hop/hopBalance.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigBalance.c]
FileName [hopBalance.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,21 +14,21 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigBalance.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopBalance.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static Aig_Obj_t * Aig_NodeBalance_rec( Aig_Man_t * pNew, Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level, int fUpdateLevel );
static Vec_Ptr_t * Aig_NodeBalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level );
static int Aig_NodeBalanceFindLeft( Vec_Ptr_t * vSuper );
static void Aig_NodeBalancePermute( Aig_Man_t * p, Vec_Ptr_t * vSuper, int LeftBound, int fExor );
static void Aig_NodeBalancePushUniqueOrderByLevel( Vec_Ptr_t * vStore, Aig_Obj_t * pObj );
static Hop_Obj_t * Hop_NodeBalance_rec( Hop_Man_t * pNew, Hop_Obj_t * pObj, Vec_Vec_t * vStore, int Level, int fUpdateLevel );
static Vec_Ptr_t * Hop_NodeBalanceCone( Hop_Obj_t * pObj, Vec_Vec_t * vStore, int Level );
static int Hop_NodeBalanceFindLeft( Vec_Ptr_t * vSuper );
static void Hop_NodeBalancePermute( Hop_Man_t * p, Vec_Ptr_t * vSuper, int LeftBound, int fExor );
static void Hop_NodeBalancePushUniqueOrderByLevel( Vec_Ptr_t * vStore, Hop_Obj_t * pObj );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@ -45,35 +45,35 @@ static void Aig_NodeBalancePushUniqueOrderByLevel( Vec_Ptr_t * vStore, Ai
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManBalance( Aig_Man_t * p, int fUpdateLevel )
Hop_Man_t * Hop_ManBalance( Hop_Man_t * p, int fUpdateLevel )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj, * pObjNew;
Hop_Man_t * pNew;
Hop_Obj_t * pObj, * pObjNew;
Vec_Vec_t * vStore;
int i;
// create the new manager
pNew = Aig_ManStart();
pNew = Hop_ManStart();
pNew->fRefCount = 0;
// map the PI nodes
Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p, pObj, i )
pObj->pData = Aig_ObjCreatePi(pNew);
Hop_ManCleanData( p );
Hop_ManConst1(p)->pData = Hop_ManConst1(pNew);
Hop_ManForEachPi( p, pObj, i )
pObj->pData = Hop_ObjCreatePi(pNew);
// balance the AIG
vStore = Vec_VecAlloc( 50 );
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
{
pObjNew = Aig_NodeBalance_rec( pNew, Aig_ObjFanin0(pObj), vStore, 0, fUpdateLevel );
Aig_ObjCreatePo( pNew, Aig_NotCond( pObjNew, Aig_ObjFaninC0(pObj) ) );
pObjNew = Hop_NodeBalance_rec( pNew, Hop_ObjFanin0(pObj), vStore, 0, fUpdateLevel );
Hop_ObjCreatePo( pNew, Hop_NotCond( pObjNew, Hop_ObjFaninC0(pObj) ) );
}
Vec_VecFree( vStore );
// remove dangling nodes
// Aig_ManCreateRefs( pNew );
// if ( i = Aig_ManCleanup( pNew ) )
// Hop_ManCreateRefs( pNew );
// if ( i = Hop_ManCleanup( pNew ) )
// printf( "Cleanup after balancing removed %d dangling nodes.\n", i );
// check the resulting AIG
if ( !Aig_ManCheck(pNew) )
printf( "Aig_ManBalance(): The check has failed.\n" );
if ( !Hop_ManCheck(pNew) )
printf( "Hop_ManBalance(): The check has failed.\n" );
return pNew;
}
@ -88,33 +88,33 @@ Aig_Man_t * Aig_ManBalance( Aig_Man_t * p, int fUpdateLevel )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_NodeBalance_rec( Aig_Man_t * pNew, Aig_Obj_t * pObjOld, Vec_Vec_t * vStore, int Level, int fUpdateLevel )
Hop_Obj_t * Hop_NodeBalance_rec( Hop_Man_t * pNew, Hop_Obj_t * pObjOld, Vec_Vec_t * vStore, int Level, int fUpdateLevel )
{
Aig_Obj_t * pObjNew;
Hop_Obj_t * pObjNew;
Vec_Ptr_t * vSuper;
int i;
assert( !Aig_IsComplement(pObjOld) );
assert( !Hop_IsComplement(pObjOld) );
// return if the result is known
if ( pObjOld->pData )
return pObjOld->pData;
assert( Aig_ObjIsNode(pObjOld) );
assert( Hop_ObjIsNode(pObjOld) );
// get the implication supergate
vSuper = Aig_NodeBalanceCone( pObjOld, vStore, Level );
vSuper = Hop_NodeBalanceCone( pObjOld, vStore, Level );
// check if supergate contains two nodes in the opposite polarity
if ( vSuper->nSize == 0 )
return pObjOld->pData = Aig_ManConst0(pNew);
return pObjOld->pData = Hop_ManConst0(pNew);
if ( Vec_PtrSize(vSuper) < 2 )
printf( "BUG!\n" );
// for each old node, derive the new well-balanced node
for ( i = 0; i < Vec_PtrSize(vSuper); i++ )
{
pObjNew = Aig_NodeBalance_rec( pNew, Aig_Regular(vSuper->pArray[i]), vStore, Level + 1, fUpdateLevel );
vSuper->pArray[i] = Aig_NotCond( pObjNew, Aig_IsComplement(vSuper->pArray[i]) );
pObjNew = Hop_NodeBalance_rec( pNew, Hop_Regular(vSuper->pArray[i]), vStore, Level + 1, fUpdateLevel );
vSuper->pArray[i] = Hop_NotCond( pObjNew, Hop_IsComplement(vSuper->pArray[i]) );
}
// build the supergate
pObjNew = Aig_NodeBalanceBuildSuper( pNew, vSuper, Aig_ObjType(pObjOld), fUpdateLevel );
pObjNew = Hop_NodeBalanceBuildSuper( pNew, vSuper, Hop_ObjType(pObjOld), fUpdateLevel );
// make sure the balanced node is not assigned
// assert( pObjOld->Level >= Aig_Regular(pObjNew)->Level );
// assert( pObjOld->Level >= Hop_Regular(pObjNew)->Level );
assert( pObjOld->pData == NULL );
return pObjOld->pData = pObjNew;
}
@ -130,11 +130,11 @@ Aig_Obj_t * Aig_NodeBalance_rec( Aig_Man_t * pNew, Aig_Obj_t * pObjOld, Vec_Vec_
SeeAlso []
***********************************************************************/
int Aig_NodeBalanceCone_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
int Hop_NodeBalanceCone_rec( Hop_Obj_t * pRoot, Hop_Obj_t * pObj, Vec_Ptr_t * vSuper )
{
int RetValue1, RetValue2, i;
// check if the node is visited
if ( Aig_Regular(pObj)->fMarkB )
if ( Hop_Regular(pObj)->fMarkB )
{
// check if the node occurs in the same polarity
for ( i = 0; i < vSuper->nSize; i++ )
@ -142,23 +142,23 @@ int Aig_NodeBalanceCone_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * vS
return 1;
// check if the node is present in the opposite polarity
for ( i = 0; i < vSuper->nSize; i++ )
if ( vSuper->pArray[i] == Aig_Not(pObj) )
if ( vSuper->pArray[i] == Hop_Not(pObj) )
return -1;
assert( 0 );
return 0;
}
// if the new node is complemented or a PI, another gate begins
if ( pObj != pRoot && (Aig_IsComplement(pObj) || Aig_ObjType(pObj) != Aig_ObjType(pRoot) || Aig_ObjRefs(pObj) > 1) )
if ( pObj != pRoot && (Hop_IsComplement(pObj) || Hop_ObjType(pObj) != Hop_ObjType(pRoot) || Hop_ObjRefs(pObj) > 1) )
{
Vec_PtrPush( vSuper, pObj );
Aig_Regular(pObj)->fMarkB = 1;
Hop_Regular(pObj)->fMarkB = 1;
return 0;
}
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsNode(pObj) );
assert( !Hop_IsComplement(pObj) );
assert( Hop_ObjIsNode(pObj) );
// go through the branches
RetValue1 = Aig_NodeBalanceCone_rec( pRoot, Aig_ObjChild0(pObj), vSuper );
RetValue2 = Aig_NodeBalanceCone_rec( pRoot, Aig_ObjChild1(pObj), vSuper );
RetValue1 = Hop_NodeBalanceCone_rec( pRoot, Hop_ObjChild0(pObj), vSuper );
RetValue2 = Hop_NodeBalanceCone_rec( pRoot, Hop_ObjChild1(pObj), vSuper );
if ( RetValue1 == -1 || RetValue2 == -1 )
return -1;
// return 1 if at least one branch has a duplicate
@ -176,11 +176,11 @@ int Aig_NodeBalanceCone_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * vS
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_NodeBalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level )
Vec_Ptr_t * Hop_NodeBalanceCone( Hop_Obj_t * pObj, Vec_Vec_t * vStore, int Level )
{
Vec_Ptr_t * vNodes;
int RetValue, i;
assert( !Aig_IsComplement(pObj) );
assert( !Hop_IsComplement(pObj) );
// extend the storage
if ( Vec_VecSize( vStore ) <= Level )
Vec_VecPush( vStore, Level, 0 );
@ -188,11 +188,11 @@ Vec_Ptr_t * Aig_NodeBalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level
vNodes = Vec_VecEntry( vStore, Level );
Vec_PtrClear( vNodes );
// collect the nodes in the implication supergate
RetValue = Aig_NodeBalanceCone_rec( pObj, pObj, vNodes );
RetValue = Hop_NodeBalanceCone_rec( pObj, pObj, vNodes );
assert( vNodes->nSize > 1 );
// unmark the visited nodes
Vec_PtrForEachEntry( vNodes, pObj, i )
Aig_Regular(pObj)->fMarkB = 0;
Hop_Regular(pObj)->fMarkB = 0;
// if we found the node and its complement in the same implication supergate,
// return empty set of nodes (meaning that we should use constant-0 node)
if ( RetValue == -1 )
@ -211,9 +211,9 @@ Vec_Ptr_t * Aig_NodeBalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level
SeeAlso []
***********************************************************************/
int Aig_NodeCompareLevelsDecrease( Aig_Obj_t ** pp1, Aig_Obj_t ** pp2 )
int Hop_NodeCompareLevelsDecrease( Hop_Obj_t ** pp1, Hop_Obj_t ** pp2 )
{
int Diff = Aig_ObjLevel(Aig_Regular(*pp1)) - Aig_ObjLevel(Aig_Regular(*pp2));
int Diff = Hop_ObjLevel(Hop_Regular(*pp1)) - Hop_ObjLevel(Hop_Regular(*pp2));
if ( Diff > 0 )
return -1;
if ( Diff < 0 )
@ -232,24 +232,24 @@ int Aig_NodeCompareLevelsDecrease( Aig_Obj_t ** pp1, Aig_Obj_t ** pp2 )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_NodeBalanceBuildSuper( Aig_Man_t * p, Vec_Ptr_t * vSuper, Aig_Type_t Type, int fUpdateLevel )
Hop_Obj_t * Hop_NodeBalanceBuildSuper( Hop_Man_t * p, Vec_Ptr_t * vSuper, Hop_Type_t Type, int fUpdateLevel )
{
Aig_Obj_t * pObj1, * pObj2;
Hop_Obj_t * pObj1, * pObj2;
int LeftBound;
assert( vSuper->nSize > 1 );
// sort the new nodes by level in the decreasing order
Vec_PtrSort( vSuper, Aig_NodeCompareLevelsDecrease );
Vec_PtrSort( vSuper, Hop_NodeCompareLevelsDecrease );
// balance the nodes
while ( vSuper->nSize > 1 )
{
// find the left bound on the node to be paired
LeftBound = (!fUpdateLevel)? 0 : Aig_NodeBalanceFindLeft( vSuper );
LeftBound = (!fUpdateLevel)? 0 : Hop_NodeBalanceFindLeft( vSuper );
// find the node that can be shared (if no such node, randomize choice)
Aig_NodeBalancePermute( p, vSuper, LeftBound, Type == AIG_EXOR );
Hop_NodeBalancePermute( p, vSuper, LeftBound, Type == AIG_EXOR );
// pull out the last two nodes
pObj1 = Vec_PtrPop(vSuper);
pObj2 = Vec_PtrPop(vSuper);
Aig_NodeBalancePushUniqueOrderByLevel( vSuper, Aig_Oper(p, pObj1, pObj2, Type) );
Hop_NodeBalancePushUniqueOrderByLevel( vSuper, Hop_Oper(p, pObj1, pObj2, Type) );
}
return Vec_PtrEntry(vSuper, 0);
}
@ -269,9 +269,9 @@ Aig_Obj_t * Aig_NodeBalanceBuildSuper( Aig_Man_t * p, Vec_Ptr_t * vSuper, Aig_Ty
SeeAlso []
***********************************************************************/
int Aig_NodeBalanceFindLeft( Vec_Ptr_t * vSuper )
int Hop_NodeBalanceFindLeft( Vec_Ptr_t * vSuper )
{
Aig_Obj_t * pObjRight, * pObjLeft;
Hop_Obj_t * pObjRight, * pObjLeft;
int Current;
// if two or less nodes, pair with the first
if ( Vec_PtrSize(vSuper) < 3 )
@ -285,13 +285,13 @@ int Aig_NodeBalanceFindLeft( Vec_Ptr_t * vSuper )
// get the next node on the left
pObjLeft = Vec_PtrEntry( vSuper, Current );
// if the level of this node is different, quit the loop
if ( Aig_ObjLevel(Aig_Regular(pObjLeft)) != Aig_ObjLevel(Aig_Regular(pObjRight)) )
if ( Hop_ObjLevel(Hop_Regular(pObjLeft)) != Hop_ObjLevel(Hop_Regular(pObjRight)) )
break;
}
Current++;
// get the node, for which the equality holds
pObjLeft = Vec_PtrEntry( vSuper, Current );
assert( Aig_ObjLevel(Aig_Regular(pObjLeft)) == Aig_ObjLevel(Aig_Regular(pObjRight)) );
assert( Hop_ObjLevel(Hop_Regular(pObjLeft)) == Hop_ObjLevel(Hop_Regular(pObjRight)) );
return Current;
}
@ -307,9 +307,9 @@ int Aig_NodeBalanceFindLeft( Vec_Ptr_t * vSuper )
SeeAlso []
***********************************************************************/
void Aig_NodeBalancePermute( Aig_Man_t * p, Vec_Ptr_t * vSuper, int LeftBound, int fExor )
void Hop_NodeBalancePermute( Hop_Man_t * p, Vec_Ptr_t * vSuper, int LeftBound, int fExor )
{
Aig_Obj_t * pObj1, * pObj2, * pObj3, * pGhost;
Hop_Obj_t * pObj1, * pObj2, * pObj3, * pGhost;
int RightBound, i;
// get the right bound
RightBound = Vec_PtrSize(vSuper) - 2;
@ -319,20 +319,20 @@ void Aig_NodeBalancePermute( Aig_Man_t * p, Vec_Ptr_t * vSuper, int LeftBound, i
// get the two last nodes
pObj1 = Vec_PtrEntry( vSuper, RightBound + 1 );
pObj2 = Vec_PtrEntry( vSuper, RightBound );
if ( Aig_Regular(pObj1) == p->pConst1 || Aig_Regular(pObj2) == p->pConst1 )
if ( Hop_Regular(pObj1) == p->pConst1 || Hop_Regular(pObj2) == p->pConst1 )
return;
// find the first node that can be shared
for ( i = RightBound; i >= LeftBound; i-- )
{
pObj3 = Vec_PtrEntry( vSuper, i );
if ( Aig_Regular(pObj3) == p->pConst1 )
if ( Hop_Regular(pObj3) == p->pConst1 )
{
Vec_PtrWriteEntry( vSuper, i, pObj2 );
Vec_PtrWriteEntry( vSuper, RightBound, pObj3 );
return;
}
pGhost = Aig_ObjCreateGhost( p, pObj1, pObj3, fExor? AIG_EXOR : AIG_AND );
if ( Aig_TableLookup( p, pGhost ) )
pGhost = Hop_ObjCreateGhost( p, pObj1, pObj3, fExor? AIG_EXOR : AIG_AND );
if ( Hop_TableLookup( p, pGhost ) )
{
if ( pObj3 == pObj2 )
return;
@ -365,9 +365,9 @@ void Aig_NodeBalancePermute( Aig_Man_t * p, Vec_Ptr_t * vSuper, int LeftBound, i
SeeAlso []
***********************************************************************/
void Aig_NodeBalancePushUniqueOrderByLevel( Vec_Ptr_t * vStore, Aig_Obj_t * pObj )
void Hop_NodeBalancePushUniqueOrderByLevel( Vec_Ptr_t * vStore, Hop_Obj_t * pObj )
{
Aig_Obj_t * pObj1, * pObj2;
Hop_Obj_t * pObj1, * pObj2;
int i;
if ( Vec_PtrPushUnique(vStore, pObj) )
return;
@ -376,7 +376,7 @@ void Aig_NodeBalancePushUniqueOrderByLevel( Vec_Ptr_t * vStore, Aig_Obj_t * pObj
{
pObj1 = vStore->pArray[i ];
pObj2 = vStore->pArray[i-1];
if ( Aig_ObjLevel(Aig_Regular(pObj1)) <= Aig_ObjLevel(Aig_Regular(pObj2)) )
if ( Hop_ObjLevel(Hop_Regular(pObj1)) <= Hop_ObjLevel(Hop_Regular(pObj2)) )
break;
vStore->pArray[i ] = pObj2;
vStore->pArray[i-1] = pObj1;

50
src/temp/aig_free/aigCheck.c → src/aig/hop/hopCheck.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigCheck.c]
FileName [hopCheck.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigCheck.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopCheck.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -39,66 +39,66 @@
SeeAlso []
***********************************************************************/
int Aig_ManCheck( Aig_Man_t * p )
int Hop_ManCheck( Hop_Man_t * p )
{
Aig_Obj_t * pObj, * pObj2;
Hop_Obj_t * pObj, * pObj2;
int i;
// check primary inputs
Aig_ManForEachPi( p, pObj, i )
Hop_ManForEachPi( p, pObj, i )
{
if ( Aig_ObjFanin0(pObj) || Aig_ObjFanin1(pObj) )
if ( Hop_ObjFanin0(pObj) || Hop_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The PI node \"%p\" has fanins.\n", pObj );
printf( "Hop_ManCheck: The PI node \"%p\" has fanins.\n", pObj );
return 0;
}
}
// check primary outputs
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
{
if ( !Aig_ObjFanin0(pObj) )
if ( !Hop_ObjFanin0(pObj) )
{
printf( "Aig_ManCheck: The PO node \"%p\" has NULL fanin.\n", pObj );
printf( "Hop_ManCheck: The PO node \"%p\" has NULL fanin.\n", pObj );
return 0;
}
if ( Aig_ObjFanin1(pObj) )
if ( Hop_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The PO node \"%p\" has second fanin.\n", pObj );
printf( "Hop_ManCheck: The PO node \"%p\" has second fanin.\n", pObj );
return 0;
}
}
// check internal nodes
Aig_ManForEachNode( p, pObj, i )
Hop_ManForEachNode( p, pObj, i )
{
if ( !Aig_ObjFanin0(pObj) || !Aig_ObjFanin1(pObj) )
if ( !Hop_ObjFanin0(pObj) || !Hop_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The AIG has internal node \"%p\" with a NULL fanin.\n", pObj );
printf( "Hop_ManCheck: The AIG has internal node \"%p\" with a NULL fanin.\n", pObj );
return 0;
}
if ( Aig_ObjFanin0(pObj) >= Aig_ObjFanin1(pObj) )
if ( Hop_ObjFanin0(pObj) >= Hop_ObjFanin1(pObj) )
{
printf( "Aig_ManCheck: The AIG has node \"%p\" with a wrong ordering of fanins.\n", pObj );
printf( "Hop_ManCheck: The AIG has node \"%p\" with a wrong ordering of fanins.\n", pObj );
return 0;
}
pObj2 = Aig_TableLookup( p, pObj );
pObj2 = Hop_TableLookup( p, pObj );
if ( pObj2 != pObj )
{
printf( "Aig_ManCheck: Node \"%p\" is not in the structural hashing table.\n", pObj );
printf( "Hop_ManCheck: Node \"%p\" is not in the structural hashing table.\n", pObj );
return 0;
}
}
// count the total number of nodes
if ( Aig_ManObjNum(p) != 1 + Aig_ManPiNum(p) + Aig_ManPoNum(p) + Aig_ManAndNum(p) + Aig_ManExorNum(p) )
if ( Hop_ManObjNum(p) != 1 + Hop_ManPiNum(p) + Hop_ManPoNum(p) + Hop_ManAndNum(p) + Hop_ManExorNum(p) )
{
printf( "Aig_ManCheck: The number of created nodes is wrong.\n" );
printf( "Hop_ManCheck: The number of created nodes is wrong.\n" );
return 0;
}
// count the number of nodes in the table
if ( Aig_TableCountEntries(p) != Aig_ManAndNum(p) + Aig_ManExorNum(p) )
if ( Hop_TableCountEntries(p) != Hop_ManAndNum(p) + Hop_ManExorNum(p) )
{
printf( "Aig_ManCheck: The number of nodes in the structural hashing table is wrong.\n" );
printf( "Hop_ManCheck: The number of nodes in the structural hashing table is wrong.\n" );
return 0;
}
// if ( !Aig_ManIsAcyclic(p) )
// if ( !Hop_ManIsAcyclic(p) )
// return 0;
return 1;
}

218
src/temp/aig/aigDfs.c → src/aig/hop/hopDfs.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigDfs.c]
FileName [hopDfs.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigDfs.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopDfs.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -39,15 +39,15 @@
SeeAlso []
***********************************************************************/
void Aig_ManDfs_rec( Aig_Obj_t * pObj, Vec_Ptr_t * vNodes )
void Hop_ManDfs_rec( Hop_Obj_t * pObj, Vec_Ptr_t * vNodes )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return;
Aig_ManDfs_rec( Aig_ObjFanin0(pObj), vNodes );
Aig_ManDfs_rec( Aig_ObjFanin1(pObj), vNodes );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA(pObj);
Hop_ManDfs_rec( Hop_ObjFanin0(pObj), vNodes );
Hop_ManDfs_rec( Hop_ObjFanin1(pObj), vNodes );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA(pObj);
Vec_PtrPush( vNodes, pObj );
}
@ -62,16 +62,16 @@ void Aig_ManDfs_rec( Aig_Obj_t * pObj, Vec_Ptr_t * vNodes )
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManDfs( Aig_Man_t * p )
Vec_Ptr_t * Hop_ManDfs( Hop_Man_t * p )
{
Vec_Ptr_t * vNodes;
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
vNodes = Vec_PtrAlloc( Aig_ManNodeNum(p) );
Aig_ManForEachNode( p, pObj, i )
Aig_ManDfs_rec( pObj, vNodes );
Aig_ManForEachNode( p, pObj, i )
Aig_ObjClearMarkA(pObj);
vNodes = Vec_PtrAlloc( Hop_ManNodeNum(p) );
Hop_ManForEachNode( p, pObj, i )
Hop_ManDfs_rec( pObj, vNodes );
Hop_ManForEachNode( p, pObj, i )
Hop_ObjClearMarkA(pObj);
return vNodes;
}
@ -86,16 +86,16 @@ Vec_Ptr_t * Aig_ManDfs( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManDfsNode( Aig_Man_t * p, Aig_Obj_t * pNode )
Vec_Ptr_t * Hop_ManDfsNode( Hop_Man_t * p, Hop_Obj_t * pNode )
{
Vec_Ptr_t * vNodes;
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
assert( !Aig_IsComplement(pNode) );
assert( !Hop_IsComplement(pNode) );
vNodes = Vec_PtrAlloc( 16 );
Aig_ManDfs_rec( pNode, vNodes );
Hop_ManDfs_rec( pNode, vNodes );
Vec_PtrForEachEntry( vNodes, pObj, i )
Aig_ObjClearMarkA(pObj);
Hop_ObjClearMarkA(pObj);
return vNodes;
}
@ -110,28 +110,28 @@ Vec_Ptr_t * Aig_ManDfsNode( Aig_Man_t * p, Aig_Obj_t * pNode )
SeeAlso []
***********************************************************************/
int Aig_ManCountLevels( Aig_Man_t * p )
int Hop_ManCountLevels( Hop_Man_t * p )
{
Vec_Ptr_t * vNodes;
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i, LevelsMax, Level0, Level1;
// initialize the levels
Aig_ManConst1(p)->pData = NULL;
Aig_ManForEachPi( p, pObj, i )
Hop_ManConst1(p)->pData = NULL;
Hop_ManForEachPi( p, pObj, i )
pObj->pData = NULL;
// compute levels in a DFS order
vNodes = Aig_ManDfs( p );
vNodes = Hop_ManDfs( p );
Vec_PtrForEachEntry( vNodes, pObj, i )
{
Level0 = (int)Aig_ObjFanin0(pObj)->pData;
Level1 = (int)Aig_ObjFanin1(pObj)->pData;
pObj->pData = (void *)(1 + Aig_ObjIsExor(pObj) + AIG_MAX(Level0, Level1));
Level0 = (int)Hop_ObjFanin0(pObj)->pData;
Level1 = (int)Hop_ObjFanin1(pObj)->pData;
pObj->pData = (void *)(1 + Hop_ObjIsExor(pObj) + AIG_MAX(Level0, Level1));
}
Vec_PtrFree( vNodes );
// get levels of the POs
LevelsMax = 0;
Aig_ManForEachPo( p, pObj, i )
LevelsMax = AIG_MAX( LevelsMax, (int)Aig_ObjFanin0(pObj)->pData );
Hop_ManForEachPo( p, pObj, i )
LevelsMax = AIG_MAX( LevelsMax, (int)Hop_ObjFanin0(pObj)->pData );
return LevelsMax;
}
@ -146,29 +146,29 @@ int Aig_ManCountLevels( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ManCreateRefs( Aig_Man_t * p )
void Hop_ManCreateRefs( Hop_Man_t * p )
{
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
if ( p->fRefCount )
return;
p->fRefCount = 1;
// clear refs
Aig_ObjClearRef( Aig_ManConst1(p) );
Aig_ManForEachPi( p, pObj, i )
Aig_ObjClearRef( pObj );
Aig_ManForEachNode( p, pObj, i )
Aig_ObjClearRef( pObj );
Aig_ManForEachPo( p, pObj, i )
Aig_ObjClearRef( pObj );
Hop_ObjClearRef( Hop_ManConst1(p) );
Hop_ManForEachPi( p, pObj, i )
Hop_ObjClearRef( pObj );
Hop_ManForEachNode( p, pObj, i )
Hop_ObjClearRef( pObj );
Hop_ManForEachPo( p, pObj, i )
Hop_ObjClearRef( pObj );
// set refs
Aig_ManForEachNode( p, pObj, i )
Hop_ManForEachNode( p, pObj, i )
{
Aig_ObjRef( Aig_ObjFanin0(pObj) );
Aig_ObjRef( Aig_ObjFanin1(pObj) );
Hop_ObjRef( Hop_ObjFanin0(pObj) );
Hop_ObjRef( Hop_ObjFanin1(pObj) );
}
Aig_ManForEachPo( p, pObj, i )
Aig_ObjRef( Aig_ObjFanin0(pObj) );
Hop_ManForEachPo( p, pObj, i )
Hop_ObjRef( Hop_ObjFanin0(pObj) );
}
/**Function*************************************************************
@ -182,15 +182,15 @@ void Aig_ManCreateRefs( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ConeMark_rec( Aig_Obj_t * pObj )
void Hop_ConeMark_rec( Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return;
Aig_ConeMark_rec( Aig_ObjFanin0(pObj) );
Aig_ConeMark_rec( Aig_ObjFanin1(pObj) );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
Hop_ConeMark_rec( Hop_ObjFanin0(pObj) );
Hop_ConeMark_rec( Hop_ObjFanin1(pObj) );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
}
/**Function*************************************************************
@ -204,15 +204,15 @@ void Aig_ConeMark_rec( Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Aig_ConeCleanAndMark_rec( Aig_Obj_t * pObj )
void Hop_ConeCleanAndMark_rec( Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return;
Aig_ConeCleanAndMark_rec( Aig_ObjFanin0(pObj) );
Aig_ConeCleanAndMark_rec( Aig_ObjFanin1(pObj) );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
Hop_ConeCleanAndMark_rec( Hop_ObjFanin0(pObj) );
Hop_ConeCleanAndMark_rec( Hop_ObjFanin1(pObj) );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
pObj->pData = NULL;
}
@ -227,16 +227,16 @@ void Aig_ConeCleanAndMark_rec( Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
int Aig_ConeCountAndMark_rec( Aig_Obj_t * pObj )
int Hop_ConeCountAndMark_rec( Hop_Obj_t * pObj )
{
int Counter;
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return 0;
Counter = 1 + Aig_ConeCountAndMark_rec( Aig_ObjFanin0(pObj) ) +
Aig_ConeCountAndMark_rec( Aig_ObjFanin1(pObj) );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
Counter = 1 + Hop_ConeCountAndMark_rec( Hop_ObjFanin0(pObj) ) +
Hop_ConeCountAndMark_rec( Hop_ObjFanin1(pObj) );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
return Counter;
}
@ -251,15 +251,15 @@ int Aig_ConeCountAndMark_rec( Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Aig_ConeUnmark_rec( Aig_Obj_t * pObj )
void Hop_ConeUnmark_rec( Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || !Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || !Hop_ObjIsMarkA(pObj) )
return;
Aig_ConeUnmark_rec( Aig_ObjFanin0(pObj) );
Aig_ConeUnmark_rec( Aig_ObjFanin1(pObj) );
assert( Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjClearMarkA( pObj );
Hop_ConeUnmark_rec( Hop_ObjFanin0(pObj) );
Hop_ConeUnmark_rec( Hop_ObjFanin1(pObj) );
assert( Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjClearMarkA( pObj );
}
/**Function*************************************************************
@ -273,11 +273,11 @@ void Aig_ConeUnmark_rec( Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
int Aig_DagSize( Aig_Obj_t * pObj )
int Hop_DagSize( Hop_Obj_t * pObj )
{
int Counter;
Counter = Aig_ConeCountAndMark_rec( Aig_Regular(pObj) );
Aig_ConeUnmark_rec( Aig_Regular(pObj) );
Counter = Hop_ConeCountAndMark_rec( Hop_Regular(pObj) );
Hop_ConeUnmark_rec( Hop_Regular(pObj) );
return Counter;
}
@ -292,16 +292,16 @@ int Aig_DagSize( Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Aig_Transfer_rec( Aig_Man_t * pDest, Aig_Obj_t * pObj )
void Hop_Transfer_rec( Hop_Man_t * pDest, Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return;
Aig_Transfer_rec( pDest, Aig_ObjFanin0(pObj) );
Aig_Transfer_rec( pDest, Aig_ObjFanin1(pObj) );
pObj->pData = Aig_And( pDest, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
Hop_Transfer_rec( pDest, Hop_ObjFanin0(pObj) );
Hop_Transfer_rec( pDest, Hop_ObjFanin1(pObj) );
pObj->pData = Hop_And( pDest, Hop_ObjChild0Copy(pObj), Hop_ObjChild1Copy(pObj) );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
}
/**Function*************************************************************
@ -315,27 +315,27 @@ void Aig_Transfer_rec( Aig_Man_t * pDest, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Transfer( Aig_Man_t * pSour, Aig_Man_t * pDest, Aig_Obj_t * pRoot, int nVars )
Hop_Obj_t * Hop_Transfer( Hop_Man_t * pSour, Hop_Man_t * pDest, Hop_Obj_t * pRoot, int nVars )
{
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
// solve simple cases
if ( pSour == pDest )
return pRoot;
if ( Aig_ObjIsConst1( Aig_Regular(pRoot) ) )
return Aig_NotCond( Aig_ManConst1(pDest), Aig_IsComplement(pRoot) );
if ( Hop_ObjIsConst1( Hop_Regular(pRoot) ) )
return Hop_NotCond( Hop_ManConst1(pDest), Hop_IsComplement(pRoot) );
// set the PI mapping
Aig_ManForEachPi( pSour, pObj, i )
Hop_ManForEachPi( pSour, pObj, i )
{
if ( i == nVars )
break;
pObj->pData = Aig_IthVar(pDest, i);
pObj->pData = Hop_IthVar(pDest, i);
}
// transfer and set markings
Aig_Transfer_rec( pDest, Aig_Regular(pRoot) );
Hop_Transfer_rec( pDest, Hop_Regular(pRoot) );
// clear the markings
Aig_ConeUnmark_rec( Aig_Regular(pRoot) );
return Aig_NotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );
Hop_ConeUnmark_rec( Hop_Regular(pRoot) );
return Hop_NotCond( Hop_Regular(pRoot)->pData, Hop_IsComplement(pRoot) );
}
/**Function*************************************************************
@ -349,21 +349,21 @@ Aig_Obj_t * Aig_Transfer( Aig_Man_t * pSour, Aig_Man_t * pDest, Aig_Obj_t * pRoo
SeeAlso []
***********************************************************************/
void Aig_Compose_rec( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFunc, Aig_Obj_t * pVar )
void Hop_Compose_rec( Hop_Man_t * p, Hop_Obj_t * pObj, Hop_Obj_t * pFunc, Hop_Obj_t * pVar )
{
assert( !Aig_IsComplement(pObj) );
if ( Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( Hop_ObjIsMarkA(pObj) )
return;
if ( Aig_ObjIsConst1(pObj) || Aig_ObjIsPi(pObj) )
if ( Hop_ObjIsConst1(pObj) || Hop_ObjIsPi(pObj) )
{
pObj->pData = pObj == pVar ? pFunc : pObj;
return;
}
Aig_Compose_rec( p, Aig_ObjFanin0(pObj), pFunc, pVar );
Aig_Compose_rec( p, Aig_ObjFanin1(pObj), pFunc, pVar );
pObj->pData = Aig_And( p, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
Hop_Compose_rec( p, Hop_ObjFanin0(pObj), pFunc, pVar );
Hop_Compose_rec( p, Hop_ObjFanin1(pObj), pFunc, pVar );
pObj->pData = Hop_And( p, Hop_ObjChild0Copy(pObj), Hop_ObjChild1Copy(pObj) );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
}
/**Function*************************************************************
@ -377,19 +377,19 @@ void Aig_Compose_rec( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFunc, Aig_Ob
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Compose( Aig_Man_t * p, Aig_Obj_t * pRoot, Aig_Obj_t * pFunc, int iVar )
Hop_Obj_t * Hop_Compose( Hop_Man_t * p, Hop_Obj_t * pRoot, Hop_Obj_t * pFunc, int iVar )
{
// quit if the PI variable is not defined
if ( iVar >= Aig_ManPiNum(p) )
if ( iVar >= Hop_ManPiNum(p) )
{
printf( "Aig_Compose(): The PI variable %d is not defined.\n", iVar );
printf( "Hop_Compose(): The PI variable %d is not defined.\n", iVar );
return NULL;
}
// recursively perform composition
Aig_Compose_rec( p, Aig_Regular(pRoot), pFunc, Aig_ManPi(p, iVar) );
Hop_Compose_rec( p, Hop_Regular(pRoot), pFunc, Hop_ManPi(p, iVar) );
// clear the markings
Aig_ConeUnmark_rec( Aig_Regular(pRoot) );
return Aig_NotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );
Hop_ConeUnmark_rec( Hop_Regular(pRoot) );
return Hop_NotCond( Hop_Regular(pRoot)->pData, Hop_IsComplement(pRoot) );
}
////////////////////////////////////////////////////////////////////////

62
src/temp/aig/aigMan.c → src/aig/hop/hopMan.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigMan.c]
FileName [hopMan.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aig_.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopMan.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -39,12 +39,12 @@
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManStart()
Hop_Man_t * Hop_ManStart()
{
Aig_Man_t * p;
Hop_Man_t * p;
// start the manager
p = ALLOC( Aig_Man_t, 1 );
memset( p, 0, sizeof(Aig_Man_t) );
p = ALLOC( Hop_Man_t, 1 );
memset( p, 0, sizeof(Hop_Man_t) );
// perform initializations
p->nTravIds = 1;
p->fRefCount = 1;
@ -53,16 +53,16 @@ Aig_Man_t * Aig_ManStart()
p->vPis = Vec_PtrAlloc( 100 );
p->vPos = Vec_PtrAlloc( 100 );
// prepare the internal memory manager
Aig_ManStartMemory( p );
Hop_ManStartMemory( p );
// create the constant node
p->pConst1 = Aig_ManFetchMemory( p );
p->pConst1 = Hop_ManFetchMemory( p );
p->pConst1->Type = AIG_CONST1;
p->pConst1->fPhase = 1;
p->nCreated = 1;
// start the table
p->nTableSize = 10007;
p->pTable = ALLOC( Aig_Obj_t *, p->nTableSize );
memset( p->pTable, 0, sizeof(Aig_Obj_t *) * p->nTableSize );
p->pTable = ALLOC( Hop_Obj_t *, p->nTableSize );
memset( p->pTable, 0, sizeof(Hop_Obj_t *) * p->nTableSize );
return p;
}
@ -77,24 +77,24 @@ Aig_Man_t * Aig_ManStart()
SeeAlso []
***********************************************************************/
void Aig_ManStop( Aig_Man_t * p )
void Hop_ManStop( Hop_Man_t * p )
{
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
// make sure the nodes have clean marks
pObj = Aig_ManConst1(p);
pObj = Hop_ManConst1(p);
assert( !pObj->fMarkA && !pObj->fMarkB );
Aig_ManForEachPi( p, pObj, i )
Hop_ManForEachPi( p, pObj, i )
assert( !pObj->fMarkA && !pObj->fMarkB );
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
assert( !pObj->fMarkA && !pObj->fMarkB );
Aig_ManForEachNode( p, pObj, i )
Hop_ManForEachNode( p, pObj, i )
assert( !pObj->fMarkA && !pObj->fMarkB );
// print time
if ( p->time1 ) { PRT( "time1", p->time1 ); }
if ( p->time2 ) { PRT( "time2", p->time2 ); }
// Aig_TableProfile( p );
if ( p->vChunks ) Aig_ManStopMemory( p );
// Hop_TableProfile( p );
if ( p->vChunks ) Hop_ManStopMemory( p );
if ( p->vPis ) Vec_PtrFree( p->vPis );
if ( p->vPos ) Vec_PtrFree( p->vPos );
free( p->pTable );
@ -112,23 +112,23 @@ void Aig_ManStop( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
int Aig_ManCleanup( Aig_Man_t * p )
int Hop_ManCleanup( Hop_Man_t * p )
{
Vec_Ptr_t * vNodes;
Aig_Obj_t * pNode;
Hop_Obj_t * pNode;
int i, nNodesOld;
assert( p->fRefCount );
nNodesOld = Aig_ManNodeNum(p);
nNodesOld = Hop_ManNodeNum(p);
// collect roots of dangling nodes
vNodes = Vec_PtrAlloc( 100 );
Aig_ManForEachNode( p, pNode, i )
if ( Aig_ObjRefs(pNode) == 0 )
Hop_ManForEachNode( p, pNode, i )
if ( Hop_ObjRefs(pNode) == 0 )
Vec_PtrPush( vNodes, pNode );
// recursively remove dangling nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
Aig_ObjDelete_rec( p, pNode );
Hop_ObjDelete_rec( p, pNode );
Vec_PtrFree( vNodes );
return nNodesOld - Aig_ManNodeNum(p);
return nNodesOld - Hop_ManNodeNum(p);
}
/**Function*************************************************************
@ -142,14 +142,14 @@ int Aig_ManCleanup( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ManPrintStats( Aig_Man_t * p )
void Hop_ManPrintStats( Hop_Man_t * p )
{
printf( "PI/PO = %d/%d. ", Aig_ManPiNum(p), Aig_ManPoNum(p) );
printf( "A = %7d. ", Aig_ManAndNum(p) );
printf( "X = %5d. ", Aig_ManExorNum(p) );
printf( "PI/PO = %d/%d. ", Hop_ManPiNum(p), Hop_ManPoNum(p) );
printf( "A = %7d. ", Hop_ManAndNum(p) );
printf( "X = %5d. ", Hop_ManExorNum(p) );
printf( "Cre = %7d. ", p->nCreated );
printf( "Del = %7d. ", p->nDeleted );
printf( "Lev = %3d. ", Aig_ManCountLevels(p) );
printf( "Lev = %3d. ", Hop_ManCountLevels(p) );
printf( "\n" );
}

24
src/temp/aig_free/aigMem.c → src/aig/hop/hopMem.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigMem.c]
FileName [hopMem.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigMem.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopMem.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -43,7 +43,7 @@
SeeAlso []
***********************************************************************/
void Aig_ManStartMemory( Aig_Man_t * p )
void Hop_ManStartMemory( Hop_Man_t * p )
{
p->vChunks = Vec_PtrAlloc( 128 );
p->vPages = Vec_PtrAlloc( 128 );
@ -60,7 +60,7 @@ void Aig_ManStartMemory( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ManStopMemory( Aig_Man_t * p )
void Hop_ManStopMemory( Hop_Man_t * p )
{
void * pMemory;
int i;
@ -83,15 +83,15 @@ void Aig_ManStopMemory( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ManAddMemory( Aig_Man_t * p )
void Hop_ManAddMemory( Hop_Man_t * p )
{
char * pMemory;
int i, nBytes;
assert( sizeof(Aig_Obj_t) <= 64 );
assert( sizeof(Hop_Obj_t) <= 64 );
assert( p->pListFree == NULL );
// assert( (Aig_ManObjNum(p) & IVY_PAGE_MASK) == 0 );
// assert( (Hop_ManObjNum(p) & IVY_PAGE_MASK) == 0 );
// allocate new memory page
nBytes = sizeof(Aig_Obj_t) * (1<<IVY_PAGE_SIZE) + 64;
nBytes = sizeof(Hop_Obj_t) * (1<<IVY_PAGE_SIZE) + 64;
pMemory = ALLOC( char, nBytes );
Vec_PtrPush( p->vChunks, pMemory );
// align memory at the 32-byte boundary
@ -99,11 +99,11 @@ void Aig_ManAddMemory( Aig_Man_t * p )
// remember the manager in the first entry
Vec_PtrPush( p->vPages, pMemory );
// break the memory down into nodes
p->pListFree = (Aig_Obj_t *)pMemory;
p->pListFree = (Hop_Obj_t *)pMemory;
for ( i = 1; i <= IVY_PAGE_MASK; i++ )
{
*((char **)pMemory) = pMemory + sizeof(Aig_Obj_t);
pMemory += sizeof(Aig_Obj_t);
*((char **)pMemory) = pMemory + sizeof(Hop_Obj_t);
pMemory += sizeof(Hop_Obj_t);
}
*((char **)pMemory) = NULL;
}

100
src/temp/aig/aigObj.c → src/aig/hop/hopObj.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigObj.c]
FileName [hopObj.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigObj.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopObj.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -39,10 +39,10 @@
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ObjCreatePi( Aig_Man_t * p )
Hop_Obj_t * Hop_ObjCreatePi( Hop_Man_t * p )
{
Aig_Obj_t * pObj;
pObj = Aig_ManFetchMemory( p );
Hop_Obj_t * pObj;
pObj = Hop_ManFetchMemory( p );
pObj->Type = AIG_PI;
Vec_PtrPush( p->vPis, pObj );
p->nObjs[AIG_PI]++;
@ -61,18 +61,18 @@ Aig_Obj_t * Aig_ObjCreatePi( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ObjCreatePo( Aig_Man_t * p, Aig_Obj_t * pDriver )
Hop_Obj_t * Hop_ObjCreatePo( Hop_Man_t * p, Hop_Obj_t * pDriver )
{
Aig_Obj_t * pObj;
pObj = Aig_ManFetchMemory( p );
Hop_Obj_t * pObj;
pObj = Hop_ManFetchMemory( p );
pObj->Type = AIG_PO;
Vec_PtrPush( p->vPos, pObj );
// add connections
pObj->pFanin0 = pDriver;
if ( p->fRefCount )
Aig_ObjRef( Aig_Regular(pDriver) );
Hop_ObjRef( Hop_Regular(pDriver) );
else
pObj->nRefs = Aig_ObjLevel( Aig_Regular(pDriver) );
pObj->nRefs = Hop_ObjLevel( Hop_Regular(pDriver) );
// update node counters of the manager
p->nObjs[AIG_PO]++;
p->nCreated++;
@ -90,19 +90,19 @@ Aig_Obj_t * Aig_ObjCreatePo( Aig_Man_t * p, Aig_Obj_t * pDriver )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost )
Hop_Obj_t * Hop_ObjCreate( Hop_Man_t * p, Hop_Obj_t * pGhost )
{
Aig_Obj_t * pObj;
assert( !Aig_IsComplement(pGhost) );
assert( Aig_ObjIsNode(pGhost) );
Hop_Obj_t * pObj;
assert( !Hop_IsComplement(pGhost) );
assert( Hop_ObjIsNode(pGhost) );
assert( pGhost == &p->Ghost );
// get memory for the new object
pObj = Aig_ManFetchMemory( p );
pObj = Hop_ManFetchMemory( p );
pObj->Type = pGhost->Type;
// add connections
Aig_ObjConnect( p, pObj, pGhost->pFanin0, pGhost->pFanin1 );
Hop_ObjConnect( p, pObj, pGhost->pFanin0, pGhost->pFanin1 );
// update node counters of the manager
p->nObjs[Aig_ObjType(pObj)]++;
p->nObjs[Hop_ObjType(pObj)]++;
p->nCreated++;
return pObj;
}
@ -118,10 +118,10 @@ Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost )
SeeAlso []
***********************************************************************/
void Aig_ObjConnect( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFan0, Aig_Obj_t * pFan1 )
void Hop_ObjConnect( Hop_Man_t * p, Hop_Obj_t * pObj, Hop_Obj_t * pFan0, Hop_Obj_t * pFan1 )
{
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsNode(pObj) );
assert( !Hop_IsComplement(pObj) );
assert( Hop_ObjIsNode(pObj) );
// add the first fanin
pObj->pFanin0 = pFan0;
pObj->pFanin1 = pFan1;
@ -129,14 +129,14 @@ void Aig_ObjConnect( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFan0, Aig_Obj
if ( p->fRefCount )
{
if ( pFan0 != NULL )
Aig_ObjRef( Aig_ObjFanin0(pObj) );
Hop_ObjRef( Hop_ObjFanin0(pObj) );
if ( pFan1 != NULL )
Aig_ObjRef( Aig_ObjFanin1(pObj) );
Hop_ObjRef( Hop_ObjFanin1(pObj) );
}
else
pObj->nRefs = Aig_ObjLevelNew( pObj );
pObj->nRefs = Hop_ObjLevelNew( pObj );
// add the node to the structural hash table
Aig_TableInsert( p, pObj );
Hop_TableInsert( p, pObj );
}
/**Function*************************************************************
@ -150,17 +150,17 @@ void Aig_ObjConnect( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFan0, Aig_Obj
SeeAlso []
***********************************************************************/
void Aig_ObjDisconnect( Aig_Man_t * p, Aig_Obj_t * pObj )
void Hop_ObjDisconnect( Hop_Man_t * p, Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsNode(pObj) );
assert( !Hop_IsComplement(pObj) );
assert( Hop_ObjIsNode(pObj) );
// remove connections
if ( pObj->pFanin0 != NULL )
Aig_ObjDeref(Aig_ObjFanin0(pObj));
Hop_ObjDeref(Hop_ObjFanin0(pObj));
if ( pObj->pFanin1 != NULL )
Aig_ObjDeref(Aig_ObjFanin1(pObj));
Hop_ObjDeref(Hop_ObjFanin1(pObj));
// remove the node from the structural hash table
Aig_TableDelete( p, pObj );
Hop_TableDelete( p, pObj );
// add the first fanin
pObj->pFanin0 = NULL;
pObj->pFanin1 = NULL;
@ -177,21 +177,21 @@ void Aig_ObjDisconnect( Aig_Man_t * p, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Aig_ObjDelete( Aig_Man_t * p, Aig_Obj_t * pObj )
void Hop_ObjDelete( Hop_Man_t * p, Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
assert( !Aig_ObjIsTerm(pObj) );
assert( Aig_ObjRefs(pObj) == 0 );
assert( !Hop_IsComplement(pObj) );
assert( !Hop_ObjIsTerm(pObj) );
assert( Hop_ObjRefs(pObj) == 0 );
// update node counters of the manager
p->nObjs[pObj->Type]--;
p->nDeleted++;
// remove connections
Aig_ObjDisconnect( p, pObj );
Hop_ObjDisconnect( p, pObj );
// remove PIs/POs from the arrays
if ( Aig_ObjIsPi(pObj) )
if ( Hop_ObjIsPi(pObj) )
Vec_PtrRemove( p->vPis, pObj );
// free the node
Aig_ManRecycleMemory( p, pObj );
Hop_ManRecycleMemory( p, pObj );
}
/**Function*************************************************************
@ -205,20 +205,20 @@ void Aig_ObjDelete( Aig_Man_t * p, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Aig_ObjDelete_rec( Aig_Man_t * p, Aig_Obj_t * pObj )
void Hop_ObjDelete_rec( Hop_Man_t * p, Hop_Obj_t * pObj )
{
Aig_Obj_t * pFanin0, * pFanin1;
assert( !Aig_IsComplement(pObj) );
if ( Aig_ObjIsConst1(pObj) || Aig_ObjIsPi(pObj) )
Hop_Obj_t * pFanin0, * pFanin1;
assert( !Hop_IsComplement(pObj) );
if ( Hop_ObjIsConst1(pObj) || Hop_ObjIsPi(pObj) )
return;
assert( Aig_ObjIsNode(pObj) );
pFanin0 = Aig_ObjFanin0(pObj);
pFanin1 = Aig_ObjFanin1(pObj);
Aig_ObjDelete( p, pObj );
if ( pFanin0 && !Aig_ObjIsNone(pFanin0) && Aig_ObjRefs(pFanin0) == 0 )
Aig_ObjDelete_rec( p, pFanin0 );
if ( pFanin1 && !Aig_ObjIsNone(pFanin1) && Aig_ObjRefs(pFanin1) == 0 )
Aig_ObjDelete_rec( p, pFanin1 );
assert( Hop_ObjIsNode(pObj) );
pFanin0 = Hop_ObjFanin0(pObj);
pFanin1 = Hop_ObjFanin1(pObj);
Hop_ObjDelete( p, pObj );
if ( pFanin0 && !Hop_ObjIsNone(pFanin0) && Hop_ObjRefs(pFanin0) == 0 )
Hop_ObjDelete_rec( p, pFanin0 );
if ( pFanin1 && !Hop_ObjIsNone(pFanin1) && Hop_ObjRefs(pFanin1) == 0 )
Hop_ObjDelete_rec( p, pFanin1 );
}
////////////////////////////////////////////////////////////////////////

178
src/temp/aig_free/aigOper.c → src/aig/hop/hopOper.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigOper.c]
FileName [hopOper.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,31 +14,31 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigOper.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopOper.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
// procedure to detect an EXOR gate
static inline int Aig_ObjIsExorType( Aig_Obj_t * p0, Aig_Obj_t * p1, Aig_Obj_t ** ppFan0, Aig_Obj_t ** ppFan1 )
static inline int Hop_ObjIsExorType( Hop_Obj_t * p0, Hop_Obj_t * p1, Hop_Obj_t ** ppFan0, Hop_Obj_t ** ppFan1 )
{
if ( !Aig_IsComplement(p0) || !Aig_IsComplement(p1) )
if ( !Hop_IsComplement(p0) || !Hop_IsComplement(p1) )
return 0;
p0 = Aig_Regular(p0);
p1 = Aig_Regular(p1);
if ( !Aig_ObjIsAnd(p0) || !Aig_ObjIsAnd(p1) )
p0 = Hop_Regular(p0);
p1 = Hop_Regular(p1);
if ( !Hop_ObjIsAnd(p0) || !Hop_ObjIsAnd(p1) )
return 0;
if ( Aig_ObjFanin0(p0) != Aig_ObjFanin0(p1) || Aig_ObjFanin1(p0) != Aig_ObjFanin1(p1) )
if ( Hop_ObjFanin0(p0) != Hop_ObjFanin0(p1) || Hop_ObjFanin1(p0) != Hop_ObjFanin1(p1) )
return 0;
if ( Aig_ObjFaninC0(p0) == Aig_ObjFaninC0(p1) || Aig_ObjFaninC1(p0) == Aig_ObjFaninC1(p1) )
if ( Hop_ObjFaninC0(p0) == Hop_ObjFaninC0(p1) || Hop_ObjFaninC1(p0) == Hop_ObjFaninC1(p1) )
return 0;
*ppFan0 = Aig_ObjChild0(p0);
*ppFan1 = Aig_ObjChild1(p0);
*ppFan0 = Hop_ObjChild0(p0);
*ppFan1 = Hop_ObjChild1(p0);
return 1;
}
@ -57,13 +57,13 @@ static inline int Aig_ObjIsExorType( Aig_Obj_t * p0, Aig_Obj_t * p1, Aig_Obj_t *
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_IthVar( Aig_Man_t * p, int i )
Hop_Obj_t * Hop_IthVar( Hop_Man_t * p, int i )
{
int v;
for ( v = Aig_ManPiNum(p); v <= i; v++ )
Aig_ObjCreatePi( p );
for ( v = Hop_ManPiNum(p); v <= i; v++ )
Hop_ObjCreatePi( p );
assert( i < Vec_PtrSize(p->vPis) );
return Aig_ManPi( p, i );
return Hop_ManPi( p, i );
}
/**Function*************************************************************
@ -77,12 +77,12 @@ Aig_Obj_t * Aig_IthVar( Aig_Man_t * p, int i )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Oper( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1, Aig_Type_t Type )
Hop_Obj_t * Hop_Oper( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1, Hop_Type_t Type )
{
if ( Type == AIG_AND )
return Aig_And( p, p0, p1 );
return Hop_And( p, p0, p1 );
if ( Type == AIG_EXOR )
return Aig_Exor( p, p0, p1 );
return Hop_Exor( p, p0, p1 );
assert( 0 );
return NULL;
}
@ -98,27 +98,27 @@ Aig_Obj_t * Aig_Oper( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1, Aig_Type_t
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_And( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
Hop_Obj_t * Hop_And( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1 )
{
Aig_Obj_t * pGhost, * pResult;
// Aig_Obj_t * pFan0, * pFan1;
Hop_Obj_t * pGhost, * pResult;
// Hop_Obj_t * pFan0, * pFan1;
// check trivial cases
if ( p0 == p1 )
return p0;
if ( p0 == Aig_Not(p1) )
return Aig_Not(p->pConst1);
if ( Aig_Regular(p0) == p->pConst1 )
return p0 == p->pConst1 ? p1 : Aig_Not(p->pConst1);
if ( Aig_Regular(p1) == p->pConst1 )
return p1 == p->pConst1 ? p0 : Aig_Not(p->pConst1);
if ( p0 == Hop_Not(p1) )
return Hop_Not(p->pConst1);
if ( Hop_Regular(p0) == p->pConst1 )
return p0 == p->pConst1 ? p1 : Hop_Not(p->pConst1);
if ( Hop_Regular(p1) == p->pConst1 )
return p1 == p->pConst1 ? p0 : Hop_Not(p->pConst1);
// check if it can be an EXOR gate
// if ( Aig_ObjIsExorType( p0, p1, &pFan0, &pFan1 ) )
// return Aig_Exor( p, pFan0, pFan1 );
// if ( Hop_ObjIsExorType( p0, p1, &pFan0, &pFan1 ) )
// return Hop_Exor( p, pFan0, pFan1 );
// check the table
pGhost = Aig_ObjCreateGhost( p, p0, p1, AIG_AND );
if ( pResult = Aig_TableLookup( p, pGhost ) )
pGhost = Hop_ObjCreateGhost( p, p0, p1, AIG_AND );
if ( pResult = Hop_TableLookup( p, pGhost ) )
return pResult;
return Aig_ObjCreate( p, pGhost );
return Hop_ObjCreate( p, pGhost );
}
/**Function*************************************************************
@ -132,26 +132,26 @@ Aig_Obj_t * Aig_And( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Exor( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
Hop_Obj_t * Hop_Exor( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1 )
{
/*
Aig_Obj_t * pGhost, * pResult;
Hop_Obj_t * pGhost, * pResult;
// check trivial cases
if ( p0 == p1 )
return Aig_Not(p->pConst1);
if ( p0 == Aig_Not(p1) )
return Hop_Not(p->pConst1);
if ( p0 == Hop_Not(p1) )
return p->pConst1;
if ( Aig_Regular(p0) == p->pConst1 )
return Aig_NotCond( p1, p0 == p->pConst1 );
if ( Aig_Regular(p1) == p->pConst1 )
return Aig_NotCond( p0, p1 == p->pConst1 );
if ( Hop_Regular(p0) == p->pConst1 )
return Hop_NotCond( p1, p0 == p->pConst1 );
if ( Hop_Regular(p1) == p->pConst1 )
return Hop_NotCond( p0, p1 == p->pConst1 );
// check the table
pGhost = Aig_ObjCreateGhost( p, p0, p1, AIG_EXOR );
if ( pResult = Aig_TableLookup( p, pGhost ) )
pGhost = Hop_ObjCreateGhost( p, p0, p1, AIG_EXOR );
if ( pResult = Hop_TableLookup( p, pGhost ) )
return pResult;
return Aig_ObjCreate( p, pGhost );
return Hop_ObjCreate( p, pGhost );
*/
return Aig_Or( p, Aig_And(p, p0, Aig_Not(p1)), Aig_And(p, Aig_Not(p0), p1) );
return Hop_Or( p, Hop_And(p, p0, Hop_Not(p1)), Hop_And(p, Hop_Not(p0), p1) );
}
/**Function*************************************************************
@ -165,9 +165,9 @@ Aig_Obj_t * Aig_Exor( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Or( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
Hop_Obj_t * Hop_Or( Hop_Man_t * p, Hop_Obj_t * p0, Hop_Obj_t * p1 )
{
return Aig_Not( Aig_And( p, Aig_Not(p0), Aig_Not(p1) ) );
return Hop_Not( Hop_And( p, Hop_Not(p0), Hop_Not(p1) ) );
}
/**Function*************************************************************
@ -181,48 +181,48 @@ Aig_Obj_t * Aig_Or( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Mux( Aig_Man_t * p, Aig_Obj_t * pC, Aig_Obj_t * p1, Aig_Obj_t * p0 )
Hop_Obj_t * Hop_Mux( Hop_Man_t * p, Hop_Obj_t * pC, Hop_Obj_t * p1, Hop_Obj_t * p0 )
{
/*
Aig_Obj_t * pTempA1, * pTempA2, * pTempB1, * pTempB2, * pTemp;
Hop_Obj_t * pTempA1, * pTempA2, * pTempB1, * pTempB2, * pTemp;
int Count0, Count1;
// consider trivial cases
if ( p0 == Aig_Not(p1) )
return Aig_Exor( p, pC, p0 );
if ( p0 == Hop_Not(p1) )
return Hop_Exor( p, pC, p0 );
// other cases can be added
// implement the first MUX (F = C * x1 + C' * x0)
// check for constants here!!!
pTempA1 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, pC, p1, AIG_AND) );
pTempA2 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pC), p0, AIG_AND) );
pTempA1 = Hop_TableLookup( p, Hop_ObjCreateGhost(p, pC, p1, AIG_AND) );
pTempA2 = Hop_TableLookup( p, Hop_ObjCreateGhost(p, Hop_Not(pC), p0, AIG_AND) );
if ( pTempA1 && pTempA2 )
{
pTemp = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pTempA1), Aig_Not(pTempA2), AIG_AND) );
if ( pTemp ) return Aig_Not(pTemp);
pTemp = Hop_TableLookup( p, Hop_ObjCreateGhost(p, Hop_Not(pTempA1), Hop_Not(pTempA2), AIG_AND) );
if ( pTemp ) return Hop_Not(pTemp);
}
Count0 = (pTempA1 != NULL) + (pTempA2 != NULL);
// implement the second MUX (F' = C * x1' + C' * x0')
pTempB1 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, pC, Aig_Not(p1), AIG_AND) );
pTempB2 = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pC), Aig_Not(p0), AIG_AND) );
pTempB1 = Hop_TableLookup( p, Hop_ObjCreateGhost(p, pC, Hop_Not(p1), AIG_AND) );
pTempB2 = Hop_TableLookup( p, Hop_ObjCreateGhost(p, Hop_Not(pC), Hop_Not(p0), AIG_AND) );
if ( pTempB1 && pTempB2 )
{
pTemp = Aig_TableLookup( p, Aig_ObjCreateGhost(p, Aig_Not(pTempB1), Aig_Not(pTempB2), AIG_AND) );
pTemp = Hop_TableLookup( p, Hop_ObjCreateGhost(p, Hop_Not(pTempB1), Hop_Not(pTempB2), AIG_AND) );
if ( pTemp ) return pTemp;
}
Count1 = (pTempB1 != NULL) + (pTempB2 != NULL);
// compare and decide which one to implement
if ( Count0 >= Count1 )
{
pTempA1 = pTempA1? pTempA1 : Aig_And(p, pC, p1);
pTempA2 = pTempA2? pTempA2 : Aig_And(p, Aig_Not(pC), p0);
return Aig_Or( p, pTempA1, pTempA2 );
pTempA1 = pTempA1? pTempA1 : Hop_And(p, pC, p1);
pTempA2 = pTempA2? pTempA2 : Hop_And(p, Hop_Not(pC), p0);
return Hop_Or( p, pTempA1, pTempA2 );
}
pTempB1 = pTempB1? pTempB1 : Aig_And(p, pC, Aig_Not(p1));
pTempB2 = pTempB2? pTempB2 : Aig_And(p, Aig_Not(pC), Aig_Not(p0));
return Aig_Not( Aig_Or( p, pTempB1, pTempB2 ) );
pTempB1 = pTempB1? pTempB1 : Hop_And(p, pC, Hop_Not(p1));
pTempB2 = pTempB2? pTempB2 : Hop_And(p, Hop_Not(pC), Hop_Not(p0));
return Hop_Not( Hop_Or( p, pTempB1, pTempB2 ) );
*/
return Aig_Or( p, Aig_And(p, pC, p1), Aig_And(p, Aig_Not(pC), p0) );
return Hop_Or( p, Hop_And(p, pC, p1), Hop_And(p, Hop_Not(pC), p0) );
}
/**Function*************************************************************
@ -236,9 +236,9 @@ Aig_Obj_t * Aig_Mux( Aig_Man_t * p, Aig_Obj_t * pC, Aig_Obj_t * p1, Aig_Obj_t *
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Maj( Aig_Man_t * p, Aig_Obj_t * pA, Aig_Obj_t * pB, Aig_Obj_t * pC )
Hop_Obj_t * Hop_Maj( Hop_Man_t * p, Hop_Obj_t * pA, Hop_Obj_t * pB, Hop_Obj_t * pC )
{
return Aig_Or( p, Aig_Or(p, Aig_And(p, pA, pB), Aig_And(p, pA, pC)), Aig_And(p, pB, pC) );
return Hop_Or( p, Hop_Or(p, Hop_And(p, pA, pB), Hop_And(p, pA, pC)), Hop_And(p, pB, pC) );
}
/**Function*************************************************************
@ -252,14 +252,14 @@ Aig_Obj_t * Aig_Maj( Aig_Man_t * p, Aig_Obj_t * pA, Aig_Obj_t * pB, Aig_Obj_t *
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Multi_rec( Aig_Man_t * p, Aig_Obj_t ** ppObjs, int nObjs, Aig_Type_t Type )
Hop_Obj_t * Hop_Multi_rec( Hop_Man_t * p, Hop_Obj_t ** ppObjs, int nObjs, Hop_Type_t Type )
{
Aig_Obj_t * pObj1, * pObj2;
Hop_Obj_t * pObj1, * pObj2;
if ( nObjs == 1 )
return ppObjs[0];
pObj1 = Aig_Multi_rec( p, ppObjs, nObjs/2, Type );
pObj2 = Aig_Multi_rec( p, ppObjs + nObjs/2, nObjs - nObjs/2, Type );
return Aig_Oper( p, pObj1, pObj2, Type );
pObj1 = Hop_Multi_rec( p, ppObjs, nObjs/2, Type );
pObj2 = Hop_Multi_rec( p, ppObjs + nObjs/2, nObjs - nObjs/2, Type );
return Hop_Oper( p, pObj1, pObj2, Type );
}
/**Function*************************************************************
@ -273,11 +273,11 @@ Aig_Obj_t * Aig_Multi_rec( Aig_Man_t * p, Aig_Obj_t ** ppObjs, int nObjs, Aig_Ty
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Multi( Aig_Man_t * p, Aig_Obj_t ** pArgs, int nArgs, Aig_Type_t Type )
Hop_Obj_t * Hop_Multi( Hop_Man_t * p, Hop_Obj_t ** pArgs, int nArgs, Hop_Type_t Type )
{
assert( Type == AIG_AND || Type == AIG_EXOR );
assert( nArgs > 0 );
return Aig_Multi_rec( p, pArgs, nArgs, Type );
return Hop_Multi_rec( p, pArgs, nArgs, Type );
}
/**Function*************************************************************
@ -291,16 +291,16 @@ Aig_Obj_t * Aig_Multi( Aig_Man_t * p, Aig_Obj_t ** pArgs, int nArgs, Aig_Type_t
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_Miter( Aig_Man_t * p, Vec_Ptr_t * vPairs )
Hop_Obj_t * Hop_Miter( Hop_Man_t * p, Vec_Ptr_t * vPairs )
{
int i;
assert( vPairs->nSize > 0 );
assert( vPairs->nSize % 2 == 0 );
// go through the cubes of the node's SOP
for ( i = 0; i < vPairs->nSize; i += 2 )
vPairs->pArray[i/2] = Aig_Not( Aig_Exor( p, vPairs->pArray[i], vPairs->pArray[i+1] ) );
vPairs->pArray[i/2] = Hop_Not( Hop_Exor( p, vPairs->pArray[i], vPairs->pArray[i+1] ) );
vPairs->nSize = vPairs->nSize/2;
return Aig_Not( Aig_Multi_rec( p, (Aig_Obj_t **)vPairs->pArray, vPairs->nSize, AIG_AND ) );
return Hop_Not( Hop_Multi_rec( p, (Hop_Obj_t **)vPairs->pArray, vPairs->nSize, AIG_AND ) );
}
/**Function*************************************************************
@ -314,13 +314,13 @@ Aig_Obj_t * Aig_Miter( Aig_Man_t * p, Vec_Ptr_t * vPairs )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_CreateAnd( Aig_Man_t * p, int nVars )
Hop_Obj_t * Hop_CreateAnd( Hop_Man_t * p, int nVars )
{
Aig_Obj_t * pFunc;
Hop_Obj_t * pFunc;
int i;
pFunc = Aig_ManConst1( p );
pFunc = Hop_ManConst1( p );
for ( i = 0; i < nVars; i++ )
pFunc = Aig_And( p, pFunc, Aig_IthVar(p, i) );
pFunc = Hop_And( p, pFunc, Hop_IthVar(p, i) );
return pFunc;
}
@ -335,13 +335,13 @@ Aig_Obj_t * Aig_CreateAnd( Aig_Man_t * p, int nVars )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_CreateOr( Aig_Man_t * p, int nVars )
Hop_Obj_t * Hop_CreateOr( Hop_Man_t * p, int nVars )
{
Aig_Obj_t * pFunc;
Hop_Obj_t * pFunc;
int i;
pFunc = Aig_ManConst0( p );
pFunc = Hop_ManConst0( p );
for ( i = 0; i < nVars; i++ )
pFunc = Aig_Or( p, pFunc, Aig_IthVar(p, i) );
pFunc = Hop_Or( p, pFunc, Hop_IthVar(p, i) );
return pFunc;
}
@ -356,13 +356,13 @@ Aig_Obj_t * Aig_CreateOr( Aig_Man_t * p, int nVars )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_CreateExor( Aig_Man_t * p, int nVars )
Hop_Obj_t * Hop_CreateExor( Hop_Man_t * p, int nVars )
{
Aig_Obj_t * pFunc;
Hop_Obj_t * pFunc;
int i;
pFunc = Aig_ManConst0( p );
pFunc = Hop_ManConst0( p );
for ( i = 0; i < nVars; i++ )
pFunc = Aig_Exor( p, pFunc, Aig_IthVar(p, i) );
pFunc = Hop_Exor( p, pFunc, Hop_IthVar(p, i) );
return pFunc;
}

88
src/temp/aig/aigTable.c → src/aig/hop/hopTable.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigTable.c]
FileName [hopTable.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,40 +14,40 @@
Date [Ver. 1.0. Started - May 11, 2006. ]
Revision [$Id: aigTable.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopTable.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
// hashing the node
static unsigned long Aig_Hash( Aig_Obj_t * pObj, int TableSize )
static unsigned long Hop_Hash( Hop_Obj_t * pObj, int TableSize )
{
unsigned long Key = Aig_ObjIsExor(pObj) * 1699;
Key ^= (long)Aig_ObjFanin0(pObj) * 7937;
Key ^= (long)Aig_ObjFanin1(pObj) * 2971;
Key ^= Aig_ObjFaninC0(pObj) * 911;
Key ^= Aig_ObjFaninC1(pObj) * 353;
unsigned long Key = Hop_ObjIsExor(pObj) * 1699;
Key ^= (long)Hop_ObjFanin0(pObj) * 7937;
Key ^= (long)Hop_ObjFanin1(pObj) * 2971;
Key ^= Hop_ObjFaninC0(pObj) * 911;
Key ^= Hop_ObjFaninC1(pObj) * 353;
return Key % TableSize;
}
// returns the place where this node is stored (or should be stored)
static Aig_Obj_t ** Aig_TableFind( Aig_Man_t * p, Aig_Obj_t * pObj )
static Hop_Obj_t ** Hop_TableFind( Hop_Man_t * p, Hop_Obj_t * pObj )
{
int i;
assert( Aig_ObjChild0(pObj) && Aig_ObjChild1(pObj) );
assert( Aig_ObjChild0(pObj) < Aig_ObjChild1(pObj) );
for ( i = Aig_Hash(pObj, p->nTableSize); p->pTable[i]; i = (i+1) % p->nTableSize )
assert( Hop_ObjChild0(pObj) && Hop_ObjChild1(pObj) );
assert( Hop_ObjChild0(pObj) < Hop_ObjChild1(pObj) );
for ( i = Hop_Hash(pObj, p->nTableSize); p->pTable[i]; i = (i+1) % p->nTableSize )
if ( p->pTable[i] == pObj )
break;
return p->pTable + i;
}
static void Aig_TableResize( Aig_Man_t * p );
static void Hop_TableResize( Hop_Man_t * p );
static unsigned int Cudd_PrimeAig( unsigned int p );
////////////////////////////////////////////////////////////////////////
@ -65,19 +65,19 @@ static unsigned int Cudd_PrimeAig( unsigned int p );
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_TableLookup( Aig_Man_t * p, Aig_Obj_t * pGhost )
Hop_Obj_t * Hop_TableLookup( Hop_Man_t * p, Hop_Obj_t * pGhost )
{
int i;
assert( !Aig_IsComplement(pGhost) );
assert( Aig_ObjChild0(pGhost) && Aig_ObjChild1(pGhost) );
assert( Aig_ObjChild0(pGhost) < Aig_ObjChild1(pGhost) );
if ( p->fRefCount && (!Aig_ObjRefs(Aig_ObjFanin0(pGhost)) || !Aig_ObjRefs(Aig_ObjFanin1(pGhost))) )
assert( !Hop_IsComplement(pGhost) );
assert( Hop_ObjChild0(pGhost) && Hop_ObjChild1(pGhost) );
assert( Hop_ObjChild0(pGhost) < Hop_ObjChild1(pGhost) );
if ( p->fRefCount && (!Hop_ObjRefs(Hop_ObjFanin0(pGhost)) || !Hop_ObjRefs(Hop_ObjFanin1(pGhost))) )
return NULL;
for ( i = Aig_Hash(pGhost, p->nTableSize); p->pTable[i]; i = (i+1) % p->nTableSize )
for ( i = Hop_Hash(pGhost, p->nTableSize); p->pTable[i]; i = (i+1) % p->nTableSize )
{
if ( Aig_ObjChild0(p->pTable[i]) == Aig_ObjChild0(pGhost) &&
Aig_ObjChild1(p->pTable[i]) == Aig_ObjChild1(pGhost) &&
Aig_ObjType(p->pTable[i]) == Aig_ObjType(pGhost) )
if ( Hop_ObjChild0(p->pTable[i]) == Hop_ObjChild0(pGhost) &&
Hop_ObjChild1(p->pTable[i]) == Hop_ObjChild1(pGhost) &&
Hop_ObjType(p->pTable[i]) == Hop_ObjType(pGhost) )
return p->pTable[i];
}
return NULL;
@ -94,14 +94,14 @@ Aig_Obj_t * Aig_TableLookup( Aig_Man_t * p, Aig_Obj_t * pGhost )
SeeAlso []
***********************************************************************/
void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj )
void Hop_TableInsert( Hop_Man_t * p, Hop_Obj_t * pObj )
{
Aig_Obj_t ** ppPlace;
assert( !Aig_IsComplement(pObj) );
assert( Aig_TableLookup(p, pObj) == NULL );
if ( p->nTableSize < 2 * Aig_ManNodeNum(p) )
Aig_TableResize( p );
ppPlace = Aig_TableFind( p, pObj );
Hop_Obj_t ** ppPlace;
assert( !Hop_IsComplement(pObj) );
assert( Hop_TableLookup(p, pObj) == NULL );
if ( p->nTableSize < 2 * Hop_ManNodeNum(p) )
Hop_TableResize( p );
ppPlace = Hop_TableFind( p, pObj );
assert( *ppPlace == NULL );
*ppPlace = pObj;
}
@ -117,12 +117,12 @@ void Aig_TableInsert( Aig_Man_t * p, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj )
void Hop_TableDelete( Hop_Man_t * p, Hop_Obj_t * pObj )
{
Aig_Obj_t * pEntry, ** ppPlace;
Hop_Obj_t * pEntry, ** ppPlace;
int i;
assert( !Aig_IsComplement(pObj) );
ppPlace = Aig_TableFind( p, pObj );
assert( !Hop_IsComplement(pObj) );
ppPlace = Hop_TableFind( p, pObj );
assert( *ppPlace == pObj ); // node should be in the table
*ppPlace = NULL;
// rehash the adjacent entries
@ -131,7 +131,7 @@ void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj )
{
pEntry = p->pTable[i];
p->pTable[i] = 0;
Aig_TableInsert( p, pEntry );
Hop_TableInsert( p, pEntry );
}
}
@ -146,7 +146,7 @@ void Aig_TableDelete( Aig_Man_t * p, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
int Aig_TableCountEntries( Aig_Man_t * p )
int Hop_TableCountEntries( Hop_Man_t * p )
{
int i, Counter = 0;
for ( i = 0; i < p->nTableSize; i++ )
@ -165,18 +165,18 @@ int Aig_TableCountEntries( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_TableResize( Aig_Man_t * p )
void Hop_TableResize( Hop_Man_t * p )
{
Aig_Obj_t ** pTableOld, ** ppPlace;
Hop_Obj_t ** pTableOld, ** ppPlace;
int nTableSizeOld, Counter, nEntries, e, clk;
clk = clock();
// save the old table
pTableOld = p->pTable;
nTableSizeOld = p->nTableSize;
// get the new table
p->nTableSize = Cudd_PrimeAig( 5 * Aig_ManNodeNum(p) );
p->pTable = ALLOC( Aig_Obj_t *, p->nTableSize );
memset( p->pTable, 0, sizeof(Aig_Obj_t *) * p->nTableSize );
p->nTableSize = Cudd_PrimeAig( 5 * Hop_ManNodeNum(p) );
p->pTable = ALLOC( Hop_Obj_t *, p->nTableSize );
memset( p->pTable, 0, sizeof(Hop_Obj_t *) * p->nTableSize );
// rehash the entries from the old table
Counter = 0;
for ( e = 0; e < nTableSizeOld; e++ )
@ -185,11 +185,11 @@ clk = clock();
continue;
Counter++;
// get the place where this entry goes in the table table
ppPlace = Aig_TableFind( p, pTableOld[e] );
ppPlace = Hop_TableFind( p, pTableOld[e] );
assert( *ppPlace == NULL ); // should not be in the table
*ppPlace = pTableOld[e];
}
nEntries = Aig_ManNodeNum(p);
nEntries = Hop_ManNodeNum(p);
// assert( Counter == nEntries );
// printf( "Increasing the structural table size from %6d to %6d. ", nTableSizeOld, p->nTableSize );
// PRT( "Time", clock() - clk );
@ -208,7 +208,7 @@ clk = clock();
SeeAlso []
******************************************************************************/
void Aig_TableProfile( Aig_Man_t * p )
void Hop_TableProfile( Hop_Man_t * p )
{
int i, Counter = 0;
for ( i = 0; i < p->nTableSize; i++ )

272
src/temp/aig/aigUtil.c → src/aig/hop/hopUtil.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigUtil.c]
FileName [hopUtil.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,11 +14,11 @@
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: aigUtil.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
Revision [$Id: hopUtil.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "aig.h"
#include "hop.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -39,10 +39,10 @@
SeeAlso []
***********************************************************************/
void Aig_ManIncrementTravId( Aig_Man_t * p )
void Hop_ManIncrementTravId( Hop_Man_t * p )
{
if ( p->nTravIds >= (1<<30)-1 )
Aig_ManCleanData( p );
Hop_ManCleanData( p );
p->nTravIds++;
}
@ -57,17 +57,17 @@ void Aig_ManIncrementTravId( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ManCleanData( Aig_Man_t * p )
void Hop_ManCleanData( Hop_Man_t * p )
{
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
p->nTravIds = 1;
Aig_ManConst1(p)->pData = NULL;
Aig_ManForEachPi( p, pObj, i )
Hop_ManConst1(p)->pData = NULL;
Hop_ManForEachPi( p, pObj, i )
pObj->pData = NULL;
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
pObj->pData = NULL;
Aig_ManForEachNode( p, pObj, i )
Hop_ManForEachNode( p, pObj, i )
pObj->pData = NULL;
}
@ -82,15 +82,15 @@ void Aig_ManCleanData( Aig_Man_t * p )
SeeAlso []
***********************************************************************/
void Aig_ObjCollectMulti_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
void Hop_ObjCollectMulti_rec( Hop_Obj_t * pRoot, Hop_Obj_t * pObj, Vec_Ptr_t * vSuper )
{
if ( pRoot != pObj && (Aig_IsComplement(pObj) || Aig_ObjIsPi(pObj) || Aig_ObjType(pRoot) != Aig_ObjType(pObj)) )
if ( pRoot != pObj && (Hop_IsComplement(pObj) || Hop_ObjIsPi(pObj) || Hop_ObjType(pRoot) != Hop_ObjType(pObj)) )
{
Vec_PtrPushUnique(vSuper, pObj);
return;
}
Aig_ObjCollectMulti_rec( pRoot, Aig_ObjChild0(pObj), vSuper );
Aig_ObjCollectMulti_rec( pRoot, Aig_ObjChild1(pObj), vSuper );
Hop_ObjCollectMulti_rec( pRoot, Hop_ObjChild0(pObj), vSuper );
Hop_ObjCollectMulti_rec( pRoot, Hop_ObjChild1(pObj), vSuper );
}
/**Function*************************************************************
@ -104,11 +104,11 @@ void Aig_ObjCollectMulti_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * v
SeeAlso []
***********************************************************************/
void Aig_ObjCollectMulti( Aig_Obj_t * pRoot, Vec_Ptr_t * vSuper )
void Hop_ObjCollectMulti( Hop_Obj_t * pRoot, Vec_Ptr_t * vSuper )
{
assert( !Aig_IsComplement(pRoot) );
assert( !Hop_IsComplement(pRoot) );
Vec_PtrClear( vSuper );
Aig_ObjCollectMulti_rec( pRoot, pRoot, vSuper );
Hop_ObjCollectMulti_rec( pRoot, pRoot, vSuper );
}
/**Function*************************************************************
@ -122,28 +122,28 @@ void Aig_ObjCollectMulti( Aig_Obj_t * pRoot, Vec_Ptr_t * vSuper )
SeeAlso []
***********************************************************************/
int Aig_ObjIsMuxType( Aig_Obj_t * pNode )
int Hop_ObjIsMuxType( Hop_Obj_t * pNode )
{
Aig_Obj_t * pNode0, * pNode1;
Hop_Obj_t * pNode0, * pNode1;
// check that the node is regular
assert( !Aig_IsComplement(pNode) );
assert( !Hop_IsComplement(pNode) );
// if the node is not AND, this is not MUX
if ( !Aig_ObjIsAnd(pNode) )
if ( !Hop_ObjIsAnd(pNode) )
return 0;
// if the children are not complemented, this is not MUX
if ( !Aig_ObjFaninC0(pNode) || !Aig_ObjFaninC1(pNode) )
if ( !Hop_ObjFaninC0(pNode) || !Hop_ObjFaninC1(pNode) )
return 0;
// get children
pNode0 = Aig_ObjFanin0(pNode);
pNode1 = Aig_ObjFanin1(pNode);
pNode0 = Hop_ObjFanin0(pNode);
pNode1 = Hop_ObjFanin1(pNode);
// if the children are not ANDs, this is not MUX
if ( !Aig_ObjIsAnd(pNode0) || !Aig_ObjIsAnd(pNode1) )
if ( !Hop_ObjIsAnd(pNode0) || !Hop_ObjIsAnd(pNode1) )
return 0;
// otherwise the node is MUX iff it has a pair of equal grandchildren
return (Aig_ObjFanin0(pNode0) == Aig_ObjFanin0(pNode1) && (Aig_ObjFaninC0(pNode0) ^ Aig_ObjFaninC0(pNode1))) ||
(Aig_ObjFanin0(pNode0) == Aig_ObjFanin1(pNode1) && (Aig_ObjFaninC0(pNode0) ^ Aig_ObjFaninC1(pNode1))) ||
(Aig_ObjFanin1(pNode0) == Aig_ObjFanin0(pNode1) && (Aig_ObjFaninC1(pNode0) ^ Aig_ObjFaninC0(pNode1))) ||
(Aig_ObjFanin1(pNode0) == Aig_ObjFanin1(pNode1) && (Aig_ObjFaninC1(pNode0) ^ Aig_ObjFaninC1(pNode1)));
return (Hop_ObjFanin0(pNode0) == Hop_ObjFanin0(pNode1) && (Hop_ObjFaninC0(pNode0) ^ Hop_ObjFaninC0(pNode1))) ||
(Hop_ObjFanin0(pNode0) == Hop_ObjFanin1(pNode1) && (Hop_ObjFaninC0(pNode0) ^ Hop_ObjFaninC1(pNode1))) ||
(Hop_ObjFanin1(pNode0) == Hop_ObjFanin0(pNode1) && (Hop_ObjFaninC1(pNode0) ^ Hop_ObjFaninC0(pNode1))) ||
(Hop_ObjFanin1(pNode0) == Hop_ObjFanin1(pNode1) && (Hop_ObjFaninC1(pNode0) ^ Hop_ObjFaninC1(pNode1)));
}
@ -158,33 +158,33 @@ int Aig_ObjIsMuxType( Aig_Obj_t * pNode )
SeeAlso []
***********************************************************************/
int Aig_ObjRecognizeExor( Aig_Obj_t * pObj, Aig_Obj_t ** ppFan0, Aig_Obj_t ** ppFan1 )
int Hop_ObjRecognizeExor( Hop_Obj_t * pObj, Hop_Obj_t ** ppFan0, Hop_Obj_t ** ppFan1 )
{
Aig_Obj_t * p0, * p1;
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) )
Hop_Obj_t * p0, * p1;
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) )
return 0;
if ( Aig_ObjIsExor(pObj) )
if ( Hop_ObjIsExor(pObj) )
{
*ppFan0 = Aig_ObjChild0(pObj);
*ppFan1 = Aig_ObjChild1(pObj);
*ppFan0 = Hop_ObjChild0(pObj);
*ppFan1 = Hop_ObjChild1(pObj);
return 1;
}
assert( Aig_ObjIsAnd(pObj) );
p0 = Aig_ObjChild0(pObj);
p1 = Aig_ObjChild1(pObj);
if ( !Aig_IsComplement(p0) || !Aig_IsComplement(p1) )
assert( Hop_ObjIsAnd(pObj) );
p0 = Hop_ObjChild0(pObj);
p1 = Hop_ObjChild1(pObj);
if ( !Hop_IsComplement(p0) || !Hop_IsComplement(p1) )
return 0;
p0 = Aig_Regular(p0);
p1 = Aig_Regular(p1);
if ( !Aig_ObjIsAnd(p0) || !Aig_ObjIsAnd(p1) )
p0 = Hop_Regular(p0);
p1 = Hop_Regular(p1);
if ( !Hop_ObjIsAnd(p0) || !Hop_ObjIsAnd(p1) )
return 0;
if ( Aig_ObjFanin0(p0) != Aig_ObjFanin0(p1) || Aig_ObjFanin1(p0) != Aig_ObjFanin1(p1) )
if ( Hop_ObjFanin0(p0) != Hop_ObjFanin0(p1) || Hop_ObjFanin1(p0) != Hop_ObjFanin1(p1) )
return 0;
if ( Aig_ObjFaninC0(p0) == Aig_ObjFaninC0(p1) || Aig_ObjFaninC1(p0) == Aig_ObjFaninC1(p1) )
if ( Hop_ObjFaninC0(p0) == Hop_ObjFaninC0(p1) || Hop_ObjFaninC1(p0) == Hop_ObjFaninC1(p1) )
return 0;
*ppFan0 = Aig_ObjChild0(p0);
*ppFan1 = Aig_ObjChild1(p0);
*ppFan0 = Hop_ObjChild0(p0);
*ppFan1 = Hop_ObjChild1(p0);
return 1;
}
@ -202,78 +202,78 @@ int Aig_ObjRecognizeExor( Aig_Obj_t * pObj, Aig_Obj_t ** ppFan0, Aig_Obj_t ** pp
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ObjRecognizeMux( Aig_Obj_t * pNode, Aig_Obj_t ** ppNodeT, Aig_Obj_t ** ppNodeE )
Hop_Obj_t * Hop_ObjRecognizeMux( Hop_Obj_t * pNode, Hop_Obj_t ** ppNodeT, Hop_Obj_t ** ppNodeE )
{
Aig_Obj_t * pNode0, * pNode1;
assert( !Aig_IsComplement(pNode) );
assert( Aig_ObjIsMuxType(pNode) );
Hop_Obj_t * pNode0, * pNode1;
assert( !Hop_IsComplement(pNode) );
assert( Hop_ObjIsMuxType(pNode) );
// get children
pNode0 = Aig_ObjFanin0(pNode);
pNode1 = Aig_ObjFanin1(pNode);
pNode0 = Hop_ObjFanin0(pNode);
pNode1 = Hop_ObjFanin1(pNode);
// find the control variable
if ( Aig_ObjFanin1(pNode0) == Aig_ObjFanin1(pNode1) && (Aig_ObjFaninC1(pNode0) ^ Aig_ObjFaninC1(pNode1)) )
if ( Hop_ObjFanin1(pNode0) == Hop_ObjFanin1(pNode1) && (Hop_ObjFaninC1(pNode0) ^ Hop_ObjFaninC1(pNode1)) )
{
// if ( Fraig_IsComplement(pNode1->p2) )
if ( Aig_ObjFaninC1(pNode0) )
if ( Hop_ObjFaninC1(pNode0) )
{ // pNode2->p2 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild0(pNode1));//pNode2->p1);
*ppNodeE = Aig_Not(Aig_ObjChild0(pNode0));//pNode1->p1);
return Aig_ObjChild1(pNode1);//pNode2->p2;
*ppNodeT = Hop_Not(Hop_ObjChild0(pNode1));//pNode2->p1);
*ppNodeE = Hop_Not(Hop_ObjChild0(pNode0));//pNode1->p1);
return Hop_ObjChild1(pNode1);//pNode2->p2;
}
else
{ // pNode1->p2 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild0(pNode0));//pNode1->p1);
*ppNodeE = Aig_Not(Aig_ObjChild0(pNode1));//pNode2->p1);
return Aig_ObjChild1(pNode0);//pNode1->p2;
*ppNodeT = Hop_Not(Hop_ObjChild0(pNode0));//pNode1->p1);
*ppNodeE = Hop_Not(Hop_ObjChild0(pNode1));//pNode2->p1);
return Hop_ObjChild1(pNode0);//pNode1->p2;
}
}
else if ( Aig_ObjFanin0(pNode0) == Aig_ObjFanin0(pNode1) && (Aig_ObjFaninC0(pNode0) ^ Aig_ObjFaninC0(pNode1)) )
else if ( Hop_ObjFanin0(pNode0) == Hop_ObjFanin0(pNode1) && (Hop_ObjFaninC0(pNode0) ^ Hop_ObjFaninC0(pNode1)) )
{
// if ( Fraig_IsComplement(pNode1->p1) )
if ( Aig_ObjFaninC0(pNode0) )
if ( Hop_ObjFaninC0(pNode0) )
{ // pNode2->p1 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild1(pNode1));//pNode2->p2);
*ppNodeE = Aig_Not(Aig_ObjChild1(pNode0));//pNode1->p2);
return Aig_ObjChild0(pNode1);//pNode2->p1;
*ppNodeT = Hop_Not(Hop_ObjChild1(pNode1));//pNode2->p2);
*ppNodeE = Hop_Not(Hop_ObjChild1(pNode0));//pNode1->p2);
return Hop_ObjChild0(pNode1);//pNode2->p1;
}
else
{ // pNode1->p1 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild1(pNode0));//pNode1->p2);
*ppNodeE = Aig_Not(Aig_ObjChild1(pNode1));//pNode2->p2);
return Aig_ObjChild0(pNode0);//pNode1->p1;
*ppNodeT = Hop_Not(Hop_ObjChild1(pNode0));//pNode1->p2);
*ppNodeE = Hop_Not(Hop_ObjChild1(pNode1));//pNode2->p2);
return Hop_ObjChild0(pNode0);//pNode1->p1;
}
}
else if ( Aig_ObjFanin0(pNode0) == Aig_ObjFanin1(pNode1) && (Aig_ObjFaninC0(pNode0) ^ Aig_ObjFaninC1(pNode1)) )
else if ( Hop_ObjFanin0(pNode0) == Hop_ObjFanin1(pNode1) && (Hop_ObjFaninC0(pNode0) ^ Hop_ObjFaninC1(pNode1)) )
{
// if ( Fraig_IsComplement(pNode1->p1) )
if ( Aig_ObjFaninC0(pNode0) )
if ( Hop_ObjFaninC0(pNode0) )
{ // pNode2->p2 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild0(pNode1));//pNode2->p1);
*ppNodeE = Aig_Not(Aig_ObjChild1(pNode0));//pNode1->p2);
return Aig_ObjChild1(pNode1);//pNode2->p2;
*ppNodeT = Hop_Not(Hop_ObjChild0(pNode1));//pNode2->p1);
*ppNodeE = Hop_Not(Hop_ObjChild1(pNode0));//pNode1->p2);
return Hop_ObjChild1(pNode1);//pNode2->p2;
}
else
{ // pNode1->p1 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild1(pNode0));//pNode1->p2);
*ppNodeE = Aig_Not(Aig_ObjChild0(pNode1));//pNode2->p1);
return Aig_ObjChild0(pNode0);//pNode1->p1;
*ppNodeT = Hop_Not(Hop_ObjChild1(pNode0));//pNode1->p2);
*ppNodeE = Hop_Not(Hop_ObjChild0(pNode1));//pNode2->p1);
return Hop_ObjChild0(pNode0);//pNode1->p1;
}
}
else if ( Aig_ObjFanin1(pNode0) == Aig_ObjFanin0(pNode1) && (Aig_ObjFaninC1(pNode0) ^ Aig_ObjFaninC0(pNode1)) )
else if ( Hop_ObjFanin1(pNode0) == Hop_ObjFanin0(pNode1) && (Hop_ObjFaninC1(pNode0) ^ Hop_ObjFaninC0(pNode1)) )
{
// if ( Fraig_IsComplement(pNode1->p2) )
if ( Aig_ObjFaninC1(pNode0) )
if ( Hop_ObjFaninC1(pNode0) )
{ // pNode2->p1 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild1(pNode1));//pNode2->p2);
*ppNodeE = Aig_Not(Aig_ObjChild0(pNode0));//pNode1->p1);
return Aig_ObjChild0(pNode1);//pNode2->p1;
*ppNodeT = Hop_Not(Hop_ObjChild1(pNode1));//pNode2->p2);
*ppNodeE = Hop_Not(Hop_ObjChild0(pNode0));//pNode1->p1);
return Hop_ObjChild0(pNode1);//pNode2->p1;
}
else
{ // pNode1->p2 is positive phase of C
*ppNodeT = Aig_Not(Aig_ObjChild0(pNode0));//pNode1->p1);
*ppNodeE = Aig_Not(Aig_ObjChild1(pNode1));//pNode2->p2);
return Aig_ObjChild1(pNode0);//pNode1->p2;
*ppNodeT = Hop_Not(Hop_ObjChild0(pNode0));//pNode1->p1);
*ppNodeE = Hop_Not(Hop_ObjChild1(pNode1));//pNode2->p2);
return Hop_ObjChild1(pNode0);//pNode1->p2;
}
}
assert( 0 ); // this is not MUX
@ -293,36 +293,36 @@ Aig_Obj_t * Aig_ObjRecognizeMux( Aig_Obj_t * pNode, Aig_Obj_t ** ppNodeT, Aig_Ob
SeeAlso []
***********************************************************************/
void Aig_ObjPrintVerilog( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, int Level )
void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level )
{
Vec_Ptr_t * vSuper;
Aig_Obj_t * pFanin, * pFanin0, * pFanin1, * pFaninC;
Hop_Obj_t * pFanin, * pFanin0, * pFanin1, * pFaninC;
int fCompl, i;
// store the complemented attribute
fCompl = Aig_IsComplement(pObj);
pObj = Aig_Regular(pObj);
fCompl = Hop_IsComplement(pObj);
pObj = Hop_Regular(pObj);
// constant case
if ( Aig_ObjIsConst1(pObj) )
if ( Hop_ObjIsConst1(pObj) )
{
fprintf( pFile, "%d", !fCompl );
return;
}
// PI case
if ( Aig_ObjIsPi(pObj) )
if ( Hop_ObjIsPi(pObj) )
{
fprintf( pFile, "%s%s", fCompl? "~" : "", pObj->pData );
return;
}
// EXOR case
if ( Aig_ObjIsExor(pObj) )
if ( Hop_ObjIsExor(pObj) )
{
Vec_VecExpand( vLevels, Level );
vSuper = Vec_VecEntry( vLevels, Level );
Aig_ObjCollectMulti( pObj, vSuper );
Hop_ObjCollectMulti( pObj, vSuper );
fprintf( pFile, "%s", (Level==0? "" : "(") );
Vec_PtrForEachEntry( vSuper, pFanin, i )
{
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin, (fCompl && i==0)), vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin, (fCompl && i==0)), vLevels, Level+1 );
if ( i < Vec_PtrSize(vSuper) - 1 )
fprintf( pFile, " ^ " );
}
@ -330,25 +330,25 @@ void Aig_ObjPrintVerilog( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, i
return;
}
// MUX case
if ( Aig_ObjIsMuxType(pObj) )
if ( Hop_ObjIsMuxType(pObj) )
{
if ( Aig_ObjRecognizeExor( pObj, &pFanin0, &pFanin1 ) )
if ( Hop_ObjRecognizeExor( pObj, &pFanin0, &pFanin1 ) )
{
fprintf( pFile, "%s", (Level==0? "" : "(") );
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin0, fCompl), vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin0, fCompl), vLevels, Level+1 );
fprintf( pFile, " ^ " );
Aig_ObjPrintVerilog( pFile, pFanin1, vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, pFanin1, vLevels, Level+1 );
fprintf( pFile, "%s", (Level==0? "" : ")") );
}
else
{
pFaninC = Aig_ObjRecognizeMux( pObj, &pFanin1, &pFanin0 );
pFaninC = Hop_ObjRecognizeMux( pObj, &pFanin1, &pFanin0 );
fprintf( pFile, "%s", (Level==0? "" : "(") );
Aig_ObjPrintVerilog( pFile, pFaninC, vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, pFaninC, vLevels, Level+1 );
fprintf( pFile, " ? " );
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin1, fCompl), vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin1, fCompl), vLevels, Level+1 );
fprintf( pFile, " : " );
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin0, fCompl), vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin0, fCompl), vLevels, Level+1 );
fprintf( pFile, "%s", (Level==0? "" : ")") );
}
return;
@ -356,11 +356,11 @@ void Aig_ObjPrintVerilog( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, i
// AND case
Vec_VecExpand( vLevels, Level );
vSuper = Vec_VecEntry(vLevels, Level);
Aig_ObjCollectMulti( pObj, vSuper );
Hop_ObjCollectMulti( pObj, vSuper );
fprintf( pFile, "%s", (Level==0? "" : "(") );
Vec_PtrForEachEntry( vSuper, pFanin, i )
{
Aig_ObjPrintVerilog( pFile, Aig_NotCond(pFanin, fCompl), vLevels, Level+1 );
Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin, fCompl), vLevels, Level+1 );
if ( i < Vec_PtrSize(vSuper) - 1 )
fprintf( pFile, " %s ", fCompl? "|" : "&" );
}
@ -380,19 +380,19 @@ void Aig_ObjPrintVerilog( FILE * pFile, Aig_Obj_t * pObj, Vec_Vec_t * vLevels, i
SeeAlso []
***********************************************************************/
void Aig_ObjPrintVerbose( Aig_Obj_t * pObj, int fHaig )
void Hop_ObjPrintVerbose( Hop_Obj_t * pObj, int fHaig )
{
assert( !Aig_IsComplement(pObj) );
assert( !Hop_IsComplement(pObj) );
printf( "Node %p : ", pObj );
if ( Aig_ObjIsConst1(pObj) )
if ( Hop_ObjIsConst1(pObj) )
printf( "constant 1" );
else if ( Aig_ObjIsPi(pObj) )
else if ( Hop_ObjIsPi(pObj) )
printf( "PI" );
else
printf( "AND( %p%s, %p%s )",
Aig_ObjFanin0(pObj), (Aig_ObjFaninC0(pObj)? "\'" : " "),
Aig_ObjFanin1(pObj), (Aig_ObjFaninC1(pObj)? "\'" : " ") );
printf( " (refs = %3d)", Aig_ObjRefs(pObj) );
Hop_ObjFanin0(pObj), (Hop_ObjFaninC0(pObj)? "\'" : " "),
Hop_ObjFanin1(pObj), (Hop_ObjFaninC1(pObj)? "\'" : " ") );
printf( " (refs = %3d)", Hop_ObjRefs(pObj) );
}
/**Function*************************************************************
@ -406,18 +406,18 @@ void Aig_ObjPrintVerbose( Aig_Obj_t * pObj, int fHaig )
SeeAlso []
***********************************************************************/
void Aig_ManPrintVerbose( Aig_Man_t * p, int fHaig )
void Hop_ManPrintVerbose( Hop_Man_t * p, int fHaig )
{
Vec_Ptr_t * vNodes;
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
printf( "PIs: " );
Aig_ManForEachPi( p, pObj, i )
Hop_ManForEachPi( p, pObj, i )
printf( " %p", pObj );
printf( "\n" );
vNodes = Aig_ManDfs( p );
vNodes = Hop_ManDfs( p );
Vec_PtrForEachEntry( vNodes, pObj, i )
Aig_ObjPrintVerbose( pObj, fHaig ), printf( "\n" );
Hop_ObjPrintVerbose( pObj, fHaig ), printf( "\n" );
printf( "\n" );
}
@ -432,61 +432,61 @@ void Aig_ManPrintVerbose( Aig_Man_t * p, int fHaig )
SeeAlso []
***********************************************************************/
void Aig_ManDumpBlif( Aig_Man_t * p, char * pFileName )
void Hop_ManDumpBlif( Hop_Man_t * p, char * pFileName )
{
FILE * pFile;
Vec_Ptr_t * vNodes;
Aig_Obj_t * pObj, * pConst1 = NULL;
Hop_Obj_t * pObj, * pConst1 = NULL;
int i, nDigits, Counter = 0;
if ( Aig_ManPoNum(p) == 0 )
if ( Hop_ManPoNum(p) == 0 )
{
printf( "Aig_ManDumpBlif(): AIG manager does not have POs.\n" );
printf( "Hop_ManDumpBlif(): AIG manager does not have POs.\n" );
return;
}
// collect nodes in the DFS order
vNodes = Aig_ManDfs( p );
vNodes = Hop_ManDfs( p );
// assign IDs to objects
Aig_ManConst1(p)->pData = (void *)Counter++;
Aig_ManForEachPi( p, pObj, i )
Hop_ManConst1(p)->pData = (void *)Counter++;
Hop_ManForEachPi( p, pObj, i )
pObj->pData = (void *)Counter++;
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
pObj->pData = (void *)Counter++;
Vec_PtrForEachEntry( vNodes, pObj, i )
pObj->pData = (void *)Counter++;
nDigits = Extra_Base10Log( Counter );
// write the file
pFile = fopen( pFileName, "w" );
fprintf( pFile, "# BLIF file written by procedure Aig_ManDumpBlif() in ABC\n" );
fprintf( pFile, "# BLIF file written by procedure Hop_ManDumpBlif() in ABC\n" );
fprintf( pFile, "# http://www.eecs.berkeley.edu/~alanmi/abc/\n" );
fprintf( pFile, ".model test\n" );
// write PIs
fprintf( pFile, ".inputs" );
Aig_ManForEachPi( p, pObj, i )
Hop_ManForEachPi( p, pObj, i )
fprintf( pFile, " n%0*d", nDigits, (int)pObj->pData );
fprintf( pFile, "\n" );
// write POs
fprintf( pFile, ".outputs" );
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
fprintf( pFile, " n%0*d", nDigits, (int)pObj->pData );
fprintf( pFile, "\n" );
// write nodes
Vec_PtrForEachEntry( vNodes, pObj, i )
{
fprintf( pFile, ".names n%0*d n%0*d n%0*d\n",
nDigits, (int)Aig_ObjFanin0(pObj)->pData,
nDigits, (int)Aig_ObjFanin1(pObj)->pData,
nDigits, (int)Hop_ObjFanin0(pObj)->pData,
nDigits, (int)Hop_ObjFanin1(pObj)->pData,
nDigits, (int)pObj->pData );
fprintf( pFile, "%d%d 1\n", !Aig_ObjFaninC0(pObj), !Aig_ObjFaninC1(pObj) );
fprintf( pFile, "%d%d 1\n", !Hop_ObjFaninC0(pObj), !Hop_ObjFaninC1(pObj) );
}
// write POs
Aig_ManForEachPo( p, pObj, i )
Hop_ManForEachPo( p, pObj, i )
{
fprintf( pFile, ".names n%0*d n%0*d\n",
nDigits, (int)Aig_ObjFanin0(pObj)->pData,
nDigits, (int)Hop_ObjFanin0(pObj)->pData,
nDigits, (int)pObj->pData );
fprintf( pFile, "%d 1\n", !Aig_ObjFaninC0(pObj) );
if ( Aig_ObjIsConst1(Aig_ObjFanin0(pObj)) )
pConst1 = Aig_ManConst1(p);
fprintf( pFile, "%d 1\n", !Hop_ObjFaninC0(pObj) );
if ( Hop_ObjIsConst1(Hop_ObjFanin0(pObj)) )
pConst1 = Hop_ManConst1(p);
}
if ( pConst1 )
fprintf( pFile, ".names n%0*d\n 1\n", nDigits, (int)pConst1->pData );

0
src/temp/aig/aig_.c → src/aig/hop/hop_.c
View File

9
src/aig/hop/module.make Normal file
View File

@ -0,0 +1,9 @@
SRC += src/aig/hop/hopBalance.c \
src/aig/hop/hopCheck.c \
src/aig/hop/hopDfs.c \
src/aig/hop/hopMan.c \
src/aig/hop/hopMem.c \
src/aig/hop/hopObj.c \
src/aig/hop/hopOper.c \
src/aig/hop/hopTable.c \
src/aig/hop/hopUtil.c

414
src/aig/ivy/attr.h Normal file
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@ -0,0 +1,414 @@
/**CFile****************************************************************
FileName [attr.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network attributes.]
Synopsis [External declarations.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: attr.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#ifndef __ATTR_H__
#define __ATTR_H__
#ifdef __cplusplus
extern "C" {
#endif
////////////////////////////////////////////////////////////////////////
/// INCLUDES ///
////////////////////////////////////////////////////////////////////////
#include "extra.h"
////////////////////////////////////////////////////////////////////////
/// PARAMETERS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// BASIC TYPES ///
////////////////////////////////////////////////////////////////////////
typedef struct Attr_ManStruct_t_ Attr_Man_t;
struct Attr_ManStruct_t_
{
// attribute info
int nAttrSize; // the size of each attribute in bytes
Extra_MmFixed_t * pManMem; // memory manager for attributes
int nAttrs; // the number of attributes allocated
void ** pAttrs; // the array of attributes
int fUseInt; // uses integer attributes
// attribute specific info
void * pManAttr; // the manager for this attribute
void (*pFuncFreeMan) (void *); // the procedure to call to free attribute-specific manager
void (*pFuncFreeObj) (void *, void *); // the procedure to call to free attribute-specific data
};
// at any time, an attribute of the given ID can be
// - not available (p->nAttrs < Id)
// - available but not allocated (p->nAttrs >= Id && p->pAttrs[Id] == NULL)
// - available and allocated (p->nAttrs >= Id && p->pAttrs[Id] != NULL)
////////////////////////////////////////////////////////////////////////
/// MACRO DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Allocates the attribute manager.]
Description [The manager is simple if it does not need memory manager.]
SideEffects []
SeeAlso []
***********************************************************************/
static inline Attr_Man_t * Attr_ManAlloc( int nAttrSize, int fManMem )
{
Attr_Man_t * p;
p = ALLOC( Attr_Man_t, 1 );
memset( p, 0, sizeof(Attr_Man_t) );
p->nAttrSize = nAttrSize;
if ( fManMem )
p->pManMem = Extra_MmFixedStart( nAttrSize );
return p;
}
/**Function*************************************************************
Synopsis [Start the attribute manager for integers.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Attr_Man_t * Attr_ManStartInt( int nAttrs )
{
Attr_Man_t * p;
p = Attr_ManAlloc( sizeof(int), 0 );
p->nAttrs = nAttrs;
p->pAttrs = (void **)ALLOC( int, nAttrs );
memset( (int *)p->pAttrs, 0, sizeof(int) * nAttrs );
p->fUseInt = 1;
return p;
}
/**Function*************************************************************
Synopsis [Start the attribute manager for pointers.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Attr_Man_t * Attr_ManStartPtr( int nAttrs )
{
Attr_Man_t * p;
p = Attr_ManAlloc( sizeof(void *), 0 );
p->nAttrs = nAttrs;
p->pAttrs = ALLOC( void *, nAttrs );
memset( p->pAttrs, 0, sizeof(void *) * nAttrs );
return p;
}
/**Function*************************************************************
Synopsis [Start the attribute manager for the fixed entry size.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline Attr_Man_t * Attr_ManStartPtrMem( int nAttrs, int nAttrSize )
{
Attr_Man_t * p;
int i;
p = Attr_ManAlloc( nAttrSize, 1 );
p->nAttrs = nAttrs;
p->pAttrs = ALLOC( void *, nAttrs );
for ( i = 0; i < p->nAttrs; i++ )
{
p->pAttrs[i] = Extra_MmFixedEntryFetch( p->pManMem );
memset( p->pAttrs[i], 0, nAttrSize );
}
return p;
}
/**Function*************************************************************
Synopsis [Stop the attribute manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Attr_ManStop( Attr_Man_t * p )
{
// free the attributes of objects
if ( p->pFuncFreeObj )
{
int i;
if ( p->fUseInt )
{
for ( i = 0; i < p->nAttrs; i++ )
if ( ((int *)p->pAttrs)[i] )
p->pFuncFreeObj( p->pManAttr, (void *)((int *)p->pAttrs)[i] );
}
else
{
for ( i = 0; i < p->nAttrs; i++ )
if ( p->pAttrs[i] )
p->pFuncFreeObj( p->pManAttr, p->pAttrs[i] );
}
}
// free the attribute manager
if ( p->pManAttr && p->pFuncFreeMan )
p->pFuncFreeMan( p->pManAttr );
// free the memory manager
if ( p->pManMem )
Extra_MmFixedStop( p->pManMem, 0 );
// free the attribute manager
FREE( p->pAttrs );
free( p );
}
/**Function*************************************************************
Synopsis [Reads the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Attr_ManReadAttrInt( Attr_Man_t * p, int Id )
{
assert( p->fUseInt );
if ( Id >= p->nAttrs )
return 0;
return ((int *)p->pAttrs)[Id];
}
/**Function*************************************************************
Synopsis [Reads the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void * Attr_ManReadAttrPtr( Attr_Man_t * p, int Id )
{
assert( !p->fUseInt );
if ( Id >= p->nAttrs )
return NULL;
return p->pAttrs[Id];
}
/**Function*************************************************************
Synopsis [Writes the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Attr_ManWriteAttrInt( Attr_Man_t * p, int Id, int Attr )
{
assert( p->fUseInt );
((int *)p->pAttrs)[Id] = Attr;
}
/**Function*************************************************************
Synopsis [Writes the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Attr_ManWriteAttrPtr( Attr_Man_t * p, int Id, void * pAttr )
{
assert( !p->fUseInt );
assert( p->pManMem == NULL );
p->pAttrs[Id] = pAttr;
}
/**Function*************************************************************
Synopsis [Returns or creates the pointer to the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int * Attr_ManFetchSpotInt( Attr_Man_t * p, int Id )
{
assert( p->fUseInt );
if ( Id >= p->nAttrs )
{
// save the old size
int i, nAttrsOld = p->nAttrs;
// get the new size
p->nAttrs = p->nAttrs? 2*p->nAttrs : 1024;
p->pAttrs = realloc( p->pAttrs, sizeof(int) * p->nAttrs );
// fill in the empty spots
for ( i = nAttrsOld; i < p->nAttrs; i++ )
((int *)p->pAttrs)[Id] = 0;
}
return ((int *)p->pAttrs) + Id;
}
/**Function*************************************************************
Synopsis [Returns or creates the pointer to the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void ** Attr_ManFetchSpotPtr( Attr_Man_t * p, int Id )
{
assert( !p->fUseInt );
if ( Id >= p->nAttrs )
{
// save the old size
int i, nAttrsOld = p->nAttrs;
// get the new size
p->nAttrs = p->nAttrs? 2*p->nAttrs : 1024;
p->pAttrs = realloc( p->pAttrs, sizeof(void *) * p->nAttrs );
// fill in the empty spots
for ( i = nAttrsOld; i < p->nAttrs; i++ )
p->pAttrs[Id] = NULL;
}
// if memory manager is available but entry is not created, create it
if ( p->pManMem && p->pAttrs[Id] != NULL )
{
p->pAttrs[Id] = Extra_MmFixedEntryFetch( p->pManMem );
memset( p->pAttrs[Id], 0, p->nAttrSize );
}
return p->pAttrs + Id;
}
/**Function*************************************************************
Synopsis [Returns or creates the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline int Attr_ManFetchAttrInt( Attr_Man_t * p, int Id )
{
return *Attr_ManFetchSpotInt( p, Id );
}
/**Function*************************************************************
Synopsis [Returns or creates the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void * Attr_ManFetchAttrPtr( Attr_Man_t * p, int Id )
{
return *Attr_ManFetchSpotPtr( p, Id );
}
/**Function*************************************************************
Synopsis [Sets the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Attr_ManSetAttrInt( Attr_Man_t * p, int Id, int Attr )
{
*Attr_ManFetchSpotInt( p, Id ) = Attr;
}
/**Function*************************************************************
Synopsis [Sets the attribute of the given object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline void Attr_ManSetAttrPtr( Attr_Man_t * p, int Id, void * pAttr )
{
assert( p->pManMem == NULL );
*Attr_ManFetchSpotPtr( p, Id ) = pAttr;
}
#ifdef __cplusplus
}
#endif
#endif
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

8
src/temp/ivy/ivy.h → src/aig/ivy/ivy.h
View File

@ -139,10 +139,10 @@ struct Ivy_FraigParams_t_
int fDoSparse; // skip sparse functions
int nBTLimitNode; // conflict limit at a node
int nBTLimitMiter; // conflict limit at an output
int nBTLimitGlobal; // conflict limit global
int nInsLimitNode; // inspection limit at a node
int nInsLimitMiter; // inspection limit at an output
int nInsLimitGlobal; // inspection limit global
// int nBTLimitGlobal; // conflict limit global
// int nInsLimitNode; // inspection limit at a node
// int nInsLimitMiter; // inspection limit at an output
// int nInsLimitGlobal; // inspection limit global
};

0
src/temp/ivy/ivyBalance.c → src/aig/ivy/ivyBalance.c
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0
src/temp/ivy/ivyCanon.c → src/aig/ivy/ivyCanon.c
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0
src/temp/ivy/ivyCheck.c → src/aig/ivy/ivyCheck.c
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0
src/temp/ivy/ivyCut.c → src/aig/ivy/ivyCut.c
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0
src/temp/ivy/ivyCutTrav.c → src/aig/ivy/ivyCutTrav.c
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0
src/temp/ivy/ivyDfs.c → src/aig/ivy/ivyDfs.c
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0
src/temp/ivy/ivyDsd.c → src/aig/ivy/ivyDsd.c
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0
src/temp/ivy/ivyFanout.c → src/aig/ivy/ivyFanout.c
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0
src/temp/ivy/ivyFastMap.c → src/aig/ivy/ivyFastMap.c
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378
src/aig/ivy/ivyFpga.c Normal file
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@ -0,0 +1,378 @@
/**CFile****************************************************************
FileName [ivyFpga.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [And-Inverter Graph package.]
Synopsis [Prepares the AIG package to work as an FPGA mapper.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - May 11, 2006.]
Revision [$Id: ivyFpga.c,v 1.00 2006/05/11 00:00:00 alanmi Exp $]
***********************************************************************/
#include "ivy.h"
#include "attr.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
typedef struct Ivy_FpgaMan_t_ Ivy_FpgaMan_t;
typedef struct Ivy_FpgaObj_t_ Ivy_FpgaObj_t;
typedef struct Ivy_FpgaCut_t_ Ivy_FpgaCut_t;
// manager
struct Ivy_FpgaMan_t_
{
Ivy_Man_t * pManIvy; // the AIG manager
Attr_Man_t * pManAttr; // the attribute manager
int nLutSize; // the LUT size
int nCutsMax; // the max number of cuts
int nEntrySize; // the size of the entry
int nEntryBase; // the size of the entry minus cut leaf arrays
int fVerbose; // the verbosity flag
// temporary cut storage
Ivy_FpgaCut_t * pCutStore; // the temporary cuts
};
// priority cut
struct Ivy_FpgaCut_t_
{
float Delay; // the delay of the cut
float AreaFlow; // the area flow of the cut
float Area; // the area of the cut
int nLeaves; // the number of leaves
int * pLeaves; // the array of fanins
};
// node extension
struct Ivy_FpgaObj_t_
{
unsigned Type : 4; // type
unsigned nCuts : 28; // the number of cuts
int Id; // integer ID
int nRefs; // the number of references
Ivy_FpgaObj_t * pFanin0; // the first fanin
Ivy_FpgaObj_t * pFanin1; // the second fanin
float Required; // required time of the onde
Ivy_FpgaCut_t * pCut; // the best cut
Ivy_FpgaCut_t Cuts[0]; // the cuts of the node
};
static Ivy_FpgaMan_t * Ivy_ManFpgaPrepare( Ivy_Man_t * p, int nLutSize, int nCutsMax, int fVerbose );
static void Ivy_ManFpgaUndo( Ivy_FpgaMan_t * pFpga );
static void Ivy_ObjFpgaCreate( Ivy_FpgaMan_t * pFpga, int ObjId );
static void Ivy_ManFpgaDelay( Ivy_FpgaMan_t * pFpga );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Performs FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Ivy_ManFpga( Ivy_Man_t * p, int nLutSize, int nCutsMax, int fVerbose )
{
Ivy_FpgaMan_t * pFpga;
pFpga = Ivy_ManFpgaPrepare( p, nLutSize, nCutsMax, fVerbose );
Ivy_ManFpgaDelay( pFpga );
Ivy_ManFpgaUndo( pFpga );
}
/**Function*************************************************************
Synopsis [Prepares manager for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ivy_FpgaMan_t * Ivy_ManFpgaPrepare( Ivy_Man_t * p, int nLutSize, int nCutsMax, int fVerbose )
{
Ivy_FpgaMan_t * pFpga;
Ivy_Obj_t * pObj;
int i;
pFpga = ALLOC( Ivy_FpgaMan_t, 1 );
memset( pFpga, 0, sizeof(Ivy_FpgaMan_t) );
// compute the size of the node
pFpga->pManIvy = p;
pFpga->nLutSize = nLutSize;
pFpga->nCutsMax = nCutsMax;
pFpga->fVerbose = fVerbose;
pFpga->nEntrySize = sizeof(Ivy_FpgaObj_t) + (nCutsMax + 1) * (sizeof(Ivy_FpgaCut_t) + sizeof(int) * nLutSize);
pFpga->nEntryBase = sizeof(Ivy_FpgaObj_t) + (nCutsMax + 1) * (sizeof(Ivy_FpgaCut_t));
pFpga->pManAttr = Attr_ManStartPtrMem( Ivy_ManObjIdMax(p) + 1, pFpga->nEntrySize );
if ( fVerbose )
printf( "Entry size = %d. Total memory = %5.2f Mb.\n", pFpga->nEntrySize,
1.0 * pFpga->nEntrySize * (Ivy_ManObjIdMax(p) + 1) / (1<<20) );
// connect memory for cuts
Ivy_ManForEachObj( p, pObj, i )
Ivy_ObjFpgaCreate( pFpga, pObj->Id );
// create temporary cuts
pFpga->pCutStore = (Ivy_FpgaCut_t *)ALLOC( char, pFpga->nEntrySize * (nCutsMax + 1) * (nCutsMax + 1) );
memset( pFpga->pCutStore, 0, pFpga->nEntrySize * (nCutsMax + 1) * (nCutsMax + 1) );
{
int i, * pArrays;
pArrays = (int *)((char *)pFpga->pCutStore + sizeof(Ivy_FpgaCut_t) * (nCutsMax + 1) * (nCutsMax + 1));
for ( i = 0; i < (nCutsMax + 1) * (nCutsMax + 1); i++ )
pFpga->pCutStore[i].pLeaves = pArrays + i * pFpga->nLutSize;
}
return pFpga;
}
/**Function*************************************************************
Synopsis [Quits the manager for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Ivy_ManFpgaUndo( Ivy_FpgaMan_t * pFpga )
{
Attr_ManStop( pFpga->pManAttr );
free( pFpga );
}
/**Function*************************************************************
Synopsis [Prepares the object for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Ivy_ObjFpgaCreate( Ivy_FpgaMan_t * pFpga, int ObjId )
{
Ivy_FpgaObj_t * pObjFpga;
int i, * pArrays;
pObjFpga = Attr_ManReadAttrPtr( pFpga->pManAttr, ObjId );
pArrays = (int *)((char *)pObjFpga + pFpga->nEntryBase);
for ( i = 0; i <= pFpga->nCutsMax; i++ )
pObjFpga->Cuts[i].pLeaves = pArrays + i * pFpga->nLutSize;
}
/**Function*************************************************************
Synopsis [Prepares the object for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ivy_ObjFpgaMerge( Ivy_FpgaCut_t * pC0, Ivy_FpgaCut_t * pC1, Ivy_FpgaCut_t * pC, int nLimit )
{
int i, k, c;
assert( pC0->nLeaves >= pC1->nLeaves );
// the case of the largest cut sizes
if ( pC0->nLeaves == nLimit && pC1->nLeaves == nLimit )
{
for ( i = 0; i < pC0->nLeaves; i++ )
if ( pC0->pLeaves[i] != pC1->pLeaves[i] )
return 0;
for ( i = 0; i < pC0->nLeaves; i++ )
pC->pLeaves[i] = pC0->pLeaves[i];
pC->nLeaves = pC0->nLeaves;
pC->Delay = 1 + IVY_MAX( pC0->Delay, pC1->Delay );
return 1;
}
// the case when one of the cuts is the largest
if ( pC0->nLeaves == nLimit )
{
for ( i = 0; i < pC1->nLeaves; i++ )
{
for ( k = pC0->nLeaves - 1; k >= 0; k-- )
if ( pC0->pLeaves[k] == pC1->pLeaves[i] )
break;
if ( k == -1 ) // did not find
return 0;
}
for ( i = 0; i < pC0->nLeaves; i++ )
pC->pLeaves[i] = pC0->pLeaves[i];
pC->nLeaves = pC0->nLeaves;
pC->Delay = 1 + IVY_MAX( pC0->Delay, pC1->Delay );
return 1;
}
// compare two cuts with different numbers
i = k = 0;
for ( c = 0; c < nLimit; c++ )
{
if ( k == pC1->nLeaves )
{
if ( i == pC0->nLeaves )
{
pC->nLeaves = c;
pC->Delay = 1 + IVY_MAX( pC0->Delay, pC1->Delay );
return 1;
}
pC->pLeaves[c] = pC0->pLeaves[i++];
continue;
}
if ( i == pC0->nLeaves )
{
if ( k == pC1->nLeaves )
{
pC->nLeaves = c;
pC->Delay = 1 + IVY_MAX( pC0->Delay, pC1->Delay );
return 1;
}
pC->pLeaves[c] = pC1->pLeaves[k++];
continue;
}
if ( pC0->pLeaves[i] < pC1->pLeaves[k] )
{
pC->pLeaves[c] = pC0->pLeaves[i++];
continue;
}
if ( pC0->pLeaves[i] > pC1->pLeaves[k] )
{
pC->pLeaves[c] = pC1->pLeaves[k++];
continue;
}
pC->pLeaves[c] = pC0->pLeaves[i++];
k++;
}
if ( i < pC0->nLeaves || k < pC1->nLeaves )
return 0;
pC->nLeaves = c;
pC->Delay = 1 + IVY_MAX( pC0->Delay, pC1->Delay );
return 1;
}
/**Function*************************************************************
Synopsis [Prepares the object for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ivy_FpgaCutCompare( Ivy_FpgaCut_t * pC0, Ivy_FpgaCut_t * pC1 )
{
if ( pC0->Delay < pC1->Delay )
return -1;
if ( pC0->Delay > pC1->Delay )
return 1;
if ( pC0->nLeaves < pC1->nLeaves )
return -1;
if ( pC0->nLeaves > pC1->nLeaves )
return 1;
return 0;
}
/**Function*************************************************************
Synopsis [Prepares the object for FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Ivy_ObjFpgaDelay( Ivy_FpgaMan_t * pFpga, int ObjId, int Fan0Id, int Fan1Id )
{
Ivy_FpgaObj_t * pObjFpga, * pObjFpga0, * pObjFpga1;
int nCuts, i, k;
pObjFpga = Attr_ManReadAttrPtr( pFpga->pManAttr, ObjId );
pObjFpga0 = Attr_ManReadAttrPtr( pFpga->pManAttr, Fan0Id );
pObjFpga1 = Attr_ManReadAttrPtr( pFpga->pManAttr, Fan1Id );
// create cross-product of the cuts
nCuts = 0;
for ( i = 0; pObjFpga0->Cuts[i].nLeaves > 0 && i < pFpga->nCutsMax; i++ )
for ( k = 0; pObjFpga1->Cuts[k].nLeaves > 0 && k < pFpga->nCutsMax; k++ )
if ( Ivy_ObjFpgaMerge( pObjFpga0->Cuts + i, pObjFpga1->Cuts + k, pFpga->pCutStore + nCuts, pFpga->nLutSize ) )
nCuts++;
// sort the cuts
qsort( pFpga->pCutStore, nCuts, sizeof(Ivy_FpgaCut_t), (int (*)(const void *, const void *))Ivy_FpgaCutCompare );
// take the first
pObjFpga->Cuts[0].nLeaves = 1;
pObjFpga->Cuts[0].pLeaves[0] = ObjId;
pObjFpga->Cuts[0].Delay = pFpga->pCutStore[0].Delay;
pObjFpga->Cuts[1] = pFpga->pCutStore[0];
}
/**Function*************************************************************
Synopsis [Maps the nodes for delay.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Ivy_ManFpgaDelay( Ivy_FpgaMan_t * pFpga )
{
Ivy_FpgaObj_t * pObjFpga;
Ivy_Obj_t * pObj;
int i, DelayBest;
int clk = clock();
// set arrival times and trivial cuts at const 1 and PIs
pObjFpga = Attr_ManReadAttrPtr( pFpga->pManAttr, 0 );
pObjFpga->Cuts[0].nLeaves = 1;
Ivy_ManForEachPi( pFpga->pManIvy, pObj, i )
{
pObjFpga = Attr_ManReadAttrPtr( pFpga->pManAttr, pObj->Id );
pObjFpga->Cuts[0].nLeaves = 1;
pObjFpga->Cuts[0].pLeaves[0] = pObj->Id;
}
// map the internal nodes
Ivy_ManForEachNode( pFpga->pManIvy, pObj, i )
{
Ivy_ObjFpgaDelay( pFpga, pObj->Id, Ivy_ObjFaninId0(pObj), Ivy_ObjFaninId1(pObj) );
}
// get the best arrival time of the POs
DelayBest = 0;
Ivy_ManForEachPo( pFpga->pManIvy, pObj, i )
{
pObjFpga = Attr_ManReadAttrPtr( pFpga->pManAttr, Ivy_ObjFanin0(pObj)->Id );
if ( DelayBest < (int)pObjFpga->Cuts[1].Delay )
DelayBest = (int)pObjFpga->Cuts[1].Delay;
}
printf( "Best delay = %d. ", DelayBest );
PRT( "Time", clock() - clk );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

222
src/temp/ivy/ivyFraig.c → src/aig/ivy/ivyFraig.c
View File

@ -18,9 +18,9 @@
***********************************************************************/
#include "ivy.h"
#include "satSolver.h"
#include "extra.h"
#include "ivy.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -50,6 +50,9 @@ struct Ivy_FraigMan_t_
{
// general info
Ivy_FraigParams_t * pParams; // various parameters
// temporary backtrack limits because "sint64" cannot be defined in Ivy_FraigParams_t ...
sint64 nBTLimitGlobal; // global limit on the number of backtracks
sint64 nInsLimitGlobal;// global limit on the number of clause inspects
// AIG manager
Ivy_Man_t * pManAig; // the starting AIG manager
Ivy_Man_t * pManFraig; // the final AIG manager
@ -178,7 +181,7 @@ static inline unsigned Ivy_ObjRandomSim() { return (ran
static Ivy_FraigMan_t * Ivy_FraigStart( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams );
static Ivy_FraigMan_t * Ivy_FraigStartSimple( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams );
static Ivy_Man_t * Ivy_FraigPerform_int( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams, sint64 * pnSatConfs, sint64 * pnSatInspects );
static Ivy_Man_t * Ivy_FraigPerform_int( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams, sint64 nBTLimitGlobal, sint64 nInsLimitGlobal, sint64 * pnSatConfs, sint64 * pnSatInspects );
static void Ivy_FraigPrint( Ivy_FraigMan_t * p );
static void Ivy_FraigStop( Ivy_FraigMan_t * p );
static void Ivy_FraigSimulate( Ivy_FraigMan_t * p );
@ -194,6 +197,11 @@ static void Ivy_FraigMiterProve( Ivy_FraigMan_t * p );
static void Ivy_FraigMiterPrint( Ivy_Man_t * pNtk, char * pString, int clk, int fVerbose );
static int * Ivy_FraigCreateModel( Ivy_FraigMan_t * p );
static int Ivy_FraigNodesAreEquivBdd( Ivy_Obj_t * pObj1, Ivy_Obj_t * pObj2 );
static sint64 s_nBTLimitGlobal = 0;
static sint64 s_nInsLimitGlobal = 0;
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
@ -224,10 +232,8 @@ void Ivy_FraigParamsDefault( Ivy_FraigParams_t * pParams )
pParams->nBTLimitNode = 100; // conflict limit at a node
pParams->nBTLimitMiter = 500000; // conflict limit at an output
pParams->nBTLimitGlobal = 0; // conflict limit global
pParams->nInsLimitNode = 0; // inspection limit at a node
pParams->nInsLimitMiter = 0; // inspection limit at an output
pParams->nInsLimitGlobal = 0; // inspection limit global
// pParams->nBTLimitGlobal = 0; // conflict limit global
// pParams->nInsLimitGlobal = 0; // inspection limit global
}
/**Function*************************************************************
@ -247,7 +253,7 @@ int Ivy_FraigProve( Ivy_Man_t ** ppManAig, void * pPars )
Ivy_FraigParams_t Params, * pIvyParams = &Params;
Ivy_Man_t * pManAig, * pManTemp;
int RetValue, nIter, Counter, clk, timeStart = clock();
sint64 nSatConfs, nSatInspects, nInspectLimit;
sint64 nSatConfs, nSatInspects;
// start the network and parameters
pManAig = *ppManAig;
@ -322,10 +328,9 @@ int Ivy_FraigProve( Ivy_Man_t ** ppManAig, void * pPars )
if ( pParams->fUseFraiging )
{
clk = clock();
nInspectLimit = pParams->nTotalInspectLimit? pParams->nTotalInspectLimit - pParams->nTotalInspectsMade : 0;
pIvyParams->nBTLimitNode = (int)(pParams->nFraigingLimitStart * pow(pParams->nFraigingLimitMulti,nIter));
pIvyParams->nBTLimitMiter = (int)(pParams->nMiteringLimitStart * pow(pParams->nMiteringLimitMulti,nIter)) / Ivy_ManPoNum(pManAig);
pManAig = Ivy_FraigPerform_int( pManTemp = pManAig, pIvyParams, &nSatConfs, &nSatInspects ); Ivy_ManStop( pManTemp );
pManAig = Ivy_FraigPerform_int( pManTemp = pManAig, pIvyParams, pParams->nTotalBacktrackLimit, pParams->nTotalInspectLimit, &nSatConfs, &nSatInspects ); Ivy_ManStop( pManTemp );
RetValue = Ivy_FraigMiterStatus( pManAig );
Ivy_FraigMiterPrint( pManAig, "Fraiging ", clk, pParams->fVerbose );
}
@ -353,9 +358,14 @@ int Ivy_FraigProve( Ivy_Man_t ** ppManAig, void * pPars )
fflush( stdout );
}
clk = clock();
nInspectLimit = pParams->nTotalInspectLimit? pParams->nTotalInspectLimit - pParams->nTotalInspectsMade : 0;
pIvyParams->nBTLimitMiter = pParams->nMiteringLimitLast / Ivy_ManPoNum(pManAig);
if ( pParams->nTotalBacktrackLimit )
s_nBTLimitGlobal = pParams->nTotalBacktrackLimit - pParams->nTotalBacktracksMade;
if ( pParams->nTotalInspectLimit )
s_nInsLimitGlobal = pParams->nTotalInspectLimit - pParams->nTotalInspectsMade;
pManAig = Ivy_FraigMiter( pManTemp = pManAig, pIvyParams ); Ivy_ManStop( pManTemp );
s_nBTLimitGlobal = 0;
s_nInsLimitGlobal = 0;
RetValue = Ivy_FraigMiterStatus( pManAig );
Ivy_FraigMiterPrint( pManAig, "SAT solving", clk, pParams->fVerbose );
}
@ -381,7 +391,7 @@ int Ivy_FraigProve( Ivy_Man_t ** ppManAig, void * pPars )
SeeAlso []
***********************************************************************/
Ivy_Man_t * Ivy_FraigPerform_int( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams, sint64 * pnSatConfs, sint64 * pnSatInspects )
Ivy_Man_t * Ivy_FraigPerform_int( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams, sint64 nBTLimitGlobal, sint64 nInsLimitGlobal, sint64 * pnSatConfs, sint64 * pnSatInspects )
{
Ivy_FraigMan_t * p;
Ivy_Man_t * pManAigNew;
@ -391,6 +401,10 @@ Ivy_Man_t * Ivy_FraigPerform_int( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pPara
clk = clock();
assert( Ivy_ManLatchNum(pManAig) == 0 );
p = Ivy_FraigStart( pManAig, pParams );
// set global limits
p->nBTLimitGlobal = nBTLimitGlobal;
p->nInsLimitGlobal = nInsLimitGlobal;
Ivy_FraigSimulate( p );
Ivy_FraigSweep( p );
pManAigNew = p->pManFraig;
@ -452,6 +466,9 @@ Ivy_Man_t * Ivy_FraigMiter( Ivy_Man_t * pManAig, Ivy_FraigParams_t * pParams )
clk = clock();
assert( Ivy_ManLatchNum(pManAig) == 0 );
p = Ivy_FraigStartSimple( pManAig, pParams );
// set global limits
p->nBTLimitGlobal = s_nBTLimitGlobal;
p->nInsLimitGlobal = s_nInsLimitGlobal;
// duplicate internal nodes
Ivy_ManForEachNode( p->pManAig, pObj, i )
pObj->pEquiv = Ivy_And( p->pManFraig, Ivy_ObjChild0Equiv(pObj), Ivy_ObjChild1Equiv(pObj) );
@ -2003,7 +2020,7 @@ void Ivy_FraigPrintActivity( Ivy_FraigMan_t * p )
***********************************************************************/
int Ivy_FraigNodesAreEquiv( Ivy_FraigMan_t * p, Ivy_Obj_t * pOld, Ivy_Obj_t * pNew )
{
int pLits[4], RetValue, RetValue1, nBTLimit, clk;
int pLits[4], RetValue, RetValue1, nBTLimit, clk, clk2 = clock();
// make sure the nodes are not complemented
assert( !Ivy_IsComplement(pNew) );
@ -2046,8 +2063,8 @@ clk = clock();
pLits[1] = toLitCond( Ivy_ObjSatNum(pNew), pOld->fPhase == pNew->fPhase );
//Sat_SolverWriteDimacs( p->pSat, "temp.cnf", pLits, pLits + 2, 1 );
RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2,
nBTLimit, p->pParams->nInsLimitNode,
p->pParams->nBTLimitGlobal, p->pParams->nInsLimitGlobal );
(sint64)nBTLimit, (sint64)0,
p->nBTLimitGlobal, p->nInsLimitGlobal );
p->timeSat += clock() - clk;
if ( RetValue1 == l_False )
{
@ -2090,8 +2107,8 @@ clk = clock();
pLits[0] = toLitCond( Ivy_ObjSatNum(pOld), 1 );
pLits[1] = toLitCond( Ivy_ObjSatNum(pNew), pOld->fPhase ^ pNew->fPhase );
RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 2,
nBTLimit, p->pParams->nInsLimitNode,
p->pParams->nBTLimitGlobal, p->pParams->nInsLimitGlobal );
(sint64)nBTLimit, (sint64)0,
p->nBTLimitGlobal, p->nInsLimitGlobal );
p->timeSat += clock() - clk;
if ( RetValue1 == l_False )
{
@ -2118,7 +2135,19 @@ p->timeSatFail += clock() - clk;
p->nSatFailsReal++;
return -1;
}
/*
// check BDD proof
{
int RetVal;
PRT( "Sat", clock() - clk2 );
clk2 = clock();
RetVal = Ivy_FraigNodesAreEquivBdd( pOld, pNew );
// printf( "%d ", RetVal );
assert( RetVal );
PRT( "Bdd", clock() - clk2 );
printf( "\n" );
}
*/
// return SAT proof
p->nSatProof++;
return 1;
@ -2162,8 +2191,8 @@ int Ivy_FraigNodeIsConst( Ivy_FraigMan_t * p, Ivy_Obj_t * pNew )
clk = clock();
pLits[0] = toLitCond( Ivy_ObjSatNum(pNew), pNew->fPhase );
RetValue1 = sat_solver_solve( p->pSat, pLits, pLits + 1,
p->pParams->nBTLimitMiter, p->pParams->nInsLimitMiter,
p->pParams->nBTLimitGlobal, p->pParams->nInsLimitGlobal );
(sint64)p->pParams->nBTLimitMiter, (sint64)0,
p->nBTLimitGlobal, p->nInsLimitGlobal );
p->timeSat += clock() - clk;
if ( RetValue1 == l_False )
{
@ -2513,6 +2542,161 @@ p->timeTrav += clock() - clk;
return 1;
}
#include "cuddInt.h"
/**Function*************************************************************
Synopsis [Checks equivalence using BDDs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Ivy_FraigNodesAreEquivBdd_int( DdManager * dd, DdNode * bFunc, Vec_Ptr_t * vFront, int Level )
{
DdNode ** pFuncs;
DdNode * bFuncNew;
Vec_Ptr_t * vTemp;
Ivy_Obj_t * pObj, * pFanin;
int i, NewSize;
// create new frontier
vTemp = Vec_PtrAlloc( 100 );
Vec_PtrForEachEntry( vFront, pObj, i )
{
if ( (int)pObj->Level != Level )
{
pObj->fMarkB = 1;
pObj->TravId = Vec_PtrSize(vTemp);
Vec_PtrPush( vTemp, pObj );
continue;
}
pFanin = Ivy_ObjFanin0(pObj);
if ( pFanin->fMarkB == 0 )
{
pFanin->fMarkB = 1;
pFanin->TravId = Vec_PtrSize(vTemp);
Vec_PtrPush( vTemp, pFanin );
}
pFanin = Ivy_ObjFanin1(pObj);
if ( pFanin->fMarkB == 0 )
{
pFanin->fMarkB = 1;
pFanin->TravId = Vec_PtrSize(vTemp);
Vec_PtrPush( vTemp, pFanin );
}
}
// collect the permutation
NewSize = IVY_MAX(dd->size, Vec_PtrSize(vTemp));
pFuncs = ALLOC( DdNode *, NewSize );
Vec_PtrForEachEntry( vFront, pObj, i )
{
if ( (int)pObj->Level != Level )
pFuncs[i] = Cudd_bddIthVar( dd, pObj->TravId );
else
pFuncs[i] = Cudd_bddAnd( dd,
Cudd_NotCond( Cudd_bddIthVar(dd, Ivy_ObjFanin0(pObj)->TravId), Ivy_ObjFaninC0(pObj) ),
Cudd_NotCond( Cudd_bddIthVar(dd, Ivy_ObjFanin1(pObj)->TravId), Ivy_ObjFaninC1(pObj) ) );
Cudd_Ref( pFuncs[i] );
}
// add the remaining vars
assert( NewSize == dd->size );
for ( i = Vec_PtrSize(vFront); i < dd->size; i++ )
{
pFuncs[i] = Cudd_bddIthVar( dd, i );
Cudd_Ref( pFuncs[i] );
}
// create new
bFuncNew = Cudd_bddVectorCompose( dd, bFunc, pFuncs ); Cudd_Ref( bFuncNew );
// clean trav Id
Vec_PtrForEachEntry( vTemp, pObj, i )
{
pObj->fMarkB = 0;
pObj->TravId = 0;
}
// deref
for ( i = 0; i < dd->size; i++ )
Cudd_RecursiveDeref( dd, pFuncs[i] );
free( pFuncs );
free( vFront->pArray );
*vFront = *vTemp;
vTemp->nCap = vTemp->nSize = 0;
vTemp->pArray = NULL;
Vec_PtrFree( vTemp );
Cudd_Deref( bFuncNew );
return bFuncNew;
}
/**Function*************************************************************
Synopsis [Checks equivalence using BDDs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ivy_FraigNodesAreEquivBdd( Ivy_Obj_t * pObj1, Ivy_Obj_t * pObj2 )
{
static DdManager * dd = NULL;
DdNode * bFunc, * bTemp;
Vec_Ptr_t * vFront;
Ivy_Obj_t * pObj;
int i, RetValue, Iter, Level;
// start the manager
if ( dd == NULL )
dd = Cudd_Init( 50, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
// create front
vFront = Vec_PtrAlloc( 100 );
Vec_PtrPush( vFront, pObj1 );
Vec_PtrPush( vFront, pObj2 );
// get the function
bFunc = Cudd_bddXor( dd, Cudd_bddIthVar(dd,0), Cudd_bddIthVar(dd,1) ); Cudd_Ref( bFunc );
bFunc = Cudd_NotCond( bFunc, pObj1->fPhase != pObj2->fPhase );
// try running BDDs
for ( Iter = 0; ; Iter++ )
{
// find max level
Level = 0;
Vec_PtrForEachEntry( vFront, pObj, i )
if ( Level < (int)pObj->Level )
Level = (int)pObj->Level;
if ( Level == 0 )
break;
bFunc = Ivy_FraigNodesAreEquivBdd_int( dd, bTemp = bFunc, vFront, Level ); Cudd_Ref( bFunc );
Cudd_RecursiveDeref( dd, bTemp );
if ( bFunc == Cudd_ReadLogicZero(dd) ) // proved
{printf( "%d", Iter ); break;}
if ( Cudd_DagSize(bFunc) > 1000 )
{printf( "b" ); break;}
if ( dd->size > 120 )
{printf( "s" ); break;}
if ( Iter > 50 )
{printf( "i" ); break;}
}
if ( bFunc == Cudd_ReadLogicZero(dd) ) // unsat
RetValue = 1;
else if ( Level == 0 ) // sat
RetValue = 0;
else
RetValue = -1; // spaceout/timeout
Cudd_RecursiveDeref( dd, bFunc );
Vec_PtrFree( vFront );
return RetValue;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

0
src/temp/ivy/ivyHaig.c → src/aig/ivy/ivyHaig.c
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0
src/temp/ivy/ivyIsop.c → src/aig/ivy/ivyIsop.c
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4
src/temp/ivy/ivyMan.c → src/aig/ivy/ivyMan.c
View File

@ -411,7 +411,7 @@ int Ivy_ManLatchIsSelfFeed( Ivy_Obj_t * pLatch )
int Ivy_ManPropagateBuffers( Ivy_Man_t * p, int fUpdateLevel )
{
Ivy_Obj_t * pNode;
int LimitFactor = 5;
int LimitFactor = 10;
int NodeBeg = Ivy_ManNodeNum(p);
int nSteps;
for ( nSteps = 0; Vec_PtrSize(p->vBufs) > 0; nSteps++ )
@ -435,7 +435,7 @@ int Ivy_ManPropagateBuffers( Ivy_Man_t * p, int fUpdateLevel )
break;
}
}
printf( "Number of steps = %d. Nodes beg = %d. Nodes end = %d.\n", nSteps, NodeBeg, Ivy_ManNodeNum(p) );
// printf( "Number of steps = %d. Nodes beg = %d. Nodes end = %d.\n", nSteps, NodeBeg, Ivy_ManNodeNum(p) );
return nSteps;
}

0
src/temp/ivy/ivyMem.c → src/aig/ivy/ivyMem.c
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0
src/temp/ivy/ivyMulti.c → src/aig/ivy/ivyMulti.c
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0
src/temp/ivy/ivyMulti8.c → src/aig/ivy/ivyMulti8.c
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0
src/temp/ivy/ivyObj.c → src/aig/ivy/ivyObj.c
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0
src/temp/ivy/ivyOper.c → src/aig/ivy/ivyOper.c
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0
src/temp/ivy/ivyResyn.c → src/aig/ivy/ivyResyn.c
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0
src/temp/ivy/ivyRwr.c → src/aig/ivy/ivyRwr.c
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0
src/temp/ivy/ivyRwrAlg.c → src/aig/ivy/ivyRwrAlg.c
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2
src/temp/ivy/ivySeq.c → src/aig/ivy/ivySeq.c
View File

@ -53,7 +53,7 @@ static inline int Ivy_CutHashValue( int NodeId ) { return 1 << (NodeId % 31); }
***********************************************************************/
int Ivy_ManRewriteSeq( Ivy_Man_t * p, int fUseZeroCost, int fVerbose )
{
{
Rwt_Man_t * pManRwt;
Ivy_Obj_t * pNode;
int i, nNodes, nGain;

0
src/temp/ivy/ivyShow.c → src/aig/ivy/ivyShow.c
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0
src/temp/ivy/ivyTable.c → src/aig/ivy/ivyTable.c
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0
src/temp/ivy/ivyUtil.c → src/aig/ivy/ivyUtil.c
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0
src/temp/ivy/ivy_.c → src/aig/ivy/ivy_.c
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23
src/aig/ivy/module.make Normal file
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@ -0,0 +1,23 @@
SRC += src/aig/ivy/ivyBalance.c \
src/aig/ivy/ivyCanon.c \
src/aig/ivy/ivyCheck.c \
src/aig/ivy/ivyCut.c \
src/aig/ivy/ivyCutTrav.c \
src/aig/ivy/ivyDfs.c \
src/aig/ivy/ivyDsd.c \
src/aig/ivy/ivyFanout.c \
src/aig/ivy/ivyFastMap.c \
src/aig/ivy/ivyFraig.c \
src/aig/ivy/ivyHaig.c \
src/aig/ivy/ivyIsop.c \
src/aig/ivy/ivyMan.c \
src/aig/ivy/ivyMem.c \
src/aig/ivy/ivyMulti.c \
src/aig/ivy/ivyObj.c \
src/aig/ivy/ivyOper.c \
src/aig/ivy/ivyResyn.c \
src/aig/ivy/ivyRwr.c \
src/aig/ivy/ivySeq.c \
src/aig/ivy/ivyShow.c \
src/aig/ivy/ivyTable.c \
src/aig/ivy/ivyUtil.c

0
src/temp/mem/mem.c → src/aig/mem/mem.c
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0
src/temp/mem/mem.h → src/aig/mem/mem.h
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1
src/aig/mem/module.make Normal file
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@ -0,0 +1 @@
SRC += src/aig/mem/mem.c

3
src/aig/rwt/module.make Normal file
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@ -0,0 +1,3 @@
SRC += src/hop/rwt/rwtDec.c \
src/hop/rwt/rwtMan.c \
src/hop/rwt/rwtUtil.c

0
src/temp/rwt/rwt.h → src/aig/rwt/rwt.h
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0
src/temp/rwt/rwtDec.c → src/aig/rwt/rwtDec.c
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0
src/temp/rwt/rwtMan.c → src/aig/rwt/rwtMan.c
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0
src/temp/rwt/rwtUtil.c → src/aig/rwt/rwtUtil.c
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37
src/base/abc/abc.h
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@ -36,7 +36,7 @@ extern "C" {
#include <time.h>
#include "cuddInt.h"
#include "aig.h"
#include "hop.h"
#include "extra.h"
#include "solver.h"
#include "vec.h"
@ -178,7 +178,6 @@ struct Abc_Ntk_t_
Vec_Ptr_t * vPios; // the array of PIOs
Vec_Ptr_t * vAsserts; // the array of assertions
Vec_Ptr_t * vBoxes; // the array of boxes
Vec_Ptr_t * vCutSet; // the array of cutset nodes (used in the sequential AIG)
// the number of living objects
int nObjs; // the number of live objs
int nObjCounts[ABC_OBJ_NUMBER]; // the number of objects by type
@ -196,8 +195,6 @@ struct Abc_Ntk_t_
Extra_MmStep_t * pMmStep; // memory manager for arrays
void * pManFunc; // functionality manager (AIG manager, BDD manager, or memory manager for SOPs)
// Abc_Lib_t * pVerLib; // for structural verilog designs
void * pManGlob; // the global BDD manager
Vec_Ptr_t * vFuncsGlob; // the global BDDs of CO functions
Abc_ManTime_t * pManTime; // the timing manager (for mapped networks) stores arrival/required times for all nodes
void * pManCut; // the cut manager (for AIGs) stores information about the cuts computed for the nodes
int LevelMax; // maximum number of levels
@ -206,10 +203,8 @@ struct Abc_Ntk_t_
int * pModel; // counter-example (for miters)
Abc_Ntk_t * pExdc; // the EXDC network (if given)
void * pData; // misc
// skew values (for latches)
float maxMeanCycle; // maximum mean cycle time
float globalSkew; // global skewing
Vec_Flt_t * vSkews; // endpoint skewing
// node attributes
Vec_Ptr_t * vAttrs; // managers of various node attributes (node functionality, global BDDs, etc)
};
struct Abc_Lib_t_
@ -282,7 +277,6 @@ static inline int Abc_NtkCiNum( Abc_Ntk_t * pNtk ) { return Ve
static inline int Abc_NtkCoNum( Abc_Ntk_t * pNtk ) { return Vec_PtrSize(pNtk->vCos); }
static inline int Abc_NtkAssertNum( Abc_Ntk_t * pNtk ) { return Vec_PtrSize(pNtk->vAsserts); }
static inline int Abc_NtkBoxNum( Abc_Ntk_t * pNtk ) { return Vec_PtrSize(pNtk->vBoxes); }
static inline int Abc_NtkCutSetNodeNum( Abc_Ntk_t * pNtk ) { return Vec_PtrSize(pNtk->vCutSet); }
static inline int Abc_NtkBiNum( Abc_Ntk_t * pNtk ) { return pNtk->nObjCounts[ABC_OBJ_BI]; }
static inline int Abc_NtkBoNum( Abc_Ntk_t * pNtk ) { return pNtk->nObjCounts[ABC_OBJ_BO]; }
static inline int Abc_NtkNetNum( Abc_Ntk_t * pNtk ) { return pNtk->nObjCounts[ABC_OBJ_NET]; }
@ -315,7 +309,6 @@ static inline Abc_Obj_t * Abc_NtkCi( Abc_Ntk_t * pNtk, int i ) { return (A
static inline Abc_Obj_t * Abc_NtkCo( Abc_Ntk_t * pNtk, int i ) { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vCos, i ); }
static inline Abc_Obj_t * Abc_NtkAssert( Abc_Ntk_t * pNtk, int i ) { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vAsserts, i );}
static inline Abc_Obj_t * Abc_NtkBox( Abc_Ntk_t * pNtk, int i ) { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vBoxes, i ); }
static inline Abc_Obj_t * Abc_NtkCutSetNode( Abc_Ntk_t * pNtk, int i){ return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vCutSet, i ); }
// reading data members of the object
static inline unsigned Abc_ObjType( Abc_Obj_t * pObj ) { return pObj->Type; }
@ -409,9 +402,12 @@ static inline bool Abc_LatchIsInit1( Abc_Obj_t * pLatch ) { assert(Ab
static inline bool Abc_LatchIsInitDc( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return pLatch->pData == (void *)ABC_INIT_DC; }
static inline int Abc_LatchInit( Abc_Obj_t * pLatch ) { assert(Abc_ObjIsLatch(pLatch)); return (int)pLatch->pData; }
// skewing latches
static inline void Abc_NtkSetLatSkew ( Abc_Ntk_t * pNtk, int lat, float skew ) { Vec_FltWriteEntry( pNtk->vSkews, lat, skew ); }
static inline float Abc_NtkGetLatSkew ( Abc_Ntk_t * pNtk, int lat ) { if (lat >= Vec_FltSize( pNtk->vSkews )) return 0; else return Vec_FltEntry( pNtk->vSkews, lat ); }
// global BDDs of the nodes
static inline void * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk ) { return (void *)Vec_PtrEntry(pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD); }
static inline DdManager * Abc_NtkGlobalBddMan( Abc_Ntk_t * pNtk ) { return (DdManager *)Vec_AttMan( Abc_NtkGlobalBdds(pNtk) ); }
static inline DdNode ** Abc_NtkGlobalBddArray( Abc_Ntk_t * pNtk ) { return (DdNode **)Vec_AttArray( Abc_NtkGlobalBdds(pNtk) ); }
static inline DdNode * Abc_ObjGlobalBdd( Abc_Obj_t * pObj ) { return (DdNode *)Vec_AttEntry( Abc_NtkGlobalBdds(pObj->pNtk), pObj->Id ); }
static inline void Abc_ObjSetGlobalBdd( Abc_Obj_t * pObj, DdNode * bF ) { Vec_AttWriteEntry( Abc_NtkGlobalBdds(pObj->pNtk), pObj->Id, bF ); }
// outputs the runtime in seconds
#define PRT(a,t) printf("%s = ", (a)); printf("%6.2f sec\n", (float)(t)/(float)(CLOCKS_PER_SEC))
@ -436,9 +432,6 @@ static inline float Abc_NtkGetLatSkew ( Abc_Ntk_t * pNtk, int lat )
#define Abc_AigForEachAnd( pNtk, pNode, i ) \
for ( i = 0; (i < Vec_PtrSize((pNtk)->vObjs)) && (((pNode) = Abc_NtkObj(pNtk, i)), 1); i++ ) \
if ( (pNode) == NULL || !Abc_AigNodeIsAnd(pNode) ) {} else
#define Abc_SeqForEachCutsetNode( pNtk, pNode, i ) \
for ( i = 0; (i < Abc_NtkCutSetNodeNum(pNtk)) && (((pNode) = Abc_NtkCutSetNode(pNtk, i)), 1); i++ )\
if ( (pNode) == NULL ) {} else
// various boxes
#define Abc_NtkForEachBox( pNtk, pObj, i ) \
for ( i = 0; (i < Vec_PtrSize((pNtk)->vBoxes)) && (((pObj) = Abc_NtkBox(pNtk, i)), 1); i++ )
@ -489,7 +482,7 @@ extern Abc_Aig_t * Abc_AigAlloc( Abc_Ntk_t * pNtk );
extern void Abc_AigFree( Abc_Aig_t * pMan );
extern int Abc_AigCleanup( Abc_Aig_t * pMan );
extern bool Abc_AigCheck( Abc_Aig_t * pMan );
extern int Abc_AigGetLevelNum( Abc_Ntk_t * pNtk );
extern int Abc_AigLevel( Abc_Ntk_t * pNtk );
extern Abc_Obj_t * Abc_AigConst1( Abc_Ntk_t * pNtk );
extern Abc_Obj_t * Abc_AigAnd( Abc_Aig_t * pMan, Abc_Obj_t * p0, Abc_Obj_t * p1 );
extern Abc_Obj_t * Abc_AigAndLookup( Abc_Aig_t * pMan, Abc_Obj_t * p0, Abc_Obj_t * p1 );
@ -536,7 +529,8 @@ extern Vec_Ptr_t * Abc_NtkSupport( Abc_Ntk_t * pNtk );
extern Vec_Ptr_t * Abc_NtkNodeSupport( Abc_Ntk_t * pNtk, Abc_Obj_t ** ppNodes, int nNodes );
extern Vec_Ptr_t * Abc_AigDfs( Abc_Ntk_t * pNtk, int fCollectAll, int fCollectCos );
extern Vec_Vec_t * Abc_DfsLevelized( Abc_Obj_t * pNode, bool fTfi );
extern int Abc_NtkGetLevelNum( Abc_Ntk_t * pNtk );
extern int Abc_NtkLevel( Abc_Ntk_t * pNtk );
extern int Abc_NtkLevelReverse( Abc_Ntk_t * pNtk );
extern bool Abc_NtkIsAcyclic( Abc_Ntk_t * pNtk );
extern Vec_Ptr_t * Abc_AigGetLevelizedOrder( Abc_Ntk_t * pNtk, int fCollectCis );
/*=== abcFanio.c ==========================================================*/
@ -652,8 +646,8 @@ extern Abc_Ntk_t * Abc_NtkAigToLogicSopBench( Abc_Ntk_t * pNtk );
/*=== abcNtbdd.c ==========================================================*/
extern Abc_Ntk_t * Abc_NtkDeriveFromBdd( DdManager * dd, DdNode * bFunc, char * pNamePo, Vec_Ptr_t * vNamesPi );
extern Abc_Ntk_t * Abc_NtkBddToMuxes( Abc_Ntk_t * pNtk );
extern DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int fBddSizeMax, int fLatchOnly, int fReorder, int fVerbose );
extern void Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk );
extern DdManager * Abc_NtkBuildGlobalBdds( Abc_Ntk_t * pNtk, int fBddSizeMax, int fDropInternal, int fReorder, int fVerbose );
extern DdManager * Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk, int fFreeMan );
/*=== abcNtk.c ==========================================================*/
extern Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan );
extern Abc_Ntk_t * Abc_NtkStartFrom( Abc_Ntk_t * pNtk, Abc_NtkType_t Type, Abc_NtkFunc_t Func );
@ -759,7 +753,7 @@ extern Abc_Ntk_t * Abc_NtkTopmost( Abc_Ntk_t * pNtk, int nLevels );
/*=== abcSweep.c ==========================================================*/
extern int Abc_NtkSweep( Abc_Ntk_t * pNtk, int fVerbose );
extern int Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose );
extern int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fVerbose );
extern int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fLatchSweep, int fAutoSweep, int fVerbose );
/*=== abcTiming.c ==========================================================*/
extern Abc_Time_t * Abc_NodeReadArrival( Abc_Obj_t * pNode );
extern Abc_Time_t * Abc_NodeReadRequired( Abc_Obj_t * pNode );
@ -782,6 +776,7 @@ extern void Abc_NodeSetReverseLevel( Abc_Obj_t * pObj, int LevelR
extern int Abc_NodeReadReverseLevel( Abc_Obj_t * pObj );
extern int Abc_NodeReadRequiredLevel( Abc_Obj_t * pObj );
/*=== abcUtil.c ==========================================================*/
extern void * Abc_NtkAttrFree( Abc_Ntk_t * pNtk, int Attr, int fFreeMan );
extern void Abc_NtkIncrementTravId( Abc_Ntk_t * pNtk );
extern void Abc_NtkOrderCisCos( Abc_Ntk_t * pNtk );
extern int Abc_NtkGetCubeNum( Abc_Ntk_t * pNtk );

2
src/base/abc/abcAig.c
View File

@ -269,7 +269,7 @@ bool Abc_AigCheck( Abc_Aig_t * pMan )
SeeAlso []
***********************************************************************/
int Abc_AigGetLevelNum( Abc_Ntk_t * pNtk )
int Abc_AigLevel( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, LevelsMax;

23
src/base/abc/abcCheck.c
View File

@ -580,12 +580,33 @@ bool Abc_NtkCheckLatch( Abc_Ntk_t * pNtk, Abc_Obj_t * pLatch )
fprintf( stdout, "NodeCheck: Latch \"%s\" has wrong number (%d) of fanins.\n", Abc_ObjName(pLatch), Abc_ObjFaninNum(pLatch) );
Value = 0;
}
// make sure the latch has only one fanin
// make sure the latch has only one fanout
if ( Abc_ObjFanoutNum(pLatch) != 1 )
{
fprintf( stdout, "NodeCheck: Latch \"%s\" has wrong number (%d) of fanouts.\n", Abc_ObjName(pLatch), Abc_ObjFanoutNum(pLatch) );
Value = 0;
}
// make sure the latch input has only one fanin
if ( Abc_ObjFaninNum(Abc_ObjFanin0(pLatch)) != 1 )
{
fprintf( stdout, "NodeCheck: Input of latch \"%s\" has wrong number (%d) of fanins.\n",
Abc_ObjName(Abc_ObjFanin0(pLatch)), Abc_ObjFaninNum(Abc_ObjFanin0(pLatch)) );
Value = 0;
}
// make sure the latch input has only one fanout
if ( Abc_ObjFanoutNum(Abc_ObjFanin0(pLatch)) != 1 )
{
fprintf( stdout, "NodeCheck: Input of latch \"%s\" has wrong number (%d) of fanouts.\n",
Abc_ObjName(Abc_ObjFanin0(pLatch)), Abc_ObjFanoutNum(Abc_ObjFanin0(pLatch)) );
Value = 0;
}
// make sure the latch output has only one fanin
if ( Abc_ObjFaninNum(Abc_ObjFanout0(pLatch)) != 1 )
{
fprintf( stdout, "NodeCheck: Output of latch \"%s\" has wrong number (%d) of fanins.\n",
Abc_ObjName(Abc_ObjFanout0(pLatch)), Abc_ObjFaninNum(Abc_ObjFanout0(pLatch)) );
Value = 0;
}
return Value;
}

215
src/base/abc/abcDfs.c
View File

@ -24,12 +24,12 @@
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static void Abc_NtkDfs_iter( Vec_Ptr_t * vStack, Abc_Obj_t * pRoot, Vec_Ptr_t * vNodes );
static void Abc_NtkDfs_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
static void Abc_AigDfs_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
static void Abc_NtkDfsReverse_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
static void Abc_NtkNodeSupport_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
static void Abc_DfsLevelizedTfo_rec( Abc_Obj_t * pNode, Vec_Vec_t * vLevels );
static int Abc_NtkGetLevelNum_rec( Abc_Obj_t * pNode );
static bool Abc_NtkIsAcyclic_rec( Abc_Obj_t * pNode );
////////////////////////////////////////////////////////////////////////
@ -137,6 +137,101 @@ void Abc_NtkDfs_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
Vec_PtrPush( vNodes, pNode );
}
/**Function*************************************************************
Synopsis [Returns the DFS ordered array of logic nodes.]
Description [Collects only the internal nodes, leaving CIs and CO.
However it marks with the current TravId both CIs and COs.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NtkDfsIter( Abc_Ntk_t * pNtk, int fCollectAll )
{
Vec_Ptr_t * vNodes, * vStack;
Abc_Obj_t * pObj;
int i;
// set the traversal ID
Abc_NtkIncrementTravId( pNtk );
// start the array of nodes
vNodes = Vec_PtrAlloc( 1000 );
vStack = Vec_PtrAlloc( 1000 );
Abc_NtkForEachCo( pNtk, pObj, i )
{
Abc_NodeSetTravIdCurrent( pObj );
Abc_NtkDfs_iter( vStack, Abc_ObjFanin0Ntk(Abc_ObjFanin0(pObj)), vNodes );
}
// collect dangling nodes if asked to
if ( fCollectAll )
{
Abc_NtkForEachNode( pNtk, pObj, i )
if ( !Abc_NodeIsTravIdCurrent(pObj) )
Abc_NtkDfs_iter( vStack, pObj, vNodes );
}
Vec_PtrFree( vStack );
return vNodes;
}
/**Function*************************************************************
Synopsis [Iterative version of the DFS procedure.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkDfs_iter( Vec_Ptr_t * vStack, Abc_Obj_t * pRoot, Vec_Ptr_t * vNodes )
{
Abc_Obj_t * pNode, * pFanin;
int iFanin;
// if this node is already visited, skip
if ( Abc_NodeIsTravIdCurrent( pRoot ) )
return;
// mark the node as visited
Abc_NodeSetTravIdCurrent( pRoot );
// skip the CI
if ( Abc_ObjIsCi(pRoot) || (Abc_NtkIsStrash(pRoot->pNtk) && Abc_AigNodeIsConst(pRoot)) )
return;
// add the CI
Vec_PtrClear( vStack );
Vec_PtrPush( vStack, pRoot );
Vec_PtrPush( vStack, (void *)0 );
while ( Vec_PtrSize(vStack) > 0 )
{
// get the node and its fanin
iFanin = (int)Vec_PtrPop(vStack);
pNode = Vec_PtrPop(vStack);
assert( !Abc_ObjIsNet(pNode) );
// add it to the array of nodes if we finished
if ( iFanin == Abc_ObjFaninNum(pNode) )
{
Vec_PtrPush( vNodes, pNode );
continue;
}
// explore the next fanin
Vec_PtrPush( vStack, pNode );
Vec_PtrPush( vStack, (void *)(iFanin+1) );
// get the fanin
pFanin = Abc_ObjFanin0Ntk( Abc_ObjFanin(pNode,iFanin) );
// if this node is already visited, skip
if ( Abc_NodeIsTravIdCurrent( pFanin ) )
continue;
// mark the node as visited
Abc_NodeSetTravIdCurrent( pFanin );
// skip the CI
if ( Abc_ObjIsCi(pFanin) || (Abc_NtkIsStrash(pFanin->pNtk) && Abc_AigNodeIsConst(pFanin)) )
continue;
Vec_PtrPush( vStack, pFanin );
Vec_PtrPush( vStack, (void *)0 );
}
}
/**Function*************************************************************
@ -593,7 +688,7 @@ void Abc_DfsLevelizedTfo_rec( Abc_Obj_t * pNode, Vec_Vec_t * vLevels )
/**Function*************************************************************
Synopsis [Computes the number of logic levels not counting PIs/POs.]
Synopsis [Recursively counts the number of logic levels of one node.]
Description []
@ -602,24 +697,31 @@ void Abc_DfsLevelizedTfo_rec( Abc_Obj_t * pNode, Vec_Vec_t * vLevels )
SeeAlso []
***********************************************************************/
int Abc_NtkGetLevelNum( Abc_Ntk_t * pNtk )
int Abc_NtkLevel_rec( Abc_Obj_t * pNode )
{
Abc_Obj_t * pNode;
int i, LevelsMax;
// set the traversal ID for this traversal
Abc_NtkIncrementTravId( pNtk );
// set the CI levels to zero
Abc_NtkForEachCi( pNtk, pNode, i )
pNode->Level = 0;
// perform the traversal
LevelsMax = 0;
Abc_NtkForEachNode( pNtk, pNode, i )
Abc_Obj_t * pNext;
int i, Level;
assert( !Abc_ObjIsNet(pNode) );
// skip the PI
if ( Abc_ObjIsCi(pNode) )
return pNode->Level;
assert( Abc_ObjIsNode( pNode ) );
// if this node is already visited, return
if ( Abc_NodeIsTravIdCurrent( pNode ) )
return pNode->Level;
// mark the node as visited
Abc_NodeSetTravIdCurrent( pNode );
// visit the transitive fanin
pNode->Level = 0;
Abc_ObjForEachFanin( pNode, pNext, i )
{
Abc_NtkGetLevelNum_rec( pNode );
if ( LevelsMax < (int)pNode->Level )
LevelsMax = (int)pNode->Level;
Level = Abc_NtkLevel_rec( Abc_ObjFanin0Ntk(pNext) );
if ( pNode->Level < (unsigned)Level )
pNode->Level = Level;
}
return LevelsMax;
if ( Abc_ObjFaninNum(pNode) > 0 )
pNode->Level++;
return pNode->Level;
}
/**Function*************************************************************
@ -633,18 +735,14 @@ int Abc_NtkGetLevelNum( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
int Abc_NtkGetLevelNum_rec( Abc_Obj_t * pNode )
int Abc_NtkLevelReverse_rec( Abc_Obj_t * pNode )
{
Abc_Obj_t * pFanin;
Abc_Obj_t * pNext;
int i, Level;
assert( !Abc_ObjIsNet(pNode) );
if ( pNode->Id == 27278 )
{
int x = 0;
}
// skip the PI
if ( Abc_ObjIsCi(pNode) )
return 0;
if ( Abc_ObjIsCo(pNode) )
return pNode->Level;
assert( Abc_ObjIsNode( pNode ) );
// if this node is already visited, return
if ( Abc_NodeIsTravIdCurrent( pNode ) )
@ -653,17 +751,76 @@ int Abc_NtkGetLevelNum_rec( Abc_Obj_t * pNode )
Abc_NodeSetTravIdCurrent( pNode );
// visit the transitive fanin
pNode->Level = 0;
Abc_ObjForEachFanin( pNode, pFanin, i )
Abc_ObjForEachFanout( pNode, pNext, i )
{
Level = Abc_NtkGetLevelNum_rec( Abc_ObjFanin0Ntk(pFanin) );
Level = Abc_NtkLevelReverse_rec( Abc_ObjFanout0Ntk(pNext) );
if ( pNode->Level < (unsigned)Level )
pNode->Level = Level;
}
if ( Abc_ObjFaninNum(pNode) > 0 )
pNode->Level++;
pNode->Level++;
return pNode->Level;
}
/**Function*************************************************************
Synopsis [Computes the number of logic levels not counting PIs/POs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkLevel( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, LevelsMax;
// set the CI levels to zero
Abc_NtkForEachCi( pNtk, pNode, i )
pNode->Level = 0;
// perform the traversal
LevelsMax = 0;
Abc_NtkIncrementTravId( pNtk );
Abc_NtkForEachNode( pNtk, pNode, i )
{
Abc_NtkLevel_rec( pNode );
if ( LevelsMax < (int)pNode->Level )
LevelsMax = (int)pNode->Level;
}
return LevelsMax;
}
/**Function*************************************************************
Synopsis [Computes the number of logic levels not counting PIs/POs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkLevelReverse( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, LevelsMax;
// set the CO levels to zero
Abc_NtkForEachCo( pNtk, pNode, i )
pNode->Level = 0;
// perform the traversal
LevelsMax = 0;
Abc_NtkIncrementTravId( pNtk );
Abc_NtkForEachNode( pNtk, pNode, i )
{
Abc_NtkLevelReverse_rec( pNode );
if ( LevelsMax < (int)pNode->Level )
LevelsMax = (int)pNode->Level;
}
return LevelsMax;
}
/**Function*************************************************************

4
src/base/abc/abcFanio.c
View File

@ -50,6 +50,10 @@ void Abc_ObjAddFanin( Abc_Obj_t * pObj, Abc_Obj_t * pFanin )
Vec_IntPushMem( pObj->pNtk->pMmStep, &pFaninR->vFanouts, pObj->Id );
if ( Abc_ObjIsComplement(pFanin) )
Abc_ObjSetFaninC( pObj, Abc_ObjFaninNum(pObj)-1 );
if ( Abc_ObjIsNet(pObj) && Abc_ObjFaninNum(pObj) > 1 )
{
int x = 0;
}
}

82
src/base/abc/abcFunc.c
View File

@ -29,8 +29,8 @@
#define ABC_MUX_CUBES 100000
static int Abc_ConvertZddToSop( DdManager * dd, DdNode * zCover, char * pSop, int nFanins, Vec_Str_t * vCube, int fPhase );
static DdNode * Abc_ConvertAigToBdd( DdManager * dd, Aig_Obj_t * pRoot);
static Aig_Obj_t * Abc_ConvertSopToAig( Aig_Man_t * pMan, char * pSop );
static DdNode * Abc_ConvertAigToBdd( DdManager * dd, Hop_Obj_t * pRoot);
static Hop_Obj_t * Abc_ConvertSopToAig( Hop_Man_t * pMan, char * pSop );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@ -533,13 +533,13 @@ int Abc_CountZddCubes( DdManager * dd, DdNode * zCover )
int Abc_NtkSopToAig( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
Aig_Man_t * pMan;
Hop_Man_t * pMan;
int i;
assert( Abc_NtkIsSopLogic(pNtk) || Abc_NtkIsSopNetlist(pNtk) );
// start the functionality manager
pMan = Aig_ManStart();
pMan = Hop_ManStart();
// convert each node from SOP to BDD
Abc_NtkForEachNode( pNtk, pNode, i )
@ -572,32 +572,32 @@ int Abc_NtkSopToAig( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Abc_ConvertSopToAigInternal( Aig_Man_t * pMan, char * pSop )
Hop_Obj_t * Abc_ConvertSopToAigInternal( Hop_Man_t * pMan, char * pSop )
{
Aig_Obj_t * pAnd, * pSum;
Hop_Obj_t * pAnd, * pSum;
int i, Value, nFanins;
char * pCube;
// get the number of variables
nFanins = Abc_SopGetVarNum(pSop);
// go through the cubes of the node's SOP
pSum = Aig_ManConst0(pMan);
pSum = Hop_ManConst0(pMan);
Abc_SopForEachCube( pSop, nFanins, pCube )
{
// create the AND of literals
pAnd = Aig_ManConst1(pMan);
pAnd = Hop_ManConst1(pMan);
Abc_CubeForEachVar( pCube, Value, i )
{
if ( Value == '1' )
pAnd = Aig_And( pMan, pAnd, Aig_IthVar(pMan,i) );
pAnd = Hop_And( pMan, pAnd, Hop_IthVar(pMan,i) );
else if ( Value == '0' )
pAnd = Aig_And( pMan, pAnd, Aig_Not(Aig_IthVar(pMan,i)) );
pAnd = Hop_And( pMan, pAnd, Hop_Not(Hop_IthVar(pMan,i)) );
}
// add to the sum of cubes
pSum = Aig_Or( pMan, pSum, pAnd );
pSum = Hop_Or( pMan, pSum, pAnd );
}
// decide whether to complement the result
if ( Abc_SopIsComplement(pSop) )
pSum = Aig_Not(pSum);
pSum = Hop_Not(pSum);
return pSum;
}
@ -612,16 +612,16 @@ Aig_Obj_t * Abc_ConvertSopToAigInternal( Aig_Man_t * pMan, char * pSop )
SeeAlso []
***********************************************************************/
Aig_Obj_t * Abc_ConvertSopToAig( Aig_Man_t * pMan, char * pSop )
Hop_Obj_t * Abc_ConvertSopToAig( Hop_Man_t * pMan, char * pSop )
{
extern Aig_Obj_t * Dec_GraphFactorSop( Aig_Man_t * pMan, char * pSop );
extern Hop_Obj_t * Dec_GraphFactorSop( Hop_Man_t * pMan, char * pSop );
int fUseFactor = 1;
// consider the constant node
if ( Abc_SopGetVarNum(pSop) == 0 )
return Aig_NotCond( Aig_ManConst1(pMan), Abc_SopIsConst0(pSop) );
return Hop_NotCond( Hop_ManConst1(pMan), Abc_SopIsConst0(pSop) );
// consider the special case of EXOR function
if ( Abc_SopIsExorType(pSop) )
return Aig_NotCond( Aig_CreateExor(pMan, Abc_SopGetVarNum(pSop)), Abc_SopIsComplement(pSop) );
return Hop_NotCond( Hop_CreateExor(pMan, Abc_SopGetVarNum(pSop)), Abc_SopIsComplement(pSop) );
// decide when to use factoring
if ( fUseFactor && Abc_SopGetVarNum(pSop) > 2 && Abc_SopGetCubeNum(pSop) > 1 )
return Dec_GraphFactorSop( pMan, pSop );
@ -642,7 +642,7 @@ Aig_Obj_t * Abc_ConvertSopToAig( Aig_Man_t * pMan, char * pSop )
int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
Aig_Man_t * pMan;
Hop_Man_t * pMan;
DdManager * dd;
int nFaninsMax, i;
@ -657,9 +657,9 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
// set the mapping of AIG nodes into the BDD nodes
pMan = pNtk->pManFunc;
assert( Aig_ManPiNum(pMan) >= nFaninsMax );
assert( Hop_ManPiNum(pMan) >= nFaninsMax );
for ( i = 0; i < nFaninsMax; i++ )
Aig_ManPi(pMan, i)->pData = Cudd_bddIthVar(dd, i);
Hop_ManPi(pMan, i)->pData = Cudd_bddIthVar(dd, i);
// convert each node from SOP to BDD
Abc_NtkForEachNode( pNtk, pNode, i )
@ -674,7 +674,7 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
Cudd_Ref( pNode->pData );
}
Aig_ManStop( pNtk->pManFunc );
Hop_ManStop( pNtk->pManFunc );
pNtk->pManFunc = dd;
// update the network type
@ -693,17 +693,17 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
void Abc_ConvertAigToBdd_rec1( DdManager * dd, Aig_Obj_t * pObj )
void Abc_ConvertAigToBdd_rec1( DdManager * dd, Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return;
Abc_ConvertAigToBdd_rec1( dd, Aig_ObjFanin0(pObj) );
Abc_ConvertAigToBdd_rec1( dd, Aig_ObjFanin1(pObj) );
pObj->pData = Cudd_bddAnd( dd, (DdNode *)Aig_ObjChild0Copy(pObj), (DdNode *)Aig_ObjChild1Copy(pObj) );
Abc_ConvertAigToBdd_rec1( dd, Hop_ObjFanin0(pObj) );
Abc_ConvertAigToBdd_rec1( dd, Hop_ObjFanin1(pObj) );
pObj->pData = Cudd_bddAnd( dd, (DdNode *)Hop_ObjChild0Copy(pObj), (DdNode *)Hop_ObjChild1Copy(pObj) );
Cudd_Ref( pObj->pData );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
}
/**Function*************************************************************
@ -717,17 +717,17 @@ void Abc_ConvertAigToBdd_rec1( DdManager * dd, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
void Abc_ConvertAigToBdd_rec2( DdManager * dd, Aig_Obj_t * pObj )
void Abc_ConvertAigToBdd_rec2( DdManager * dd, Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || !Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || !Hop_ObjIsMarkA(pObj) )
return;
Abc_ConvertAigToBdd_rec2( dd, Aig_ObjFanin0(pObj) );
Abc_ConvertAigToBdd_rec2( dd, Aig_ObjFanin1(pObj) );
Abc_ConvertAigToBdd_rec2( dd, Hop_ObjFanin0(pObj) );
Abc_ConvertAigToBdd_rec2( dd, Hop_ObjFanin1(pObj) );
Cudd_RecursiveDeref( dd, pObj->pData );
pObj->pData = NULL;
assert( Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjClearMarkA( pObj );
assert( Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjClearMarkA( pObj );
}
/**Function*************************************************************
@ -741,18 +741,18 @@ void Abc_ConvertAigToBdd_rec2( DdManager * dd, Aig_Obj_t * pObj )
SeeAlso []
***********************************************************************/
DdNode * Abc_ConvertAigToBdd( DdManager * dd, Aig_Obj_t * pRoot )
DdNode * Abc_ConvertAigToBdd( DdManager * dd, Hop_Obj_t * pRoot )
{
DdNode * bFunc;
// check the case of a constant
if ( Aig_ObjIsConst1( Aig_Regular(pRoot) ) )
return Cudd_NotCond( Cudd_ReadOne(dd), Aig_IsComplement(pRoot) );
if ( Hop_ObjIsConst1( Hop_Regular(pRoot) ) )
return Cudd_NotCond( Cudd_ReadOne(dd), Hop_IsComplement(pRoot) );
// construct BDD
Abc_ConvertAigToBdd_rec1( dd, Aig_Regular(pRoot) );
Abc_ConvertAigToBdd_rec1( dd, Hop_Regular(pRoot) );
// hold on to the result
bFunc = Cudd_NotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) ); Cudd_Ref( bFunc );
bFunc = Cudd_NotCond( Hop_Regular(pRoot)->pData, Hop_IsComplement(pRoot) ); Cudd_Ref( bFunc );
// dereference BDD
Abc_ConvertAigToBdd_rec2( dd, Aig_Regular(pRoot) );
Abc_ConvertAigToBdd_rec2( dd, Hop_Regular(pRoot) );
// return the result
Cudd_Deref( bFunc );
return bFunc;

4
src/base/abc/abcLatch.c
View File

@ -117,11 +117,11 @@ int Abc_NtkRemoveSelfFeedLatches( Abc_Ntk_t * pNtk )
{
if ( Abc_NtkLatchIsSelfFeed( pLatch ) )
{
if ( Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) )
if ( Abc_NtkIsStrash(pNtk) )
pConst1 = Abc_AigConst1(pNtk);
else
pConst1 = Abc_NtkCreateNodeConst1(pNtk);
Abc_ObjPatchFanin( pLatch, Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pConst1 );
Abc_ObjPatchFanin( Abc_ObjFanin0(pLatch), Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pConst1 );
Counter++;
}
}

4
src/base/abc/abcLib.c
View File

@ -47,7 +47,7 @@ Abc_Lib_t * Abc_LibCreate( char * pName )
p->pName = Extra_UtilStrsav( pName );
p->tModules = st_init_table( strcmp, st_strhash );
p->vModules = Vec_PtrAlloc( 100 );
p->pManFunc = Aig_ManStart();
p->pManFunc = Hop_ManStart();
p->pLibrary = NULL;
return p;
}
@ -70,7 +70,7 @@ void Abc_LibFree( Abc_Lib_t * pLib )
if ( pLib->pName )
free( pLib->pName );
if ( pLib->pManFunc )
Aig_ManStop( pLib->pManFunc );
Hop_ManStop( pLib->pManFunc );
if ( pLib->tModules )
st_free_table( pLib->tModules );
if ( pLib->vModules )

22
src/base/abc/abcNetlist.c
View File

@ -251,15 +251,6 @@ Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk, int fDirect )
pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
Abc_NtkDelete( pNtkTemp );
}
else if ( Abc_NtkIsSeq(pNtk) )
{
assert( 0 );
/*
pNtkTemp = Abc_NtkSeqToLogicSop(pNtk);
pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
Abc_NtkDelete( pNtkTemp );
*/
}
else if ( Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, fDirect) )
@ -328,13 +319,22 @@ Abc_Ntk_t * Abc_NtkLogicSopToNetlist( Abc_Ntk_t * pNtk )
Abc_NtkCleanup( pNtk, 0 );
assert( Abc_NtkIsLogic(pNtk) );
assert( Abc_NtkLogicHasSimpleCos(pNtk) );
// assert( Abc_NtkLogicHasSimpleCos(pNtk) );
if ( !Abc_NtkLogicHasSimpleCos(pNtk) )
{
printf( "Abc_NtkLogicSopToNetlist() warning: The network is converted to have simple COs.\n" );
Abc_NtkLogicMakeSimpleCos( pNtk, 0 );
}
if ( Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk,0) )
return NULL;
}
// Abc_NtkForEachCo(pNtk, pObj, i)
// Abc_ObjPrint( stdout, Abc_ObjFanin0(pObj) );
// start the netlist by creating PI/PO/Latch objects
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_NETLIST, pNtk->ntkFunc );
// create the CI nets and remember them in the new CI nodes
@ -358,7 +358,7 @@ Abc_Ntk_t * Abc_NtkLogicSopToNetlist( Abc_Ntk_t * pNtk )
continue;
}
assert( Abc_ObjIsNode(pDriver) );
// if the CO drive has no net, create it
// if the CO driver has no net, create it
if ( pDriver->pCopy->pCopy == NULL )
{
// create the CO net and connect it to CO

50
src/base/abc/abcNtk.c
View File

@ -58,9 +58,7 @@ Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan
pNtk->vPos = Vec_PtrAlloc( 100 );
pNtk->vCis = Vec_PtrAlloc( 100 );
pNtk->vCos = Vec_PtrAlloc( 100 );
pNtk->vCutSet = Vec_PtrAlloc( 100 );
pNtk->vBoxes = Vec_PtrAlloc( 100 );
pNtk->vSkews = Vec_FltAlloc( 100 );
// start the memory managers
pNtk->pMmObj = fUseMemMan? Extra_MmFixedStart( sizeof(Abc_Obj_t) ) : NULL;
pNtk->pMmStep = fUseMemMan? Extra_MmStepStart( ABC_NUM_STEPS ) : NULL;
@ -76,13 +74,15 @@ Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan
else if ( Abc_NtkHasBdd(pNtk) )
pNtk->pManFunc = Cudd_Init( 20, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
else if ( Abc_NtkHasAig(pNtk) )
pNtk->pManFunc = Aig_ManStart();
pNtk->pManFunc = Hop_ManStart();
else if ( Abc_NtkHasMapping(pNtk) )
pNtk->pManFunc = Abc_FrameReadLibGen();
else if ( !Abc_NtkHasBlackbox(pNtk) )
assert( 0 );
// name manager
pNtk->pManName = Nm_ManCreate( 200 );
// attribute manager
pNtk->vAttrs = Vec_PtrStart( VEC_ATTR_TOTAL_NUM );
return pNtk;
}
@ -301,40 +301,6 @@ Abc_Ntk_t * Abc_NtkDup( Abc_Ntk_t * pNtk )
printf( "Warning: Structural hashing during duplication reduced %d nodes (this is a minor bug).\n",
Abc_NtkNodeNum(pNtk) - Abc_NtkNodeNum(pNtkNew) );
}
/*
else if ( Abc_NtkIsSeq(pNtk) )
{
// start the storage for initial states
Seq_Resize( pNtkNew->pManFunc, Abc_NtkObjNumMax(pNtk) );
// copy the nodes
Abc_NtkForEachObj( pNtk, pObj, i )
if ( pObj->pCopy == NULL )
{
Abc_NtkDupObj(pNtkNew, pObj, 0);
pObj->pCopy->Level = pObj->Level;
pObj->pCopy->fPhase = pObj->fPhase;
}
// connect the nodes
Abc_NtkForEachObj( pNtk, pObj, i )
{
Abc_ObjForEachFanin( pObj, pFanin, k )
{
Abc_ObjAddFanin( pObj->pCopy, pFanin->pCopy );
if ( Abc_ObjFaninC(pObj, k) )
Abc_ObjSetFaninC( pObj->pCopy, k );
if ( Seq_ObjFaninL(pObj, k) )
Seq_NodeDupLats( pObj->pCopy, pObj, k );
}
}
// relink the choice nodes
Abc_AigForEachAnd( pNtk, pObj, i )
if ( pObj->pData )
pObj->pCopy->pData = ((Abc_Obj_t *)pObj->pData)->pCopy;
// copy the cutset
Abc_SeqForEachCutsetNode( pNtk, pObj, i )
Vec_PtrPush( pNtkNew->vCutSet, pObj->pCopy );
}
*/
else
{
// duplicate the nets and nodes (CIs/COs/latches already dupped)
@ -795,6 +761,7 @@ Abc_Ntk_t * Abc_NtkCreateWithNode( char * pSop )
void Abc_NtkDelete( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj;
void * pAttrMan;
int TotalMemory, i;
int LargePiece = (4 << ABC_NUM_STEPS);
if ( pNtk == NULL )
@ -845,9 +812,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
Vec_PtrFree( pNtk->vCos );
Vec_PtrFree( pNtk->vAsserts );
Vec_PtrFree( pNtk->vObjs );
Vec_PtrFree( pNtk->vCutSet );
Vec_PtrFree( pNtk->vBoxes );
Vec_FltFree( pNtk->vSkews );
if ( pNtk->vLevelsR ) Vec_IntFree( pNtk->vLevelsR );
if ( pNtk->pModel ) free( pNtk->pModel );
TotalMemory = 0;
@ -874,7 +839,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
else if ( Abc_NtkHasBdd(pNtk) )
Extra_StopManager( pNtk->pManFunc );
else if ( Abc_NtkHasAig(pNtk) )
{ if ( pNtk->pManFunc ) Aig_ManStop( pNtk->pManFunc ); }
{ if ( pNtk->pManFunc ) Hop_ManStop( pNtk->pManFunc ); }
else if ( Abc_NtkHasMapping(pNtk) )
pNtk->pManFunc = NULL;
else if ( !Abc_NtkHasBlackbox(pNtk) )
@ -891,6 +856,11 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
}
if ( pNtk->pBlackBoxes )
Vec_IntFree( pNtk->pBlackBoxes );
// free node attributes
Vec_PtrForEachEntry( pNtk->vAttrs, pAttrMan, i )
if ( pAttrMan )
Vec_AttFree( pAttrMan, 1 );
Vec_PtrFree( pNtk->vAttrs );
free( pNtk );
}

30
src/base/abc/abcObj.c
View File

@ -299,7 +299,7 @@ void Abc_NtkDeleteAll_rec( Abc_Obj_t * pObj )
Abc_NodeCollectFanins( pObj, vNodes );
Abc_NtkDeleteObj( pObj );
Vec_PtrForEachEntry( vNodes, pObj, i )
if ( Abc_ObjFanoutNum(pObj) == 0 )
if ( !Abc_ObjIsNode(pObj) && Abc_ObjFanoutNum(pObj) == 0 )
Abc_NtkDeleteAll_rec( pObj );
Vec_PtrFree( vNodes );
}
@ -342,7 +342,7 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName
else if ( Abc_NtkHasBdd(pNtkNew) )
pObjNew->pData = Cudd_bddTransfer(pObj->pNtk->pManFunc, pNtkNew->pManFunc, pObj->pData), Cudd_Ref(pObjNew->pData);
else if ( Abc_NtkHasAig(pNtkNew) )
pObjNew->pData = Aig_Transfer(pObj->pNtk->pManFunc, pNtkNew->pManFunc, pObj->pData, Abc_ObjFaninNum(pObj));
pObjNew->pData = Hop_Transfer(pObj->pNtk->pManFunc, pNtkNew->pManFunc, pObj->pData, Abc_ObjFaninNum(pObj));
else if ( Abc_NtkHasMapping(pNtkNew) )
pObjNew->pData = pObj->pData;
else assert( 0 );
@ -576,7 +576,7 @@ Abc_Obj_t * Abc_NtkCreateNodeConst0( Abc_Ntk_t * pNtk )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Cudd_ReadLogicZero(pNtk->pManFunc), Cudd_Ref( pNode->pData );
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_ManConst0(pNtk->pManFunc);
pNode->pData = Hop_ManConst0(pNtk->pManFunc);
else if ( Abc_NtkHasMapping(pNtk) )
pNode->pData = Mio_LibraryReadConst0(Abc_FrameReadLibGen());
else if ( !Abc_NtkHasBlackbox(pNtk) )
@ -605,7 +605,7 @@ Abc_Obj_t * Abc_NtkCreateNodeConst1( Abc_Ntk_t * pNtk )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Cudd_ReadOne(pNtk->pManFunc), Cudd_Ref( pNode->pData );
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_ManConst1(pNtk->pManFunc);
pNode->pData = Hop_ManConst1(pNtk->pManFunc);
else if ( Abc_NtkHasMapping(pNtk) )
pNode->pData = Mio_LibraryReadConst1(Abc_FrameReadLibGen());
else if ( !Abc_NtkHasBlackbox(pNtk) )
@ -635,7 +635,7 @@ Abc_Obj_t * Abc_NtkCreateNodeInv( Abc_Ntk_t * pNtk, Abc_Obj_t * pFanin )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Cudd_Not(Cudd_bddIthVar(pNtk->pManFunc,0)), Cudd_Ref( pNode->pData );
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_Not(Aig_IthVar(pNtk->pManFunc,0));
pNode->pData = Hop_Not(Hop_IthVar(pNtk->pManFunc,0));
else if ( Abc_NtkHasMapping(pNtk) )
pNode->pData = Mio_LibraryReadInv(Abc_FrameReadLibGen());
else
@ -665,7 +665,7 @@ Abc_Obj_t * Abc_NtkCreateNodeBuf( Abc_Ntk_t * pNtk, Abc_Obj_t * pFanin )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Cudd_bddIthVar(pNtk->pManFunc,0), Cudd_Ref( pNode->pData );
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_IthVar(pNtk->pManFunc,0);
pNode->pData = Hop_IthVar(pNtk->pManFunc,0);
else if ( Abc_NtkHasMapping(pNtk) )
pNode->pData = Mio_LibraryReadBuf(Abc_FrameReadLibGen());
else
@ -697,7 +697,7 @@ Abc_Obj_t * Abc_NtkCreateNodeAnd( Abc_Ntk_t * pNtk, Vec_Ptr_t * vFanins )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Extra_bddCreateAnd( pNtk->pManFunc, Vec_PtrSize(vFanins) ), Cudd_Ref(pNode->pData);
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_CreateAnd( pNtk->pManFunc, Vec_PtrSize(vFanins) );
pNode->pData = Hop_CreateAnd( pNtk->pManFunc, Vec_PtrSize(vFanins) );
else
assert( 0 );
return pNode;
@ -727,7 +727,7 @@ Abc_Obj_t * Abc_NtkCreateNodeOr( Abc_Ntk_t * pNtk, Vec_Ptr_t * vFanins )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Extra_bddCreateOr( pNtk->pManFunc, Vec_PtrSize(vFanins) ), Cudd_Ref(pNode->pData);
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_CreateOr( pNtk->pManFunc, Vec_PtrSize(vFanins) );
pNode->pData = Hop_CreateOr( pNtk->pManFunc, Vec_PtrSize(vFanins) );
else
assert( 0 );
return pNode;
@ -757,7 +757,7 @@ Abc_Obj_t * Abc_NtkCreateNodeExor( Abc_Ntk_t * pNtk, Vec_Ptr_t * vFanins )
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Extra_bddCreateExor( pNtk->pManFunc, Vec_PtrSize(vFanins) ), Cudd_Ref(pNode->pData);
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_CreateExor( pNtk->pManFunc, Vec_PtrSize(vFanins) );
pNode->pData = Hop_CreateExor( pNtk->pManFunc, Vec_PtrSize(vFanins) );
else
assert( 0 );
return pNode;
@ -787,7 +787,7 @@ Abc_Obj_t * Abc_NtkCreateNodeMux( Abc_Ntk_t * pNtk, Abc_Obj_t * pNodeC, Abc_Obj_
else if ( Abc_NtkHasBdd(pNtk) )
pNode->pData = Cudd_bddIte(pNtk->pManFunc,Cudd_bddIthVar(pNtk->pManFunc,0),Cudd_bddIthVar(pNtk->pManFunc,1),Cudd_bddIthVar(pNtk->pManFunc,2)), Cudd_Ref( pNode->pData );
else if ( Abc_NtkHasAig(pNtk) )
pNode->pData = Aig_Mux(pNtk->pManFunc,Aig_IthVar(pNtk->pManFunc,0),Aig_IthVar(pNtk->pManFunc,1),Aig_IthVar(pNtk->pManFunc,2));
pNode->pData = Hop_Mux(pNtk->pManFunc,Hop_IthVar(pNtk->pManFunc,0),Hop_IthVar(pNtk->pManFunc,1),Hop_IthVar(pNtk->pManFunc,2));
else
assert( 0 );
return pNode;
@ -834,7 +834,7 @@ bool Abc_NodeIsConst0( Abc_Obj_t * pNode )
if ( Abc_NtkHasBdd(pNtk) )
return Cudd_IsComplement(pNode->pData);
if ( Abc_NtkHasAig(pNtk) )
return Aig_IsComplement(pNode->pData);
return Hop_IsComplement(pNode->pData);
if ( Abc_NtkHasMapping(pNtk) )
return pNode->pData == Mio_LibraryReadConst0(Abc_FrameReadLibGen());
assert( 0 );
@ -864,7 +864,7 @@ bool Abc_NodeIsConst1( Abc_Obj_t * pNode )
if ( Abc_NtkHasBdd(pNtk) )
return !Cudd_IsComplement(pNode->pData);
if ( Abc_NtkHasAig(pNtk) )
return !Aig_IsComplement(pNode->pData);
return !Hop_IsComplement(pNode->pData);
if ( Abc_NtkHasMapping(pNtk) )
return pNode->pData == Mio_LibraryReadConst1(Abc_FrameReadLibGen());
assert( 0 );
@ -894,7 +894,7 @@ bool Abc_NodeIsBuf( Abc_Obj_t * pNode )
if ( Abc_NtkHasBdd(pNtk) )
return !Cudd_IsComplement(pNode->pData);
if ( Abc_NtkHasAig(pNtk) )
return !Aig_IsComplement(pNode->pData);
return !Hop_IsComplement(pNode->pData);
if ( Abc_NtkHasMapping(pNtk) )
return pNode->pData == Mio_LibraryReadBuf(Abc_FrameReadLibGen());
assert( 0 );
@ -924,7 +924,7 @@ bool Abc_NodeIsInv( Abc_Obj_t * pNode )
if ( Abc_NtkHasBdd(pNtk) )
return Cudd_IsComplement(pNode->pData);
if ( Abc_NtkHasAig(pNtk) )
return Aig_IsComplement(pNode->pData);
return Hop_IsComplement(pNode->pData);
if ( Abc_NtkHasMapping(pNtk) )
return pNode->pData == Mio_LibraryReadInv(Abc_FrameReadLibGen());
assert( 0 );
@ -951,7 +951,7 @@ void Abc_NodeComplement( Abc_Obj_t * pNode )
else if ( Abc_NtkHasBdd(pNode->pNtk) )
pNode->pData = Cudd_Not( pNode->pData );
else if ( Abc_NtkHasAig(pNode->pNtk) )
pNode->pData = Aig_Not( pNode->pData );
pNode->pData = Hop_Not( pNode->pData );
else
assert( 0 );
}

126
src/base/abc/abcShow.c
View File

@ -77,109 +77,6 @@ void Abc_NodeShowBdd( Abc_Obj_t * pNode )
Abc_ShowFile( FileNameDot );
}
/**Function*************************************************************
Synopsis [Visualizes AIG with choices.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkShowAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodesShow )
{
FILE * pFile;
Abc_Obj_t * pNode;
Vec_Ptr_t * vNodes;
char FileNameDot[200];
int i;
assert( Abc_NtkIsStrash(pNtk) );
// create the file name
Abc_ShowGetFileName( pNtk->pName, FileNameDot );
// check that the file can be opened
if ( (pFile = fopen( FileNameDot, "w" )) == NULL )
{
fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", FileNameDot );
return;
}
fclose( pFile );
// collect all nodes in the network
vNodes = Vec_PtrAlloc( 100 );
Abc_NtkForEachObj( pNtk, pNode, i )
Vec_PtrPush( vNodes, pNode );
// write the DOT file
Io_WriteDotAig( pNtk, vNodes, vNodesShow, FileNameDot, 0 );
Vec_PtrFree( vNodes );
// visualize the file
Abc_ShowFile( FileNameDot );
}
/**Function*************************************************************
Synopsis [Visualizes AIG with choices.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkShowMulti( Abc_Ntk_t * pNtk )
{
FILE * pFile;
Abc_Obj_t * pNode;
Vec_Ptr_t * vNodes;
char FileNameDot[200];
int i;
extern void Abc_NtkBalanceAttach( Abc_Ntk_t * pNtk );
extern void Abc_NtkBalanceDetach( Abc_Ntk_t * pNtk );
extern void Abc_NtkBalanceLevel( Abc_Ntk_t * pNtk );
assert( Abc_NtkIsStrash(pNtk) );
// create the file name
Abc_ShowGetFileName( pNtk->pName, FileNameDot );
// check that the file can be opened
if ( (pFile = fopen( FileNameDot, "w" )) == NULL )
{
fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", FileNameDot );
return;
}
fclose( pFile );
// get the implication supergates
Abc_NtkBalanceAttach( pNtk );
// set the levels based on the implication supergates
Abc_NtkBalanceLevel( pNtk );
// collect all nodes that are roots
vNodes = Vec_PtrAlloc( 100 );
Abc_NtkForEachCi( pNtk, pNode, i )
Vec_PtrPush( vNodes, pNode );
Abc_NtkForEachNode( pNtk, pNode, i )
if ( pNode->pCopy || Abc_ObjFaninNum(pNode) == 0 )
Vec_PtrPush( vNodes, pNode );
Abc_NtkForEachPo( pNtk, pNode, i )
Vec_PtrPush( vNodes, pNode );
// write the DOT file
Io_WriteDotAig( pNtk, vNodes, NULL, FileNameDot, 1 );
Vec_PtrFree( vNodes );
// undo the supergates
Abc_NtkBalanceDetach( pNtk );
// set the normal levels
Abc_NtkGetLevelNum( pNtk );
// visualize the file
Abc_ShowFile( FileNameDot );
}
/**Function*************************************************************
Synopsis [Visualizes a reconvergence driven cut at the node.]
@ -232,7 +129,7 @@ void Abc_NodeShowCut( Abc_Obj_t * pNode, int nNodeSizeMax, int nConeSizeMax )
// add the root node to the cone (for visualization)
Vec_PtrPush( vCutSmall, pNode );
// write the DOT file
Io_WriteDotAig( pNode->pNtk, vInside, vCutSmall, FileNameDot, 0 );
Io_WriteDotNtk( pNode->pNtk, vInside, vCutSmall, FileNameDot, 0, 0 );
// stop the cut computation manager
Abc_NtkManCutStop( p );
@ -251,7 +148,7 @@ void Abc_NodeShowCut( Abc_Obj_t * pNode, int nNodeSizeMax, int nConeSizeMax )
SeeAlso []
***********************************************************************/
void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames )
void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames, int fSeq, int fUseReverse )
{
FILE * pFile;
Abc_Obj_t * pNode;
@ -259,8 +156,15 @@ void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames )
char FileNameDot[200];
int i;
assert( !Abc_NtkIsStrash(pNtk) );
Abc_NtkLogicToSop( pNtk, 0 );
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( Abc_NtkIsStrash(pNtk) && Abc_NtkGetChoiceNum(pNtk) )
{
printf( "Temporarily visualization of AIGs with choice nodes is disabled.\n" );
return;
}
// convert to logic SOP
if ( Abc_NtkIsLogic(pNtk) )
Abc_NtkLogicToSop( pNtk, 0 );
// create the file name
Abc_ShowGetFileName( pNtk->pName, FileNameDot );
// check that the file can be opened
@ -274,10 +178,12 @@ void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames )
// collect all nodes in the network
vNodes = Vec_PtrAlloc( 100 );
Abc_NtkForEachObj( pNtk, pNode, i )
// if ( !Abc_ObjIsBi(pNode) && !Abc_ObjIsBo(pNode) )
Vec_PtrPush( vNodes, pNode );
Vec_PtrPush( vNodes, pNode );
// write the DOT file
Io_WriteDotNtk( pNtk, vNodes, NULL, FileNameDot, fGateNames );
if ( fSeq )
Io_WriteDotSeq( pNtk, vNodes, NULL, FileNameDot, fGateNames, fUseReverse );
else
Io_WriteDotNtk( pNtk, vNodes, NULL, FileNameDot, fGateNames, fUseReverse );
Vec_PtrFree( vNodes );
// visualize the file

5
src/base/abc/abcSop.c
View File

@ -768,7 +768,8 @@ bool Abc_SopCheck( char * pSop, int nFanins )
// compare the distance
if ( pCubes - pCubesOld != nFanins )
{
fprintf( stdout, "Abc_SopCheck: SOP has a mismatch between its cover and its fanins.\n" );
fprintf( stdout, "Abc_SopCheck: SOP has a mismatch between its cover size (%d) and its fanin number (%d).\n",
pCubes - pCubesOld, nFanins );
return 0;
}
// check the output values for this cube
@ -779,7 +780,7 @@ bool Abc_SopCheck( char * pSop, int nFanins )
fFound1 = 1;
else if ( *pCubes != 'x' && *pCubes != 'n' )
{
fprintf( stdout, "Abc_SopCheck: SOP has a strange character in the output part of its cube.\n" );
fprintf( stdout, "Abc_SopCheck: SOP has a strange character (%c) in the output part of its cube.\n", *pCubes );
return 0;
}
// check the last symbol (new line)

29
src/base/abc/abcUtil.c
View File

@ -32,6 +32,27 @@
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Frees one attribute manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void * Abc_NtkAttrFree( Abc_Ntk_t * pNtk, int Attr, int fFreeMan )
{
void * pUserMan;
Vec_Att_t * pAttrMan;
pAttrMan = Vec_PtrEntry( pNtk->vAttrs, Attr );
Vec_PtrWriteEntry( pNtk->vAttrs, Attr, NULL );
pUserMan = Vec_AttFree( pAttrMan, fFreeMan );
return pUserMan;
}
/**Function*************************************************************
Synopsis [Increments the current traversal ID of the network.]
@ -225,7 +246,7 @@ int Abc_NtkGetAigNodeNum( Abc_Ntk_t * pNtk )
assert( pNode->pData );
if ( Abc_NodeIsConst(pNode) )
continue;
nNodes += pNode->pData? Aig_DagSize( pNode->pData ) : 0;
nNodes += pNode->pData? Hop_DagSize( pNode->pData ) : 0;
}
return nNodes;
}
@ -356,7 +377,7 @@ int Abc_NtkGetChoiceNum( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, Counter;
if ( !Abc_NtkHasAig(pNtk) )
if ( !Abc_NtkIsStrash(pNtk) )
return 0;
Counter = 0;
Abc_NtkForEachNode( pNtk, pNode, i )
@ -578,7 +599,7 @@ void Abc_NtkFixCoDriverProblem( Abc_Obj_t * pDriver, Abc_Obj_t * pNodeCo, int fD
Description [The COs of a logic network are simple under three conditions:
(1) The edge from CO to its driver is not complemented.
(2) If CI is a driver of a CO, they have the same name.]
(2) If two COs share the same driver, they have the same name.]
(3) If two COs share the same driver, they have the same name.]
SideEffects []
@ -621,7 +642,7 @@ bool Abc_NtkLogicHasSimpleCos( Abc_Ntk_t * pNtk )
Description [The COs of a logic network are simple under three conditions:
(1) The edge from CO to its driver is not complemented.
(2) If CI is a driver of a CO, they have the same name.]
(2) If two COs share the same driver, they have the same name.
(3) If two COs share the same driver, they have the same name.
In some cases, such as FPGA mapping, we prevent the increase in delay
by duplicating the driver nodes, rather than adding invs/bufs.]

556
src/base/abci/abc.c
View File

@ -22,10 +22,9 @@
#include "mainInt.h"
#include "fraig.h"
#include "fxu.h"
#include "fpga.h"
#include "pga.h"
#include "cut.h"
//#include "seq.h"
#include "fpga.h"
#include "if.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
@ -46,12 +45,10 @@ static int Abc_CommandPrintAuto ( Abc_Frame_t * pAbc, int argc, char ** arg
static int Abc_CommandPrintKMap ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintGates ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintSharing ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPrintSkews ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShow ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShowBdd ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShowCut ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShowAig ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandShowNtk ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandCollapse ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandStrash ( Abc_Frame_t * pAbc, int argc, char ** argv );
@ -123,7 +120,7 @@ static int Abc_CommandSuperChoiceLut ( Abc_Frame_t * pAbc, int argc, char ** arg
static int Abc_CommandFpga ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandFpgaFast ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandPga ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandIf ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandScut ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandInit ( Abc_Frame_t * pAbc, int argc, char ** argv );
@ -145,9 +142,6 @@ static int Abc_CommandDebug ( Abc_Frame_t * pAbc, int argc, char ** arg
static int Abc_CommandTraceStart ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandTraceCheck ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandHoward ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandSkewForward ( Abc_Frame_t * pAbc, int argc, char ** argv );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
@ -182,12 +176,10 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "Printing", "print_kmap", Abc_CommandPrintKMap, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_gates", Abc_CommandPrintGates, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_sharing", Abc_CommandPrintSharing, 0 );
Cmd_CommandAdd( pAbc, "Printing", "print_skews", Abc_CommandPrintSkews, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show", Abc_CommandShow, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show_bdd", Abc_CommandShowBdd, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show_cut", Abc_CommandShowCut, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show_aig", Abc_CommandShowAig, 0 );
Cmd_CommandAdd( pAbc, "Printing", "show_ntk", Abc_CommandShowNtk, 0 );
Cmd_CommandAdd( pAbc, "Synthesis", "collapse", Abc_CommandCollapse, 1 );
Cmd_CommandAdd( pAbc, "Synthesis", "strash", Abc_CommandStrash, 1 );
@ -259,7 +251,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "FPGA mapping", "fpga", Abc_CommandFpga, 1 );
Cmd_CommandAdd( pAbc, "FPGA mapping", "ffpga", Abc_CommandFpgaFast, 1 );
Cmd_CommandAdd( pAbc, "FPGA mapping", "pga", Abc_CommandPga, 1 );
Cmd_CommandAdd( pAbc, "FPGA mapping", "if", Abc_CommandIf, 1 );
// Cmd_CommandAdd( pAbc, "Sequential", "scut", Abc_CommandScut, 0 );
Cmd_CommandAdd( pAbc, "Sequential", "init", Abc_CommandInit, 1 );
@ -281,9 +273,6 @@ void Abc_Init( Abc_Frame_t * pAbc )
// Cmd_CommandAdd( pAbc, "Verification", "trace_start", Abc_CommandTraceStart, 0 );
// Cmd_CommandAdd( pAbc, "Verification", "trace_check", Abc_CommandTraceCheck, 0 );
// Cmd_CommandAdd( pAbc, "Sequential", "howard", Abc_CommandHoward, 0 );
// Cmd_CommandAdd( pAbc, "Sequential", "skew_fwd", Abc_CommandSkewForward, 0 );
// Rwt_Man4ExploreStart();
// Map_Var3Print();
// Map_Var4Test();
@ -1383,29 +1372,38 @@ usage:
SeeAlso []
***********************************************************************/
int Abc_CommandPrintSkews( Abc_Frame_t * pAbc, int argc, char ** argv )
int Abc_CommandShow( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fPrintAll;
int fSeq;
int fGateNames;
int fUseReverse;
extern void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames, int fSeq, int fUseReverse );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fPrintAll = 0;
fSeq = 0;
fGateNames = 0;
fUseReverse = 1;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "ah" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "rsgh" ) ) != EOF )
{
switch ( c )
{
case 'a':
fPrintAll = 1;
case 'r':
fUseReverse ^= 1;
break;
case 's':
fSeq ^= 1;
break;
case 'g':
fGateNames ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
@ -1417,25 +1415,19 @@ int Abc_CommandPrintSkews( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1;
}
if ( !Abc_NtkIsSeq(pNtk) && Abc_NtkLatchNum(pNtk) == 0 )
{
fprintf( pErr, "The network has no latches.\n" );
return 0;
}
if ( pNtk->vSkews == NULL || pNtk->vSkews->nSize == 0 )
{
fprintf( pErr, "The network has no clock skew schedule.\n" );
return 0;
}
Abc_NtkPrintSkews( pOut, pNtk, fPrintAll );
Abc_NtkShow( pNtk, fGateNames, fSeq, fUseReverse );
return 0;
usage:
fprintf( pErr, "usage: print_skews [-h] [-a]\n" );
fprintf( pErr, "\t prints information about a clock skew schedule\n" );
fprintf( pErr, "\t-a : dumps the skew of every latch [default = no]\n");
fprintf( pErr, "usage: show [-srgh]\n" );
fprintf( pErr, " visualizes the network structure using DOT and GSVIEW\n" );
#ifdef WIN32
fprintf( pErr, " \"dot.exe\" and \"gsview32.exe\" should be set in the paths\n" );
fprintf( pErr, " (\"gsview32.exe\" may be in \"C:\\Program Files\\Ghostgum\\gsview\\\")\n" );
#endif
fprintf( pErr, "\t-s : toggles visualization of sequential networks [default = %s].\n", fSeq? "yes": "no" );
fprintf( pErr, "\t-r : toggles ordering nodes in reverse order [default = %s].\n", fUseReverse? "yes": "no" );
fprintf( pErr, "\t-g : toggles printing gate names for mapped network [default = %s].\n", fGateNames? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
@ -1628,145 +1620,6 @@ usage:
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandShowAig( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fMulti;
extern void Abc_NtkShowAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodesShow );
extern void Abc_NtkShowMulti( Abc_Ntk_t * pNtk );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fMulti = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "mh" ) ) != EOF )
{
switch ( c )
{
case 'm':
fMulti ^= 1;
break;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( pErr, "Visualizing networks other than AIGs can be done using command \"show_ntk\".\n" );
return 1;
}
if ( fMulti && !Abc_NtkIsStrash(pNtk) )
{
fprintf( pErr, "Visualizing multi-input ANDs cannot be done for sequential network (run \"unseq\").\n" );
return 1;
}
if ( !fMulti )
Abc_NtkShowAig( pNtk, NULL );
else
Abc_NtkShowMulti( pNtk );
return 0;
usage:
fprintf( pErr, "usage: show_aig [-h]\n" );
fprintf( pErr, " visualizes the AIG with choices using DOT and GSVIEW\n" );
#ifdef WIN32
fprintf( pErr, " \"dot.exe\" and \"gsview32.exe\" should be set in the paths\n" );
fprintf( pErr, " (\"gsview32.exe\" may be in \"C:\\Program Files\\Ghostgum\\gsview\\\")\n" );
#endif
fprintf( pErr, "\t-m : toggles visualization of multi-input ANDs [default = %s].\n", fMulti? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandShowNtk( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fGateNames;
extern void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fGateNames = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "gh" ) ) != EOF )
{
switch ( c )
{
case 'g':
fGateNames ^= 1;
break;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( Abc_NtkIsStrash(pNtk) )
{
fprintf( pErr, "Visualizing AIG can only be done using command \"show_aig\".\n" );
return 1;
}
Abc_NtkShow( pNtk, fGateNames );
return 0;
usage:
fprintf( pErr, "usage: show_ntk [-gh]\n" );
fprintf( pErr, " visualizes the network structure using DOT and GSVIEW\n" );
#ifdef WIN32
fprintf( pErr, " \"dot.exe\" and \"gsview32.exe\" should be set in the paths\n" );
fprintf( pErr, " (\"gsview32.exe\" may be in \"C:\\Program Files\\Ghostgum\\gsview\\\")\n" );
#endif
fprintf( pErr, "\t-g : toggles printing gate names for mapped network [default = %s].\n", fGateNames? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
@ -5136,8 +4989,8 @@ int Abc_CommandCycle( Abc_Frame_t * pAbc, int argc, char ** argv )
pErr = Abc_FrameReadErr(pAbc);
// set defaults
nFrames = 50;
fVerbose = 0;
nFrames = 100;
fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "Fvh" ) ) != EOF )
{
@ -5633,7 +5486,7 @@ int Abc_CommandIRewriteSeq( Abc_Frame_t * pAbc, int argc, char ** argv )
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fUpdateLevel = 1;
fUpdateLevel = 0;
fUseZeroCost = 0;
fVerbose = 0;
Extra_UtilGetoptReset();
@ -7343,7 +7196,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
usage:
if ( DelayTarget == -1 )
sprintf( Buffer, "not used" );
sprintf( Buffer, "best possible" );
else
sprintf( Buffer, "%.2f", DelayTarget );
if ( nLutSize == -1 )
@ -7394,7 +7247,7 @@ int Abc_CommandFpgaFast( Abc_Frame_t * pAbc, int argc, char ** argv )
fRecovery = 1;
fVerbose = 0;
DelayTarget =-1;
nLutSize = 8;
nLutSize = 5;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "avhDK" ) ) != EOF )
{
@ -7514,46 +7367,90 @@ usage:
SeeAlso []
***********************************************************************/
int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
{
char Buffer[100];
char LutSize[100];
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk, * pNtkRes;
Pga_Params_t Params, * pParams = &Params;
If_Par_t Pars, * pPars = &Pars;
int c;
extern Abc_Ntk_t * Abc_NtkPga( Pga_Params_t * pParams );
extern Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
memset( pParams, 0, sizeof(Pga_Params_t) );
pParams->pNtk = pNtk;
pParams->pLutLib = Abc_FrameReadLibLut();
pParams->fAreaFlow = 1;
pParams->fArea = 1;
pParams->fSwitching = 0;
pParams->fDropCuts = 0;
pParams->fVerbose = 0;
memset( pPars, 0, sizeof(If_Par_t) );
pPars->Mode = 1;
pPars->nLutSize = 4;
// pPars->pLutLib = Abc_FrameReadLibLut();
pPars->nCutsMax = 2;
pPars->fSeq = 0;
pPars->fLatchPaths = 0;
pPars->nLatches = 0;
pPars->pTimesArr = Abc_NtkGetCiArrivalFloats(pNtk);
pPars->pTimesReq = NULL;
pPars->DelayTarget = -1;
pPars->fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "fapdvh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "MKCDlsvh" ) ) != EOF )
{
switch ( c )
{
case 'f':
pParams->fAreaFlow ^= 1;
case 'M':
if ( globalUtilOptind >= argc )
{
fprintf( pErr, "Command line switch \"-M\" should be followed by a positive integer.\n" );
goto usage;
}
pPars->Mode = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
if ( pPars->Mode < 0 )
goto usage;
break;
case 'a':
pParams->fArea ^= 1;
case 'K':
if ( globalUtilOptind >= argc )
{
fprintf( pErr, "Command line switch \"-K\" should be followed by a positive integer.\n" );
goto usage;
}
pPars->nLutSize = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
if ( pPars->nLutSize < 0 )
goto usage;
break;
case 'p':
pParams->fSwitching ^= 1;
case 'C':
if ( globalUtilOptind >= argc )
{
fprintf( pErr, "Command line switch \"-C\" should be followed by a positive integer.\n" );
goto usage;
}
pPars->nCutsMax = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
if ( pPars->nCutsMax < 0 )
goto usage;
break;
case 'd':
pParams->fDropCuts ^= 1;
case 'D':
if ( globalUtilOptind >= argc )
{
fprintf( pErr, "Command line switch \"-D\" should be followed by a floating point number.\n" );
goto usage;
}
pPars->DelayTarget = (float)atof(argv[globalUtilOptind]);
globalUtilOptind++;
if ( pPars->DelayTarget <= 0.0 )
goto usage;
break;
case 'l':
pPars->fLatchPaths ^= 1;
break;
case 's':
pPars->fSeq ^= 1;
break;
case 'v':
pParams->fVerbose ^= 1;
pPars->fVerbose ^= 1;
break;
case 'h':
default:
@ -7567,8 +7464,18 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1;
}
printf( "This command is not yet implemented.\n" );
return 0;
if ( pPars->Mode < 0 || pPars->Mode > 4 )
{
fprintf( pErr, "Incorrect mapping mode.\n" );
return 1;
}
// set the latch paths
if ( pPars->fLatchPaths )
{
for ( c = 0; c < Abc_NtkPiNum(pNtk); c++ )
pPars->pTimesArr[c] = -ABC_INFINITY;
}
if ( !Abc_NtkIsStrash(pNtk) )
{
@ -7588,7 +7495,7 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
}
fprintf( pOut, "The network was strashed and balanced before FPGA mapping.\n" );
// get the new network
pNtkRes = Abc_NtkPga( pParams );
pNtkRes = Abc_NtkIf( pNtk, pPars );
if ( pNtkRes == NULL )
{
Abc_NtkDelete( pNtk );
@ -7600,7 +7507,7 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
else
{
// get the new network
pNtkRes = Abc_NtkPga( pParams );
pNtkRes = Abc_NtkIf( pNtk, pPars );
if ( pNtkRes == NULL )
{
fprintf( pErr, "FPGA mapping has failed.\n" );
@ -7612,14 +7519,28 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pErr, "usage: pga [-fapdvh]\n" );
fprintf( pErr, "\t performs FPGA mapping of the current network\n" );
fprintf( pErr, "\t-f : toggles area flow recovery [default = %s]\n", pParams->fAreaFlow? "yes": "no" );
fprintf( pErr, "\t-a : toggles area recovery [default = %s]\n", pParams->fArea? "yes": "no" );
fprintf( pErr, "\t-p : optimizes power by minimizing switching activity [default = %s]\n", pParams->fSwitching? "yes": "no" );
fprintf( pErr, "\t-d : toggles dropping cuts to save memory [default = %s]\n", pParams->fDropCuts? "yes": "no" );
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", pParams->fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : prints the command usage\n");
if ( pPars->DelayTarget == -1 )
sprintf( Buffer, "best possible" );
else
sprintf( Buffer, "%.2f", pPars->DelayTarget );
if ( pPars->nLutSize == -1 )
sprintf( LutSize, "library" );
else
sprintf( LutSize, "%d", pPars->nLutSize );
fprintf( pErr, "usage: if [-M num] [-K num] [-C num] [-D float] [-lsvh]\n" );
fprintf( pErr, "\t performs FPGA mapping of the network as follows:\n" );
fprintf( pErr, "\t 1 - delay only\n" );
fprintf( pErr, "\t 2 - area only\n" );
fprintf( pErr, "\t 3 - area under delay constraints\n" );
fprintf( pErr, "\t 4 - area under delay constraints with area recovery\n" );
fprintf( pErr, "\t-M num : the mapping mode [default = %d]\n", pPars->Mode );
fprintf( pErr, "\t-K num : the number of LUT inputs (2 < num < 32) [default = %s]\n", LutSize );
fprintf( pErr, "\t-C num : the max number of cuts to use (1 < num < 2^12) [default = %d]\n", pPars->nCutsMax );
fprintf( pErr, "\t-D float : sets the delay constraint for the mapping [default = %s]\n", Buffer );
fprintf( pErr, "\t-l : optimizes latch paths for delay, other paths for area [default = %s]\n", pPars->fLatchPaths? "yes": "no" );
fprintf( pErr, "\t-s : toggles sequential mapping [default = %s]\n", pPars->fSeq? "yes": "no" );
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", pPars->fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : prints the command usage\n");
return 1;
}
@ -7996,7 +7917,7 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
Mode = 5;
fForward = 0;
fBackward = 0;
fVerbose = 1;
fVerbose = 0;
nMaxIters = 15;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "Mfbvh" ) ) != EOF )
@ -8048,6 +7969,12 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
}
if ( Mode < 0 || Mode > 6 )
{
fprintf( pErr, "The mode (%d) is incorrect. Retiming is not performed.\n", Mode );
return 0;
}
if ( Abc_NtkIsStrash(pNtk) )
{
if ( Abc_NtkGetChoiceNum(pNtk) )
@ -8089,6 +8016,7 @@ usage:
fprintf( pErr, "\t 3: forward and backward min-area retiming\n" );
fprintf( pErr, "\t 4: forward and backward min-delay retiming\n" );
fprintf( pErr, "\t 5: mode 3 followed by mode 4\n" );
fprintf( pErr, "\t 6: Pan's optimum-delay retiming using binary search\n" );
fprintf( pErr, "\t-M num : the retiming algorithm to use [default = %d]\n", Mode );
fprintf( pErr, "\t-f : enables forward-only retiming in modes 3,4,5 [default = %s]\n", fForward? "yes": "no" );
fprintf( pErr, "\t-b : enables backward-only retiming in modes 3,4,5 [default = %s]\n", fBackward? "yes": "no" );
@ -8488,6 +8416,8 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fLatchSweep;
int fAutoSweep;
int fVerbose;
pNtk = Abc_FrameReadNtk(pAbc);
@ -8495,12 +8425,20 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fVerbose = 1;
fLatchSweep = 0;
fAutoSweep = 0;
fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "lavh" ) ) != EOF )
{
switch ( c )
{
case 'l':
fLatchSweep ^= 1;
break;
case 'a':
fAutoSweep ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
@ -8521,16 +8459,18 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1;
}
// modify the current network
Abc_NtkCleanupSeq( pNtk, fVerbose );
Abc_NtkCleanupSeq( pNtk, fLatchSweep, fAutoSweep, fVerbose );
return 0;
usage:
fprintf( pErr, "usage: scleanup [-vh]\n" );
fprintf( pErr, "usage: scleanup [-lavh]\n" );
fprintf( pErr, "\t performs sequential cleanup\n" );
fprintf( pErr, "\t - removes nodes/latches that do not feed into POs\n" );
fprintf( pErr, "\t - removes and shared latches driven by constants\n" );
fprintf( pErr, "\t - replaces autonomous logic by free PI variables\n" );
fprintf( pErr, "\t (the latter may change sequential behaviour)\n" );
fprintf( pErr, "\t-l : toggle sweeping latches [default = %s]\n", fLatchSweep? "yes": "no" );
fprintf( pErr, "\t-a : toggle removing autonomous logic [default = %s]\n", fAutoSweep? "yes": "no" );
fprintf( pErr, "\t-v : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
@ -8694,7 +8634,7 @@ int Abc_CommandSec( Abc_Frame_t * pAbc, int argc, char ** argv )
// set defaults
fSat = 0;
fVerbose = 0;
nFrames = 3;
nFrames = 5;
nSeconds = 20;
nConfLimit = 10000;
nInsLimit = 0;
@ -8758,6 +8698,12 @@ int Abc_CommandSec( Abc_Frame_t * pAbc, int argc, char ** argv )
}
}
if ( Abc_NtkLatchNum(pNtk) == 0 )
{
printf( "The network has no latches. Used combinational command \"cec\".\n" );
return 0;
}
pArgvNew = argv + globalUtilOptind;
nArgcNew = argc - globalUtilOptind;
if ( !Abc_NtkPrepareTwoNtks( pErr, pNtk, pArgvNew, nArgcNew, &pNtk1, &pNtk2, &fDelete1, &fDelete2 ) )
@ -9290,168 +9236,6 @@ usage:
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandHoward( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fVerbose;
double result;
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
{
switch ( c )
{
case 'v':
fVerbose ^= 1;
break;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( !Abc_NtkIsSeq(pNtk) && Abc_NtkLatchNum(pNtk) == 0 )
{
fprintf( pErr, "The network has no latches. Analysis is not performed.\n" );
return 0;
}
if ( Abc_NtkHasAig(pNtk) )
{
// quit if there are choice nodes
if ( Abc_NtkGetChoiceNum(pNtk) )
{
fprintf( pErr, "Currently cannot analyze networks with choice nodes.\n" );
return 0;
}
/*
if ( Abc_NtkIsStrash(pNtk) )
pNtkRes = Abc_NtkAigToSeq(pNtk);
else
pNtkRes = Abc_NtkDup(pNtk);
*/
fprintf( pErr, "Currently cannot analyze unmapped networks.\n" );
return 0;
}
// result = Seq_NtkHoward( pNtk, fVerbose );
result = 0;
if (result < 0) {
fprintf( pErr, "Analysis failed.\n" );
return 0;
}
printf("Maximum mean cycle time = %.2f\n", result);
return 1;
usage:
fprintf( pErr, "usage: howard [-h]\n" );
fprintf( pErr, "\t computes the maximum mean cycle time using Howard's algorithm\n" );
fprintf( pErr, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_CommandSkewForward( Abc_Frame_t * pAbc, int argc, char ** argv )
{
FILE * pOut, * pErr;
Abc_Ntk_t * pNtk;
int c;
int fMinimize;
float target;
pNtk = Abc_FrameReadNtk(pAbc);
pOut = Abc_FrameReadOut(pAbc);
pErr = Abc_FrameReadErr(pAbc);
// set defaults
target = pNtk->maxMeanCycle;
fMinimize = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "mh" ) ) != EOF )
{
switch ( c )
{
case 'm':
fMinimize ^= 1;
break;
default:
goto usage;
}
}
if ( pNtk == NULL )
{
fprintf( pErr, "Empty network.\n" );
return 1;
}
if ( !Abc_NtkIsSeq(pNtk) && Abc_NtkLatchNum(pNtk) == 0 )
{
fprintf( pErr, "The network has no latches.\n" );
return 0;
}
if ( pNtk->vSkews == NULL || pNtk->vSkews->nSize == 0 )
{
fprintf( pErr, "The network has no clock skew schedule.\n" );
return 0;
}
// Seq_NtkSkewForward( pNtk, target, fMinimize );
return 1;
usage:
fprintf( pErr, "usage: skew_fwd [-h] [-m] [-t float]\n" );
fprintf( pErr, "\t converts a skew schedule into a set of forward skews 0<skew<T\n" );
fprintf( pErr, "\t-m : minimizes sum of skews [default = %s]\n", fMinimize? "yes": "no" );
fprintf( pErr, "\t-t : clock period, T [default = maxMeanCycle] (unimplemented)\n");
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

22
src/base/abci/abcAuto.c
View File

@ -49,16 +49,24 @@ void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose )
char ** pInputNames; // pointers to the CI names
char ** pOutputNames; // pointers to the CO names
int nOutputs, nInputs, i;
Vec_Ptr_t * vFuncsGlob;
Abc_Obj_t * pObj;
// compute the global BDDs
if ( Abc_NtkGlobalBdds(pNtk, 10000000, 0, 1, fVerbose) == NULL )
if ( Abc_NtkBuildGlobalBdds(pNtk, 10000000, 1, 1, fVerbose) == NULL )
return;
// get information about the network
nInputs = Abc_NtkCiNum(pNtk);
nOutputs = Abc_NtkCoNum(pNtk);
dd = pNtk->pManGlob;
pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
// dd = pNtk->pManGlob;
dd = Abc_NtkGlobalBddMan( pNtk );
// complement the global functions
vFuncsGlob = Vec_PtrAlloc( Abc_NtkCoNum(pNtk) );
Abc_NtkForEachCo( pNtk, pObj, i )
Vec_PtrPush( vFuncsGlob, Abc_ObjGlobalBdd(pObj) );
pbGlobal = (DdNode **)Vec_PtrArray( vFuncsGlob );
// get the network names
pInputNames = Abc_NtkCollectCioNames( pNtk, 0 );
@ -83,12 +91,14 @@ void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose )
Abc_NtkAutoPrintOne( dd, nInputs, pbGlobal, Output, pInputNames, pOutputNames, fNaive );
// deref the PO functions
Abc_NtkFreeGlobalBdds( pNtk );
// Abc_NtkFreeGlobalBdds( pNtk );
// stop the global BDD manager
Extra_StopManager( pNtk->pManGlob );
pNtk->pManGlob = NULL;
// Extra_StopManager( pNtk->pManGlob );
// pNtk->pManGlob = NULL;
Abc_NtkFreeGlobalBdds( pNtk, 1 );
free( pInputNames );
free( pOutputNames );
Vec_PtrFree( vFuncsGlob );
}
/**Function*************************************************************

30
src/base/abci/abcClpBdd.c
View File

@ -49,25 +49,27 @@ Abc_Ntk_t * Abc_NtkCollapse( Abc_Ntk_t * pNtk, int fBddSizeMax, int fDualRail, i
assert( Abc_NtkIsStrash(pNtk) );
// compute the global BDDs
if ( Abc_NtkGlobalBdds(pNtk, fBddSizeMax, 0, fReorder, fVerbose) == NULL )
if ( Abc_NtkBuildGlobalBdds(pNtk, fBddSizeMax, 1, fReorder, fVerbose) == NULL )
return NULL;
if ( fVerbose )
{
printf( "The shared BDD size is %d nodes. ", Cudd_ReadKeys(pNtk->pManGlob) - Cudd_ReadDead(pNtk->pManGlob) );
DdManager * dd = Abc_NtkGlobalBddMan( pNtk );
printf( "The shared BDD size is %d nodes. ", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
PRT( "BDD construction time", clock() - clk );
}
// create the new network
pNtkNew = Abc_NtkFromGlobalBdds( pNtk );
Abc_NtkFreeGlobalBdds( pNtk );
// Abc_NtkFreeGlobalBdds( pNtk );
Abc_NtkFreeGlobalBdds( pNtk, 1 );
if ( pNtkNew == NULL )
{
Cudd_Quit( pNtk->pManGlob );
pNtk->pManGlob = NULL;
// Cudd_Quit( pNtk->pManGlob );
// pNtk->pManGlob = NULL;
return NULL;
}
Extra_StopManager( pNtk->pManGlob );
pNtk->pManGlob = NULL;
// Extra_StopManager( pNtk->pManGlob );
// pNtk->pManGlob = NULL;
// make the network minimum base
Abc_NtkMinimumBase( pNtkNew );
@ -100,8 +102,9 @@ Abc_Ntk_t * Abc_NtkFromGlobalBdds( Abc_Ntk_t * pNtk )
{
ProgressBar * pProgress;
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pNode, * pNodeNew;
DdManager * dd = pNtk->pManGlob;
Abc_Obj_t * pNode, * pDriver, * pNodeNew;
// DdManager * dd = pNtk->pManGlob;
DdManager * dd = Abc_NtkGlobalBddMan( pNtk );
int i;
// start the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
@ -112,7 +115,14 @@ Abc_Ntk_t * Abc_NtkFromGlobalBdds( Abc_Ntk_t * pNtk )
Abc_NtkForEachCo( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
pNodeNew = Abc_NodeFromGlobalBdds( pNtkNew, dd, Vec_PtrEntry(pNtk->vFuncsGlob, i) );
pDriver = Abc_ObjFanin0(pNode);
if ( Abc_ObjIsCi(pDriver) && !strcmp(Abc_ObjName(pNode), Abc_ObjName(pDriver)) )
{
Abc_ObjAddFanin( pNode->pCopy, pDriver->pCopy );
continue;
}
// pNodeNew = Abc_NodeFromGlobalBdds( pNtkNew, dd, Vec_PtrEntry(pNtk->vFuncsGlob, i) );
pNodeNew = Abc_NodeFromGlobalBdds( pNtkNew, dd, Abc_ObjGlobalBdd(pNode) );
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
}
Extra_ProgressBarStop( pProgress );

3
src/base/abci/abcCut.c
View File

@ -202,6 +202,7 @@ void Abc_NtkCutsOracle( Abc_Ntk_t * pNtk, Cut_Oracle_t * p )
***********************************************************************/
Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams )
{
/*
Cut_Man_t * p;
Abc_Obj_t * pObj, * pNode;
int i, nIters, fStatus;
@ -288,6 +289,8 @@ printf( "Converged after %d iterations.\n", nIters );
}
//Abc_NtkPrintCuts( p, pNtk, 1 );
return p;
*/
return NULL;
}
/**Function*************************************************************

20
src/base/abci/abcDebug.c
View File

@ -86,7 +86,8 @@ void Abc_NtkAutoDebug( Abc_Ntk_t * pNtk, int (*pFuncError) (Abc_Ntk_t *) )
else // no bug
Abc_NtkDelete( pNtkMod );
}
printf( "Iteration %6d : Nodes = %6d. Steps = %6d. Error step = %3d. ", nIter, Abc_NtkObjNum(pNtk), nSteps, i );
printf( "Iter %6d : Latches = %6d. Nodes = %6d. Steps = %6d. Error step = %3d. ",
nIter, Abc_NtkLatchNum(pNtk), Abc_NtkNodeNum(pNtk), nSteps, i );
PRT( "Time", clock() - clk );
if ( i == nSteps ) // could not modify it while preserving the bug
break;
@ -116,7 +117,11 @@ int Abc_NtkCountFaninsTotal( Abc_Ntk_t * pNtk )
Abc_NtkForEachObj( pNtk, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
{
if ( Abc_NodeIsConst(pFanin) )
if ( !Abc_ObjIsNode(pObj) && !Abc_ObjIsPo(pObj) )
continue;
if ( Abc_ObjIsPo(pObj) && Abc_NtkPoNum(pNtk) == 1 )
continue;
if ( Abc_ObjIsNode(pObj) && Abc_NodeIsConst(pFanin) )
continue;
Counter++;
}
@ -141,7 +146,11 @@ int Abc_NtkFindGivenFanin( Abc_Ntk_t * pNtk, int Step, Abc_Obj_t ** ppObj, Abc_O
Abc_NtkForEachObj( pNtk, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
{
if ( Abc_NodeIsConst(pFanin) )
if ( !Abc_ObjIsNode(pObj) && !Abc_ObjIsPo(pObj) )
continue;
if ( Abc_ObjIsPo(pObj) && Abc_NtkPoNum(pNtk) == 1 )
continue;
if ( Abc_ObjIsNode(pObj) && Abc_NodeIsConst(pFanin) )
continue;
if ( Counter++ == Step )
{
@ -166,6 +175,7 @@ int Abc_NtkFindGivenFanin( Abc_Ntk_t * pNtk, int Step, Abc_Obj_t ** ppObj, Abc_O
***********************************************************************/
Abc_Ntk_t * Abc_NtkAutoDebugModify( Abc_Ntk_t * pNtkInit, int Step, int fConst1 )
{
extern void Abc_NtkCycleInitStateSop( Abc_Ntk_t * pNtk, int nFrames, int fVerbose );
Abc_Ntk_t * pNtk;
Abc_Obj_t * pObj, * pFanin, * pConst;
// copy the network
@ -185,9 +195,9 @@ Abc_Ntk_t * Abc_NtkAutoDebugModify( Abc_Ntk_t * pNtkInit, int Step, int fConst1
Abc_NtkDeleteAll_rec( pFanin );
Abc_NtkSweep( pNtk, 0 );
Abc_NtkCleanupSeq( pNtk, 0 );
Abc_NtkCleanupSeq( pNtk, 0, 0, 0 );
Abc_NtkLogicToSop( pNtk, 0 );
Abc_NtkCycleInitStateSop( pNtk, 20, 0 );
Abc_NtkCycleInitStateSop( pNtk, 50, 0 );
return pNtk;
}

41
src/base/abci/abcDsd.c
View File

@ -55,31 +55,22 @@ static int Abc_NodeFindMuxVar( DdManager * dd, DdNode * bFunc, int n
***********************************************************************/
Abc_Ntk_t * Abc_NtkDsdGlobal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool fShort )
{
DdManager * dd;
Abc_Ntk_t * pNtkNew;
assert( Abc_NtkIsStrash(pNtk) );
// perform FPGA mapping
if ( Abc_NtkGlobalBdds(pNtk, 10000000, 0, 1, fVerbose) == NULL )
dd = Abc_NtkBuildGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );
if ( dd == NULL )
return NULL;
if ( fVerbose )
printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(pNtk->pManGlob) - Cudd_ReadDead(pNtk->pManGlob) );
printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
// transform the result of mapping into a BDD network
pNtkNew = Abc_NtkDsdInternal( pNtk, fVerbose, fPrint, fShort );
Extra_StopManager( dd );
if ( pNtkNew == NULL )
{
Cudd_Quit( pNtk->pManGlob );
pNtk->pManGlob = NULL;
return NULL;
}
Extra_StopManager( pNtk->pManGlob );
pNtk->pManGlob = NULL;
// copy EXDC network
if ( pNtk->pExdc )
pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtkNew ) )
{
printf( "Abc_NtkDsdGlobal: The network check has failed.\n" );
@ -102,26 +93,25 @@ Abc_Ntk_t * Abc_NtkDsdGlobal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool
***********************************************************************/
Abc_Ntk_t * Abc_NtkDsdInternal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool fShort )
{
DdManager * dd = pNtk->pManGlob;
char ** ppNamesCi, ** ppNamesCo;
Vec_Ptr_t * vFuncsGlob;
Dsd_Manager_t * pManDsd;
Abc_Ntk_t * pNtkNew;
DdNode * bFunc;
char ** ppNamesCi, ** ppNamesCo;
DdManager * dd;
Abc_Obj_t * pObj;
int i;
// complement the global functions
vFuncsGlob = Vec_PtrAlloc( Abc_NtkCoNum(pNtk) );
Abc_NtkForEachCo( pNtk, pObj, i )
{
bFunc = Vec_PtrEntry(pNtk->vFuncsGlob, i);
Vec_PtrWriteEntry(pNtk->vFuncsGlob, i, Cudd_NotCond(bFunc, Abc_ObjFaninC0(pObj)) );
}
Vec_PtrPush( vFuncsGlob, Cudd_NotCond(Abc_ObjGlobalBdd(pObj), Abc_ObjFaninC0(pObj)) );
// perform the decomposition
assert( Vec_PtrSize(pNtk->vFuncsGlob) == Abc_NtkCoNum(pNtk) );
dd = Abc_NtkGlobalBddMan(pNtk);
pManDsd = Dsd_ManagerStart( dd, Abc_NtkCiNum(pNtk), fVerbose );
Dsd_Decompose( pManDsd, (DdNode **)pNtk->vFuncsGlob->pArray, Abc_NtkCoNum(pNtk) );
Abc_NtkFreeGlobalBdds( pNtk );
Dsd_Decompose( pManDsd, (DdNode **)vFuncsGlob->pArray, Abc_NtkCoNum(pNtk) );
Vec_PtrFree( vFuncsGlob );
Abc_NtkFreeGlobalBdds( pNtk, 0 );
if ( pManDsd == NULL )
{
Cudd_Quit( dd );
@ -138,7 +128,6 @@ Abc_Ntk_t * Abc_NtkDsdInternal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bo
Abc_NtkFinalize( pNtk, pNtkNew );
// fix the problem with complemented and duplicated CO edges
Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 );
if ( fPrint )
{
ppNamesCi = Abc_NtkCollectCioNames( pNtk, 0 );

6
src/base/abci/abcFpgaFast.c
View File

@ -118,7 +118,7 @@ Abc_Ntk_t * Ivy_ManFpgaToAbc( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan )
// clone the node
pObj = Abc_NtkCloneObj( pObjAbc );
// set complemented functions
pObj->pData = Aig_Not( pObjAbc->pData );
pObj->pData = Hop_Not( pObjAbc->pData );
// return the new node
pObjAbc = pObj;
}
@ -172,9 +172,9 @@ Abc_Obj_t * Ivy_ManToAbcFast_rec( Abc_Ntk_t * pNtkNew, Ivy_Man_t * pMan, Ivy_Obj
Ivy_ManForEachNodeVec( pMan, vNodes, pNodeIvy, i )
{
if ( i < Vec_IntSize(vSupp) )
pNodeIvy->pEquiv = (Ivy_Obj_t *)Aig_IthVar( pNtkNew->pManFunc, i );
pNodeIvy->pEquiv = (Ivy_Obj_t *)Hop_IthVar( pNtkNew->pManFunc, i );
else
pNodeIvy->pEquiv = (Ivy_Obj_t *)Aig_And( pNtkNew->pManFunc, (Aig_Obj_t *)Ivy_ObjChild0Equiv(pNodeIvy), (Aig_Obj_t *)Ivy_ObjChild1Equiv(pNodeIvy) );
pNodeIvy->pEquiv = (Ivy_Obj_t *)Hop_And( pNtkNew->pManFunc, (Hop_Obj_t *)Ivy_ObjChild0Equiv(pNodeIvy), (Hop_Obj_t *)Ivy_ObjChild1Equiv(pNodeIvy) );
}
// set the local function
pObjAbc->pData = (Abc_Obj_t *)pObjIvy->pEquiv;

287
src/base/abci/abcIf.c Normal file
View File

@ -0,0 +1,287 @@
/**CFile****************************************************************
FileName [abcIf.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Interface with the FPGA mapping package.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - November 21, 2006.]
Revision [$Id: abcIf.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
#include "if.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
static Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk );
static Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t * pIfObj );
static Hop_Obj_t * Abc_NodeIfToHop( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Cut_t * pCut );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
{
Abc_Ntk_t * pNtkNew;
If_Man_t * pIfMan;
assert( Abc_NtkIsStrash(pNtk) );
// print a warning about choice nodes
if ( Abc_NtkGetChoiceNum( pNtk ) )
printf( "Performing FPGA mapping with choices.\n" );
// perform FPGA mapping
pIfMan = Abc_NtkToIf( pNtk, pPars );
if ( pIfMan == NULL )
return NULL;
if ( !If_ManPerformMapping( pIfMan ) )
{
If_ManStop( pIfMan );
return NULL;
}
// transform the result of mapping into a BDD network
pNtkNew = Abc_NtkFromIf( pIfMan, pNtk );
if ( pNtkNew == NULL )
return NULL;
If_ManStop( pIfMan );
// duplicate EXDC
if ( pNtk->pExdc )
pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtkNew ) )
{
printf( "Abc_NtkIf: The network check has failed.\n" );
Abc_NtkDelete( pNtkNew );
return NULL;
}
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
{
ProgressBar * pProgress;
If_Man_t * pIfMan;
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pIfMan = If_ManStart( pPars );
// create PIs and remember them in the old nodes
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)If_ManConst1( pIfMan );
Abc_NtkForEachCi( pNtk, pNode, i )
pNode->pCopy = (Abc_Obj_t *)If_ManCreatePi( pIfMan );
// load the AIG into the mapper
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
Abc_AigForEachAnd( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
// add the node to the mapper
pNode->pCopy = (Abc_Obj_t *)If_ManCreateAnd( pIfMan,
(If_Obj_t *)Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode),
(If_Obj_t *)Abc_ObjFanin1(pNode)->pCopy, Abc_ObjFaninC1(pNode) );
// set up the choice node
if ( Abc_AigNodeIsChoice( pNode ) )
for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
If_ObjSetChoice( (If_Obj_t *)pPrev->pCopy, (If_Obj_t *)pFanin->pCopy );
}
Extra_ProgressBarStop( pProgress );
// set the primary outputs without copying the phase
Abc_NtkForEachCo( pNtk, pNode, i )
If_ManCreatePo( pIfMan, (If_Obj_t *)Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) );
return pIfMan;
}
/**Function*************************************************************
Synopsis [Creates the mapped network.]
Description [Assuming the copy field of the mapped nodes are NULL.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk )
{
ProgressBar * pProgress;
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pNode, * pNodeNew;
int i, nDupGates;
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_AIG );
// prepare the mapping manager
If_ManCleanNodeCopy( pIfMan );
If_ManCleanCutData( pIfMan );
// make the mapper point to the new network
If_ObjSetCopy( If_ManConst1(pIfMan), Abc_NtkCreateNodeConst1(pNtkNew) );
Abc_NtkForEachCi( pNtk, pNode, i )
If_ObjSetCopy( If_ManPi(pIfMan, i), pNode->pCopy );
// process the nodes in topological order
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
Abc_NtkForEachCo( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
pNodeNew = Abc_NodeFromIf_rec( pNtkNew, pIfMan, If_ObjFanin0(If_ManPo(pIfMan, i)) );
pNodeNew = Abc_ObjNotCond( pNodeNew, If_ObjFaninC0(If_ManPo(pIfMan, i)) );
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
}
Extra_ProgressBarStop( pProgress );
// remove the constant node if not used
pNodeNew = (Abc_Obj_t *)If_ObjCopy( If_ManConst1(pIfMan) );
if ( Abc_ObjFanoutNum(pNodeNew) == 0 )
Abc_NtkDeleteObj( pNodeNew );
// decouple the PO driver nodes to reduce the number of levels
nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
// if ( nDupGates && If_ManReadVerbose(pIfMan) )
// printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Derive one node after FPGA mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t * pIfObj )
{
Abc_Obj_t * pNodeNew;
If_Cut_t * pCutBest;
If_Obj_t * pIfLeaf;
int i;
// return if the result if known
pNodeNew = (Abc_Obj_t *)If_ObjCopy( pIfObj );
if ( pNodeNew )
return pNodeNew;
assert( pIfObj->Type == IF_AND );
// get the parameters of the best cut
// create a new node
pNodeNew = Abc_NtkCreateNode( pNtkNew );
pCutBest = If_ObjCutBest( pIfObj );
If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, i )
Abc_ObjAddFanin( pNodeNew, Abc_NodeFromIf_rec(pNtkNew, pIfMan, pIfLeaf) );
// derive the function of this node
pNodeNew->pData = Abc_NodeIfToHop( pNtkNew->pManFunc, pIfMan, pCutBest );
If_ObjSetCopy( pIfObj, pNodeNew );
return pNodeNew;
}
/**Function*************************************************************
Synopsis [Recursively derives the truth table for the cut.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_NodeIfToHop_rec( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Cut_t * pCut, Vec_Ptr_t * vVisited )
{
Hop_Obj_t * gFunc, * gFunc0, * gFunc1;
// if the cut is visited, return the result
if ( If_CutData(pCut) )
return If_CutData(pCut);
// compute the functions of the children
gFunc0 = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pCut->pOne, vVisited );
gFunc1 = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pCut->pTwo, vVisited );
// get the function of the cut
gFunc = Hop_And( pHopMan, Hop_NotCond(gFunc0, pCut->fCompl0), Hop_NotCond(gFunc1, pCut->fCompl1) );
gFunc = Hop_NotCond( gFunc, pCut->Phase );
assert( If_CutData(pCut) == NULL );
If_CutSetData( pCut, gFunc );
// add this cut to the visited list
Vec_PtrPush( vVisited, pCut );
return gFunc;
}
/**Function*************************************************************
Synopsis [Derives the truth table for one cut.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_NodeIfToHop( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Cut_t * pCut )
{
Hop_Obj_t * gFunc;
If_Obj_t * pLeaf;
int i;
assert( pCut->nLeaves > 1 );
// set the leaf variables
If_CutForEachLeaf( pIfMan, pCut, pLeaf, i )
If_CutSetData( If_ObjCutTriv(pLeaf), Hop_IthVar(pHopMan, i) );
// recursively compute the function while collecting visited cuts
Vec_PtrClear( pIfMan->vTemp );
gFunc = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pCut, pIfMan->vTemp );
// printf( "%d ", Vec_PtrSize(p->vTemp) );
// clean the cuts
If_CutForEachLeaf( pIfMan, pCut, pLeaf, i )
If_CutSetData( If_ObjCutTriv(pLeaf), NULL );
Vec_PtrForEachEntry( pIfMan->vTemp, pCut, i )
If_CutSetData( pCut, NULL );
return gFunc;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////

21
src/base/abci/abcIvy.c
View File

@ -53,6 +53,8 @@ static inline Abc_Obj_t * Abc_ObjFanin1Ivy( Abc_Ntk_t * p, Ivy_Obj_t * pObj ) {
static Vec_Int_t * Abc_NtkCollectLatchValuesIvy( Abc_Ntk_t * pNtk, int fUseDcs );
extern int timeRetime;
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
@ -72,6 +74,7 @@ Ivy_Man_t * Abc_NtkIvyBefore( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )
{
Ivy_Man_t * pMan;
int fCleanup = 1;
//timeRetime = clock();
assert( !Abc_NtkIsNetlist(pNtk) );
assert( !Abc_NtkIsSeq(pNtk) );
if ( Abc_NtkIsBddLogic(pNtk) )
@ -107,6 +110,7 @@ Ivy_Man_t * Abc_NtkIvyBefore( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )
Vec_IntFree( vInit );
// Ivy_ManPrintStats( pMan );
}
//timeRetime = clock() - timeRetime;
return pMan;
}
@ -184,17 +188,22 @@ Abc_Ntk_t * Abc_NtkIvyHaig( Abc_Ntk_t * pNtk, int nIters, int fUseZeroCost, int
{
Abc_Ntk_t * pNtkAig;
Ivy_Man_t * pMan;
int i;
// int i;
pMan = Abc_NtkIvyBefore( pNtk, 1, 1 );
if ( pMan == NULL )
return NULL;
//timeRetime = clock();
Ivy_ManHaigStart( pMan, fVerbose );
// Ivy_ManRewriteSeq( pMan, 0, 0 );
for ( i = 0; i < nIters; i++ )
Ivy_ManRewriteSeq( pMan, fUseZeroCost, 0 );
Ivy_ManHaigPostprocess( pMan, fVerbose );
// for ( i = 0; i < nIters; i++ )
// Ivy_ManRewriteSeq( pMan, fUseZeroCost, 0 );
Ivy_ManRewriteSeq( pMan, 0, 0 );
Ivy_ManRewriteSeq( pMan, 1, 0 );
//printf( "Haig size = %d.\n", Ivy_ManNodeNum(pMan->pHaig) );
// Ivy_ManHaigPostprocess( pMan, fVerbose );
//timeRetime = clock() - timeRetime;
// write working AIG into the current network
// pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 1, 0 );
@ -246,7 +255,9 @@ Abc_Ntk_t * Abc_NtkIvyRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeroC
pMan = Abc_NtkIvyBefore( pNtk, 0, 0 );
if ( pMan == NULL )
return NULL;
//timeRetime = clock();
Ivy_ManRewritePre( pMan, fUpdateLevel, fUseZeroCost, fVerbose );
//timeRetime = clock() - timeRetime;
pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 0, 0 );
Ivy_ManStop( pMan );
return pNtkAig;
@ -270,7 +281,9 @@ Abc_Ntk_t * Abc_NtkIvyRewriteSeq( Abc_Ntk_t * pNtk, int fUseZeroCost, int fVerbo
pMan = Abc_NtkIvyBefore( pNtk, 1, 1 );
if ( pMan == NULL )
return NULL;
//timeRetime = clock();
Ivy_ManRewriteSeq( pMan, fUseZeroCost, fVerbose );
//timeRetime = clock() - timeRetime;
// Ivy_ManRewriteSeq( pMan, 1, 0 );
// Ivy_ManRewriteSeq( pMan, 1, 0 );
pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 1, 0 );

2
src/base/abci/abcLut.c
View File

@ -104,7 +104,7 @@ int Abc_NtkSuperChoiceLut( Abc_Ntk_t * pNtk, int nLutSize, int nCutSizeMax, int
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->Level = 0;
//Abc_NtkGetLevelNum( pNtk );
//Abc_NtkLevel( pNtk );
// start the managers
pManScl = Abc_ManSclStart( nLutSize, nCutSizeMax, 1000 );

54
src/base/abci/abcMini.c
View File

@ -24,8 +24,8 @@
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static Aig_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk );
static Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan );
static Hop_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk );
static Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Hop_Man_t * pMan );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@ -45,29 +45,29 @@ static Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan );
Abc_Ntk_t * Abc_NtkMiniBalance( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkAig;
Aig_Man_t * pMan, * pTemp;
Hop_Man_t * pMan, * pTemp;
assert( Abc_NtkIsStrash(pNtk) );
// convert to the AIG manager
pMan = Abc_NtkToAig( pNtk );
if ( pMan == NULL )
return NULL;
if ( !Aig_ManCheck( pMan ) )
if ( !Hop_ManCheck( pMan ) )
{
printf( "AIG check has failed.\n" );
Aig_ManStop( pMan );
Hop_ManStop( pMan );
return NULL;
}
// perform balance
Aig_ManPrintStats( pMan );
// Aig_ManDumpBlif( pMan, "aig_temp.blif" );
pMan = Aig_ManBalance( pTemp = pMan, 1 );
Aig_ManStop( pTemp );
Aig_ManPrintStats( pMan );
Hop_ManPrintStats( pMan );
// Hop_ManDumpBlif( pMan, "aig_temp.blif" );
pMan = Hop_ManBalance( pTemp = pMan, 1 );
Hop_ManStop( pTemp );
Hop_ManPrintStats( pMan );
// convert from the AIG manager
pNtkAig = Abc_NtkFromAig( pNtk, pMan );
if ( pNtkAig == NULL )
return NULL;
Aig_ManStop( pMan );
Hop_ManStop( pMan );
// make sure everything is okay
if ( !Abc_NtkCheck( pNtkAig ) )
{
@ -89,24 +89,24 @@ Abc_Ntk_t * Abc_NtkMiniBalance( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
Aig_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk )
Hop_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk )
{
Aig_Man_t * pMan;
Hop_Man_t * pMan;
Abc_Obj_t * pObj;
int i;
// create the manager
pMan = Aig_ManStart();
pMan = Hop_ManStart();
// transfer the pointers to the basic nodes
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Aig_ManConst1(pMan);
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Hop_ManConst1(pMan);
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Aig_ObjCreatePi(pMan);
pObj->pCopy = (Abc_Obj_t *)Hop_ObjCreatePi(pMan);
// perform the conversion of the internal nodes (assumes DFS ordering)
Abc_NtkForEachNode( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Aig_And( pMan, (Aig_Obj_t *)Abc_ObjChild0Copy(pObj), (Aig_Obj_t *)Abc_ObjChild1Copy(pObj) );
pObj->pCopy = (Abc_Obj_t *)Hop_And( pMan, (Hop_Obj_t *)Abc_ObjChild0Copy(pObj), (Hop_Obj_t *)Abc_ObjChild1Copy(pObj) );
// create the POs
Abc_NtkForEachCo( pNtk, pObj, i )
Aig_ObjCreatePo( pMan, (Aig_Obj_t *)Abc_ObjChild0Copy(pObj) );
Aig_ManCleanup( pMan );
Hop_ObjCreatePo( pMan, (Hop_Obj_t *)Abc_ObjChild0Copy(pObj) );
Hop_ManCleanup( pMan );
return pMan;
}
@ -121,26 +121,26 @@ Aig_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtk, Aig_Man_t * pMan )
Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtk, Hop_Man_t * pMan )
{
Vec_Ptr_t * vNodes;
Abc_Ntk_t * pNtkNew;
Aig_Obj_t * pObj;
Hop_Obj_t * pObj;
int i;
// perform strashing
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
// transfer the pointers to the basic nodes
Aig_ManConst1(pMan)->pData = Abc_AigConst1(pNtkNew);
Aig_ManForEachPi( pMan, pObj, i )
Hop_ManConst1(pMan)->pData = Abc_AigConst1(pNtkNew);
Hop_ManForEachPi( pMan, pObj, i )
pObj->pData = Abc_NtkCi(pNtkNew, i);
// rebuild the AIG
vNodes = Aig_ManDfs( pMan );
vNodes = Hop_ManDfs( pMan );
Vec_PtrForEachEntry( vNodes, pObj, i )
pObj->pData = Abc_AigAnd( pNtkNew->pManFunc, (Abc_Obj_t *)Aig_ObjChild0Copy(pObj), (Abc_Obj_t *)Aig_ObjChild1Copy(pObj) );
pObj->pData = Abc_AigAnd( pNtkNew->pManFunc, (Abc_Obj_t *)Hop_ObjChild0Copy(pObj), (Abc_Obj_t *)Hop_ObjChild1Copy(pObj) );
Vec_PtrFree( vNodes );
// connect the PO nodes
Aig_ManForEachPo( pMan, pObj, i )
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), (Abc_Obj_t *)Aig_ObjChild0Copy(pObj) );
Hop_ManForEachPo( pMan, pObj, i )
Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), (Abc_Obj_t *)Hop_ObjChild0Copy(pObj) );
if ( !Abc_NtkCheck( pNtkNew ) )
fprintf( stdout, "Abc_NtkFromAig(): Network check has failed.\n" );
return pNtkNew;

137
src/base/abci/abcNtbdd.c
View File

@ -27,7 +27,7 @@
static void Abc_NtkBddToMuxesPerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew );
static Abc_Obj_t * Abc_NodeBddToMuxes( Abc_Obj_t * pNodeOld, Abc_Ntk_t * pNtkNew );
static Abc_Obj_t * Abc_NodeBddToMuxes_rec( DdManager * dd, DdNode * bFunc, Abc_Ntk_t * pNtkNew, st_table * tBdd2Node );
static DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, ProgressBar * pProgress, int * pCounter, int fVerbose );
static DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, int fDropInternal, ProgressBar * pProgress, int * pCounter, int fVerbose );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
@ -243,85 +243,63 @@ Abc_Obj_t * Abc_NodeBddToMuxes_rec( DdManager * dd, DdNode * bFunc, Abc_Ntk_t *
SeeAlso []
***********************************************************************/
DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly, int fReorder, int fVerbose )
DdManager * Abc_NtkBuildGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fDropInternal, int fReorder, int fVerbose )
{
ProgressBar * pProgress;
Vec_Ptr_t * vFuncsGlob;
Abc_Obj_t * pObj, * pFanin;
DdNode * bFunc;
Vec_Att_t * pAttMan;
DdManager * dd;
DdNode * bFunc;
int i, k, Counter;
// remove dangling nodes
Abc_AigCleanup( pNtk->pManFunc );
// start the manager
assert( pNtk->pManGlob == NULL );
assert( Abc_NtkGlobalBdds(pNtk) == NULL );
dd = Cudd_Init( Abc_NtkCiNum(pNtk), 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
pAttMan = Vec_AttAlloc( 0, Abc_NtkObjNumMax(pNtk) + 1, dd, Extra_StopManager, NULL, Cudd_RecursiveDeref );
Vec_PtrWriteEntry( pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD, pAttMan );
// set reordering
if ( fReorder )
Cudd_AutodynEnable( dd, CUDD_REORDER_SYMM_SIFT );
// clean storage for local BDDs
Abc_NtkCleanCopy( pNtk );
// set the elementary variables
Abc_NtkForEachCi( pNtk, pObj, i )
if ( Abc_ObjFanoutNum(pObj) > 0 )
{
pObj->pCopy = (Abc_Obj_t *)dd->vars[i];
Cudd_Ref( dd->vars[i] );
}
// assign the constant node BDD
pObj = Abc_AigConst1(pNtk);
if ( Abc_ObjFanoutNum(pObj) > 0 )
{
pObj->pCopy = (Abc_Obj_t *)dd->one;
Abc_ObjSetGlobalBdd( pObj, dd->one );
Cudd_Ref( dd->one );
}
// set the elementary variables
Abc_NtkForEachCi( pNtk, pObj, i )
if ( Abc_ObjFanoutNum(pObj) > 0 )
{
Abc_ObjSetGlobalBdd( pObj, dd->vars[i] );
Cudd_Ref( dd->vars[i] );
}
// collect the global functions of the COs
Counter = 0;
vFuncsGlob = Vec_PtrAlloc( 100 );
if ( fLatchOnly )
// construct the BDDs
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
Abc_NtkForEachCo( pNtk, pObj, i )
{
// construct the BDDs
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
Abc_NtkForEachLatchInput( pNtk, pObj, i )
bFunc = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin0(pObj), nBddSizeMax, fDropInternal, pProgress, &Counter, fVerbose );
if ( bFunc == NULL )
{
bFunc = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin0(pObj), nBddSizeMax, pProgress, &Counter, fVerbose );
if ( bFunc == NULL )
{
if ( fVerbose )
printf( "Constructing global BDDs is aborted.\n" );
Vec_PtrFree( vFuncsGlob );
Cudd_Quit( dd );
return NULL;
}
bFunc = Cudd_NotCond( bFunc, Abc_ObjFaninC0(pObj) ); Cudd_Ref( bFunc );
Vec_PtrPush( vFuncsGlob, bFunc );
if ( fVerbose )
printf( "Constructing global BDDs is aborted.\n" );
Abc_NtkFreeGlobalBdds( pNtk, 0 );
Cudd_Quit( dd );
return NULL;
}
Extra_ProgressBarStop( pProgress );
}
else
{
// construct the BDDs
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
Abc_NtkForEachCo( pNtk, pObj, i )
{
bFunc = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin0(pObj), nBddSizeMax, pProgress, &Counter, fVerbose );
if ( bFunc == NULL )
{
if ( fVerbose )
printf( "Constructing global BDDs is aborted.\n" );
Vec_PtrFree( vFuncsGlob );
Cudd_Quit( dd );
return NULL;
}
bFunc = Cudd_NotCond( bFunc, Abc_ObjFaninC0(pObj) ); Cudd_Ref( bFunc );
Vec_PtrPush( vFuncsGlob, bFunc );
}
Extra_ProgressBarStop( pProgress );
bFunc = Cudd_NotCond( bFunc, Abc_ObjFaninC0(pObj) ); Cudd_Ref( bFunc );
Abc_ObjSetGlobalBdd( pObj, bFunc );
}
Extra_ProgressBarStop( pProgress );
/*
// derefence the intermediate BDDs
Abc_NtkForEachNode( pNtk, pObj, i )
@ -336,9 +314,9 @@ DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly
Abc_NtkForEachObj( pNtk, pObj, i )
{
if ( pObj->pCopy != NULL )
printf( "Abc_NtkGlobalBdds() error: Node %d has BDD assigned\n", pObj->Id );
printf( "Abc_NtkBuildGlobalBdds() error: Node %d has BDD assigned\n", pObj->Id );
if ( pObj->vFanouts.nSize > 0 )
printf( "Abc_NtkGlobalBdds() error: Node %d has refs assigned\n", pObj->Id );
printf( "Abc_NtkBuildGlobalBdds() error: Node %d has refs assigned\n", pObj->Id );
}
*/
// reset references
@ -353,8 +331,6 @@ DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly
Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 1 );
Cudd_AutodynDisable( dd );
}
pNtk->pManGlob = dd;
pNtk->vFuncsGlob = vFuncsGlob;
// Cudd_PrintInfo( dd, stdout );
return dd;
}
@ -370,9 +346,10 @@ DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly
SeeAlso []
***********************************************************************/
DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, ProgressBar * pProgress, int * pCounter, int fVerbose )
DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, int fDropInternal, ProgressBar * pProgress, int * pCounter, int fVerbose )
{
DdNode * bFunc, * bFunc0, * bFunc1, * bFuncC;
int fDetectMuxes = 1;
assert( !Abc_ObjIsComplement(pNode) );
if ( Cudd_ReadKeys(dd)-Cudd_ReadDead(dd) > (unsigned)nBddSizeMax )
{
@ -383,14 +360,14 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
return NULL;
}
// if the result is available return
if ( pNode->pCopy == NULL )
if ( Abc_ObjGlobalBdd(pNode) == NULL )
{
Abc_Obj_t * pNodeC, * pNode0, * pNode1;
pNode0 = Abc_ObjFanin0(pNode);
pNode1 = Abc_ObjFanin1(pNode);
// check for the special case when it is MUX/EXOR
// if ( 0 )
if ( pNode0->pCopy == NULL && pNode1->pCopy == NULL &&
if ( fDetectMuxes &&
Abc_ObjGlobalBdd(pNode0) == NULL && Abc_ObjGlobalBdd(pNode1) == NULL &&
Abc_ObjIsNode(pNode0) && Abc_ObjFanoutNum(pNode0) == 1 &&
Abc_ObjIsNode(pNode1) && Abc_ObjFanoutNum(pNode1) == 1 &&
Abc_NodeIsMuxType(pNode) )
@ -405,15 +382,15 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
pNodeC->vFanouts.nSize--;
// compute the result for all branches
bFuncC = Abc_NodeGlobalBdds_rec( dd, pNodeC, nBddSizeMax, pProgress, pCounter, fVerbose );
bFuncC = Abc_NodeGlobalBdds_rec( dd, pNodeC, nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFuncC == NULL )
return NULL;
Cudd_Ref( bFuncC );
bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode0), nBddSizeMax, pProgress, pCounter, fVerbose );
bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode0), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFunc0 == NULL )
return NULL;
Cudd_Ref( bFunc0 );
bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode1), nBddSizeMax, pProgress, pCounter, fVerbose );
bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode1), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFunc1 == NULL )
return NULL;
Cudd_Ref( bFunc1 );
@ -432,11 +409,11 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
else
{
// compute the result for both branches
bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,0), nBddSizeMax, pProgress, pCounter, fVerbose );
bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,0), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFunc0 == NULL )
return NULL;
Cudd_Ref( bFunc0 );
bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,1), nBddSizeMax, pProgress, pCounter, fVerbose );
bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,1), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFunc1 == NULL )
return NULL;
Cudd_Ref( bFunc1 );
@ -450,26 +427,26 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
(*pCounter)++;
}
// set the result
assert( pNode->pCopy == NULL );
pNode->pCopy = (Abc_Obj_t *)bFunc;
assert( Abc_ObjGlobalBdd(pNode) == NULL );
Abc_ObjSetGlobalBdd( pNode, bFunc );
// increment the progress bar
if ( pProgress )
Extra_ProgressBarUpdate( pProgress, *pCounter, NULL );
}
// prepare the return value
bFunc = (DdNode *)pNode->pCopy;
bFunc = Abc_ObjGlobalBdd(pNode);
// dereference BDD at the node
if ( --pNode->vFanouts.nSize == 0 )
if ( --pNode->vFanouts.nSize == 0 && fDropInternal )
{
Cudd_Deref( bFunc );
pNode->pCopy = NULL;
Abc_ObjSetGlobalBdd( pNode, NULL );
}
return bFunc;
}
/**Function*************************************************************
Synopsis [Dereferences global BDDs of the network.]
Synopsis [Frees the global BDDs of the network.]
Description []
@ -478,16 +455,9 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
SeeAlso []
***********************************************************************/
void Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk )
{
DdNode * bFunc;
int i;
assert( pNtk->pManGlob );
assert( pNtk->vFuncsGlob );
Vec_PtrForEachEntry( pNtk->vFuncsGlob, bFunc, i )
Cudd_RecursiveDeref( pNtk->pManGlob, bFunc );
Vec_PtrFree( pNtk->vFuncsGlob );
pNtk->vFuncsGlob = NULL;
DdManager * Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk, int fFreeMan )
{
return Abc_NtkAttrFree( pNtk, VEC_ATTR_GLOBAL_BDD, fFreeMan );
}
/**Function*************************************************************
@ -503,6 +473,7 @@ void Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk )
***********************************************************************/
double Abc_NtkSpacePercentage( Abc_Obj_t * pNode )
{
/*
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pNodeR;
DdManager * dd;
@ -521,7 +492,7 @@ double Abc_NtkSpacePercentage( Abc_Obj_t * pNode )
Vec_PtrForEachEntry( vNodes, pObj, i )
pObj->pCopy = (Abc_Obj_t *)dd->vars[i];
// build the BDD of the cone
bFunc = Abc_NodeGlobalBdds_rec( dd, pNodeR, 10000000, NULL, NULL, 1 ); Cudd_Ref( bFunc );
bFunc = Abc_NodeGlobalBdds_rec( dd, pNodeR, 10000000, 1, NULL, NULL, 1 ); Cudd_Ref( bFunc );
bFunc = Cudd_NotCond( bFunc, pNode != pNodeR );
// count minterms
Result = Cudd_CountMinterm( dd, bFunc, dd->size );
@ -533,6 +504,8 @@ double Abc_NtkSpacePercentage( Abc_Obj_t * pNode )
Cudd_Quit( dd );
Vec_PtrFree( vNodes );
return Result;
*/
return 0.0;
}

84
src/base/abci/abcPrint.c
View File

@ -113,9 +113,9 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
}
if ( Abc_NtkIsStrash(pNtk) )
fprintf( pFile, " lev = %3d", Abc_AigGetLevelNum(pNtk) );
fprintf( pFile, " lev = %3d", Abc_AigLevel(pNtk) );
else if ( !Abc_NtkIsSeq(pNtk) )
fprintf( pFile, " lev = %3d", Abc_NtkGetLevelNum(pNtk) );
fprintf( pFile, " lev = %3d", Abc_NtkLevel(pNtk) );
fprintf( pFile, "\n" );
// print the statistic into a file
@ -126,7 +126,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%d ", Abc_AigGetLevelNum(pNtk) );
fprintf( pTable, "%d ", Abc_AigLevel(pNtk) );
fprintf( pTable, "\n" );
fclose( pTable );
}
@ -150,7 +150,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
FILE * pTable;
pTable = fopen( "fpga/fpga_stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", Abc_NtkGetLevelNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%.2f ", (float)(s_MappingMem)/(float)(1<<20) );
fprintf( pTable, "%.2f", (float)(s_MappingTime)/(float)(CLOCKS_PER_SEC) );
@ -159,6 +159,24 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
}
*/
// print the statistic into a file
{
static int Counter = 0;
extern int timeRetime;
FILE * pTable;
Counter++;
pTable = fopen( "a/ret__stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
fprintf( pTable, "%.2f ", (float)(timeRetime)/(float)(CLOCKS_PER_SEC) );
if ( Counter % 4 == 0 )
fprintf( pTable, "\n" );
fclose( pTable );
}
/*
// print the statistic into a file
{
@ -166,14 +184,14 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
extern int timeRetime;
FILE * pTable;
Counter++;
pTable = fopen( "sap/stats_retime.txt", "a+" );
pTable = fopen( "d/stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
// fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkPoNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkGetLevelNum(pNtk) );
fprintf( pTable, "%.2f ", (float)(timeRetime)/(float)(CLOCKS_PER_SEC) );
if ( Counter % 4 == 0 )
fprintf( pTable, "\n" );
fprintf( pTable, "\n" );
fclose( pTable );
}
*/
@ -214,7 +232,8 @@ void Abc_NtkPrintIo( FILE * pFile, Abc_Ntk_t * pNtk )
fprintf( pFile, "Latches (%d): ", Abc_NtkLatchNum(pNtk) );
Abc_NtkForEachLatch( pNtk, pObj, i )
fprintf( pFile, " %s", Abc_ObjName(pObj) );
fprintf( pFile, " %s(%s=%s)", Abc_ObjName(pObj),
Abc_ObjName(Abc_ObjFanout0(pObj)), Abc_ObjName(Abc_ObjFanin0(pObj)) );
fprintf( pFile, "\n" );
}
@ -500,7 +519,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile, int fListN
if ( fListNodes )
{
int nLevels;
nLevels = Abc_NtkGetLevelNum(pNtk);
nLevels = Abc_NtkLevel(pNtk);
printf( "Nodes by level:\n" );
for ( i = 0; i <= nLevels; i++ )
{
@ -553,7 +572,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile, int fListN
int nOutsSum, nOutsTotal;
if ( !Abc_NtkIsStrash(pNtk) )
Abc_NtkGetLevelNum(pNtk);
Abc_NtkLevel(pNtk);
LevelMax = 0;
Abc_NtkForEachCo( pNtk, pNode, i )
@ -838,41 +857,6 @@ void Abc_NtkPrintStrSupports( Abc_Ntk_t * pNtk )
}
}
/**Function*************************************************************
Synopsis [Prints information about the clock skew schedule.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintSkews( FILE * pFile, Abc_Ntk_t * pNtk, int fPrintAll ) {
Abc_Obj_t * pObj;
int i;
int nNonZero = 0;
float skew, sum = 0.0, avg;
if (fPrintAll) fprintf( pFile, "Full Clock Skew Schedule:\n\tGlobal Skew = %.2f\n", pNtk->globalSkew );
Abc_NtkForEachLatch( pNtk, pObj, i ) {
skew = Abc_NtkGetLatSkew( pNtk, i );
if ( skew != 0.0 ) {
nNonZero++;
sum += ABS( skew );
}
if (fPrintAll) fprintf( pFile, "\tLatch %d (Id = %d) \t Endpoint Skew = %.2f\n", i, pObj->Id, skew);
}
avg = sum / Abc_NtkLatchNum( pNtk );
fprintf( pFile, "Endpoint Skews : Total |Skew| = %.2f\t Avg |Skew| = %.2f\t Non-Zero Skews = %d\n",
sum, avg, nNonZero );
}
/**Function*************************************************************
Synopsis [Prints information about the object.]
@ -942,6 +926,12 @@ void Abc_ObjPrint( FILE * pFile, Abc_Obj_t * pObj )
Abc_ObjForEachFanin( pObj, pFanin, i )
fprintf( pFile, "%d ", pFanin->Id );
fprintf( pFile, ") " );
/*
fprintf( pFile, " Fanouts ( " );
Abc_ObjForEachFanout( pObj, pFanin, i )
fprintf( pFile, "%d(%c) ", pFanin->Id, Abc_NodeIsTravIdCurrent(pFanin)? '+' : '-' );
fprintf( pFile, ") " );
*/
// print the logic function
if ( Abc_ObjIsNode(pObj) && Abc_NtkIsSopLogic(pObj->pNtk) )
fprintf( pFile, " %s", pObj->pData );

2
src/base/abci/abcProve.c
View File

@ -310,7 +310,7 @@ void Abc_NtkMiterPrint( Abc_Ntk_t * pNtk, char * pString, int clk, int fVerbose
if ( !fVerbose )
return;
printf( "Nodes = %7d. Levels = %4d. ", Abc_NtkNodeNum(pNtk),
Abc_NtkIsStrash(pNtk)? Abc_AigGetLevelNum(pNtk) : Abc_NtkGetLevelNum(pNtk) );
Abc_NtkIsStrash(pNtk)? Abc_AigLevel(pNtk) : Abc_NtkLevel(pNtk) );
PRT( pString, clock() - clk );
}

2
src/base/abci/abcRefactor.c
View File

@ -156,7 +156,7 @@ pManRef->timeTotal = clock() - clkStart;
if ( fUpdateLevel )
Abc_NtkStopReverseLevels( pNtk );
else
Abc_NtkGetLevelNum( pNtk );
Abc_NtkLevel( pNtk );
// check
if ( !Abc_NtkCheck( pNtk ) )
{

2
src/base/abci/abcRestruct.c
View File

@ -183,7 +183,7 @@ pManRst->timeTotal = clock() - clkStart;
if ( fUpdateLevel )
Abc_NtkStopReverseLevels( pNtk );
else
Abc_NtkGetLevelNum( pNtk );
Abc_NtkLevel( pNtk );
// check
if ( !Abc_NtkCheck( pNtk ) )
{

2
src/base/abci/abcResub.c
View File

@ -232,7 +232,7 @@ pManRes->timeTotal = clock() - clkStart;
if ( fUpdateLevel )
Abc_NtkStopReverseLevels( pNtk );
else
Abc_NtkGetLevelNum( pNtk );
Abc_NtkLevel( pNtk );
// check
if ( !Abc_NtkCheck( pNtk ) )
{

2
src/base/abci/abcRewrite.c
View File

@ -158,7 +158,7 @@ Rwr_ManAddTimeTotal( pManRwr, clock() - clkStart );
if ( fUpdateLevel )
Abc_NtkStopReverseLevels( pNtk );
else
Abc_NtkGetLevelNum( pNtk );
Abc_NtkLevel( pNtk );
// check
if ( !Abc_NtkCheck( pNtk ) )
{

6
src/base/abci/abcRr.c
View File

@ -104,7 +104,7 @@ int Abc_NtkRR( Abc_Ntk_t * pNtk, int nFaninLevels, int nFanoutLevels, int fUseFa
p->nFaninLevels = nFaninLevels;
p->nFanoutLevels = nFanoutLevels;
p->nNodesOld = Abc_NtkNodeNum(pNtk);
p->nLevelsOld = Abc_AigGetLevelNum(pNtk);
p->nLevelsOld = Abc_AigLevel(pNtk);
// remember latch values
// Abc_NtkForEachLatch( pNtk, pNode, i )
// pNode->pNext = pNode->pData;
@ -220,7 +220,7 @@ int Abc_NtkRR( Abc_Ntk_t * pNtk, int nFaninLevels, int nFanoutLevels, int fUseFa
// pNode->pData = pNode->pNext, pNode->pNext = NULL;
// put the nodes into the DFS order and reassign their IDs
Abc_NtkReassignIds( pNtk );
Abc_NtkGetLevelNum( pNtk );
Abc_NtkLevel( pNtk );
// check
if ( !Abc_NtkCheck( pNtk ) )
{
@ -298,7 +298,7 @@ void Abc_RRManPrintStats( Abc_RRMan_t * p )
printf( "Edges tried = %6d.\n", p->nEdgesTried );
printf( "Edges removed = %6d. (%5.2f %%)\n", p->nEdgesRemoved, 100.0*p->nEdgesRemoved/p->nEdgesTried );
printf( "Node gain = %6d. (%5.2f %%)\n", p->nNodesOld - Abc_NtkNodeNum(p->pNtk), Ratio );
printf( "Level gain = %6d.\n", p->nLevelsOld - Abc_AigGetLevelNum(p->pNtk) );
printf( "Level gain = %6d.\n", p->nLevelsOld - Abc_AigLevel(p->pNtk) );
PRT( "Windowing ", p->timeWindow );
PRT( "Miter ", p->timeMiter );
PRT( " Construct ", p->timeMiter - p->timeProve );

2
src/base/abci/abcSat.c
View File

@ -458,7 +458,7 @@ int Abc_NtkMiterSatCreateInt( solver * pSat, Abc_Ntk_t * pNtk, int fJFront )
int i, k, fUseMuxes = 1;
int clk1 = clock(), clk;
int fOrderCiVarsFirst = 0;
int nLevelsMax = Abc_AigGetLevelNum(pNtk);
int nLevelsMax = Abc_AigLevel(pNtk);
int RetValue = 0;
assert( Abc_NtkIsStrash(pNtk) );

55
src/base/abci/abcStrash.c
View File

@ -1,6 +1,6 @@
/**CFile****************************************************************
FileName [aigStrash.c]
FileName [abcStrash.c]
SystemName [ABC: Logic synthesis and verification system.]
@ -14,7 +14,7 @@
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: aigStrash.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
Revision [$Id: abcStrash.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
@ -46,10 +46,12 @@ static void Abc_NtkStrashPerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew, bool fA
***********************************************************************/
Abc_Ntk_t * Abc_NtkRestrash( Abc_Ntk_t * pNtk, bool fCleanup )
{
extern int timeRetime;
Abc_Ntk_t * pNtkAig;
Abc_Obj_t * pObj;
int i, nNodes;
int i, nNodes, RetValue;
assert( Abc_NtkIsStrash(pNtk) );
//timeRetime = clock();
// print warning about choice nodes
if ( Abc_NtkGetChoiceNum( pNtk ) )
printf( "Warning: The choice nodes in the original AIG are removed by strashing.\n" );
@ -58,7 +60,7 @@ Abc_Ntk_t * Abc_NtkRestrash( Abc_Ntk_t * pNtk, bool fCleanup )
// restrash the nodes (assuming a topological order of the old network)
Abc_NtkForEachNode( pNtk, pObj, i )
pObj->pCopy = Abc_AigAnd( pNtkAig->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild1Copy(pObj) );
// finalize the network
//l finalize the network
Abc_NtkFinalize( pNtk, pNtkAig );
// print warning about self-feed latches
// if ( Abc_NtkCountSelfFeedLatches(pNtkAig) )
@ -76,6 +78,9 @@ Abc_Ntk_t * Abc_NtkRestrash( Abc_Ntk_t * pNtk, bool fCleanup )
Abc_NtkDelete( pNtkAig );
return NULL;
}
//timeRetime = clock() - timeRetime;
if ( RetValue = Abc_NtkRemoveSelfFeedLatches(pNtkAig) )
printf( "Modified %d self-feeding latches. The result will not verify.\n", RetValue );
return pNtkAig;
}
@ -106,7 +111,7 @@ Abc_Ntk_t * Abc_NtkStrash( Abc_Ntk_t * pNtk, bool fAllNodes, bool fCleanup )
return NULL;
}
// perform strashing
Abc_NtkCleanCopy( pNtk );
// Abc_NtkCleanCopy( pNtk );
pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
Abc_NtkStrashPerform( pNtk, pNtkAig, fAllNodes );
Abc_NtkFinalize( pNtk, pNtkAig );
@ -205,13 +210,17 @@ int Abc_NtkAppend( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int fAddPos )
***********************************************************************/
void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, bool fAllNodes )
{
extern Vec_Ptr_t * Abc_NtkDfsIter( Abc_Ntk_t * pNtk, int fCollectAll );
ProgressBar * pProgress;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNodeOld;
int i;
int i, clk = clock();
assert( Abc_NtkIsLogic(pNtkOld) );
assert( Abc_NtkIsStrash(pNtkNew) );
vNodes = Abc_NtkDfs( pNtkOld, fAllNodes );
// vNodes = Abc_NtkDfs( pNtkOld, fAllNodes );
vNodes = Abc_NtkDfsIter( pNtkOld, fAllNodes );
//printf( "Nodes = %d. ", Vec_PtrSize(vNodes) );
//PRT( "Time", clock() - clk );
pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize );
Vec_PtrForEachEntry( vNodes, pNodeOld, i )
{
@ -233,16 +242,16 @@ void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, bool fAllNo
SeeAlso []
***********************************************************************/
void Abc_NodeStrash_rec( Abc_Aig_t * pMan, Aig_Obj_t * pObj )
void Abc_NodeStrash_rec( Abc_Aig_t * pMan, Hop_Obj_t * pObj )
{
assert( !Aig_IsComplement(pObj) );
if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
assert( !Hop_IsComplement(pObj) );
if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
return;
Abc_NodeStrash_rec( pMan, Aig_ObjFanin0(pObj) );
Abc_NodeStrash_rec( pMan, Aig_ObjFanin1(pObj) );
pObj->pData = Abc_AigAnd( pMan, (Abc_Obj_t *)Aig_ObjChild0Copy(pObj), (Abc_Obj_t *)Aig_ObjChild1Copy(pObj) );
assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
Aig_ObjSetMarkA( pObj );
Abc_NodeStrash_rec( pMan, Hop_ObjFanin0(pObj) );
Abc_NodeStrash_rec( pMan, Hop_ObjFanin1(pObj) );
pObj->pData = Abc_AigAnd( pMan, (Abc_Obj_t *)Hop_ObjChild0Copy(pObj), (Abc_Obj_t *)Hop_ObjChild1Copy(pObj) );
assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
Hop_ObjSetMarkA( pObj );
}
/**Function*************************************************************
@ -258,8 +267,8 @@ void Abc_NodeStrash_rec( Abc_Aig_t * pMan, Aig_Obj_t * pObj )
***********************************************************************/
Abc_Obj_t * Abc_NodeStrash( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
{
Aig_Man_t * pMan;
Aig_Obj_t * pRoot;
Hop_Man_t * pMan;
Hop_Obj_t * pRoot;
Abc_Obj_t * pFanin;
int i;
assert( Abc_ObjIsNode(pNodeOld) );
@ -269,15 +278,15 @@ Abc_Obj_t * Abc_NodeStrash( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
pRoot = pNodeOld->pData;
// check the constant case
if ( Abc_NodeIsConst(pNodeOld) )
return Abc_ObjNotCond( Abc_AigConst1(pNtkNew), Aig_IsComplement(pRoot) );
return Abc_ObjNotCond( Abc_AigConst1(pNtkNew), Hop_IsComplement(pRoot) );
// set elementary variables
Abc_ObjForEachFanin( pNodeOld, pFanin, i )
Aig_IthVar(pMan, i)->pData = pFanin->pCopy;
Hop_IthVar(pMan, i)->pData = pFanin->pCopy;
// strash the AIG of this node
Abc_NodeStrash_rec( pNtkNew->pManFunc, Aig_Regular(pRoot) );
Aig_ConeUnmark_rec( Aig_Regular(pRoot) );
Abc_NodeStrash_rec( pNtkNew->pManFunc, Hop_Regular(pRoot) );
Hop_ConeUnmark_rec( Hop_Regular(pRoot) );
// return the final node
return Abc_ObjNotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );
return Abc_ObjNotCond( Hop_Regular(pRoot)->pData, Hop_IsComplement(pRoot) );
}
@ -328,7 +337,7 @@ Abc_Ntk_t * Abc_NtkTopmost( Abc_Ntk_t * pNtk, int nLevels )
assert( Abc_NtkIsStrash(pNtk) );
assert( Abc_NtkCoNum(pNtk) == 1 );
// get the cutoff level
LevelCut = ABC_MAX( 0, Abc_AigGetLevelNum(pNtk) - nLevels );
LevelCut = ABC_MAX( 0, Abc_AigLevel(pNtk) - nLevels );
// start the network
pNtkNew = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
pNtkNew->pName = Extra_UtilStrsav(pNtk->pName);

38
src/base/abci/abcSweep.c
View File

@ -79,7 +79,7 @@ bool Abc_NtkFraigSweep( Abc_Ntk_t * pNtk, int fUseInv, int fExdc, int fVerbose )
if ( fUseTrick )
{
extern void * Abc_FrameReadLibGen();
Aig_ManStop( pNtk->pManFunc );
Hop_ManStop( pNtk->pManFunc );
pNtk->pManFunc = Abc_FrameReadLibGen();
pNtk->ntkFunc = ABC_FUNC_MAP;
Abc_NtkForEachNode( pNtk, pObj, i )
@ -269,7 +269,7 @@ void Abc_NtkFraigTransform( Abc_Ntk_t * pNtk, stmm_table * tEquiv, int fUseInv,
if ( stmm_count(tEquiv) == 0 )
return;
// assign levels to the nodes of the network
Abc_NtkGetLevelNum( pNtk );
Abc_NtkLevel( pNtk );
// merge nodes in the classes
if ( Abc_NtkHasMapping( pNtk ) )
{
@ -897,7 +897,7 @@ int Abc_NtkReplaceAutonomousLogic( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fVerbose )
int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fLatchSweep, int fAutoSweep, int fVerbose )
{
Vec_Ptr_t * vNodes;
int Counter;
@ -910,20 +910,26 @@ int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fVerbose )
if ( fVerbose )
printf( "Cleanup removed %4d dangling objects.\n", Counter );
// check if some of the latches can be removed
Counter = Abc_NtkLatchSweep( pNtk );
if ( fVerbose )
printf( "Cleanup removed %4d redundant latches.\n", Counter );
if ( fLatchSweep )
{
Counter = Abc_NtkLatchSweep( pNtk );
if ( fVerbose )
printf( "Cleanup removed %4d redundant latches.\n", Counter );
}
// detect the autonomous components
vNodes = Abc_NtkDfsSeqReverse( pNtk );
Vec_PtrFree( vNodes );
// replace them by PIs
Counter = Abc_NtkReplaceAutonomousLogic( pNtk );
if ( fVerbose )
printf( "Cleanup added %4d additional PIs.\n", Counter );
// remove the non-marked nodes
Counter = Abc_NodeRemoveNonCurrentObjects( pNtk );
if ( fVerbose )
printf( "Cleanup removed %4d autonomous objects.\n", Counter );
if ( fAutoSweep )
{
vNodes = Abc_NtkDfsSeqReverse( pNtk );
Vec_PtrFree( vNodes );
// replace them by PIs
Counter = Abc_NtkReplaceAutonomousLogic( pNtk );
if ( fVerbose )
printf( "Cleanup added %4d additional PIs.\n", Counter );
// remove the non-marked nodes
Counter = Abc_NodeRemoveNonCurrentObjects( pNtk );
if ( fVerbose )
printf( "Cleanup removed %4d autonomous objects.\n", Counter );
}
// check
if ( !Abc_NtkCheck( pNtk ) )
printf( "Abc_NtkCleanupSeq: The network check has failed.\n" );

12
src/base/abci/abcSymm.c
View File

@ -88,7 +88,7 @@ void Abc_NtkSymmetriesUsingBdds( Abc_Ntk_t * pNtk, int fNaive, int fVerbose )
// compute the global functions
clk = clock();
dd = Abc_NtkGlobalBdds( pNtk, 10000000, 0, 1, fVerbose );
dd = Abc_NtkBuildGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );
Cudd_AutodynDisable( dd );
Cudd_zddVarsFromBddVars( dd, 2 );
clkBdd = clock() - clk;
@ -97,9 +97,10 @@ clk = clock();
Ntk_NetworkSymmsBdd( dd, pNtk, fNaive, fVerbose );
clkSym = clock() - clk;
// undo the global functions
Abc_NtkFreeGlobalBdds( pNtk );
Extra_StopManager( dd );
pNtk->pManGlob = NULL;
// Abc_NtkFreeGlobalBdds( pNtk );
// Extra_StopManager( dd );
// pNtk->pManGlob = NULL;
Abc_NtkFreeGlobalBdds( pNtk, 1 );
PRT( "Constructing BDDs", clkBdd );
PRT( "Computing symms ", clkSym );
@ -129,7 +130,8 @@ void Ntk_NetworkSymmsBdd( DdManager * dd, Abc_Ntk_t * pNtk, int fNaive, int fVer
// compute symmetry info for each PO
Abc_NtkForEachCo( pNtk, pNode, i )
{
bFunc = pNtk->vFuncsGlob->pArray[i];
// bFunc = pNtk->vFuncsGlob->pArray[i];
bFunc = Abc_ObjGlobalBdd( pNode );
nSupps += Cudd_SupportSize( dd, bFunc );
if ( Cudd_IsConstant(bFunc) )
continue;

4
src/base/abci/abcTiming.c
View File

@ -648,8 +648,8 @@ void Abc_NtkStartReverseLevels( Abc_Ntk_t * pNtk )
int i, k, nLevelsCur;
// assert( Abc_NtkIsStrash(pNtk) );
// remember the maximum number of direct levels
// pNtk->LevelMax = Abc_AigGetLevelNum(pNtk);
pNtk->LevelMax = Abc_NtkGetLevelNum(pNtk);
// pNtk->LevelMax = Abc_AigLevel(pNtk);
pNtk->LevelMax = Abc_NtkLevel(pNtk);
// start the reverse levels
pNtk->vLevelsR = Vec_IntAlloc( 0 );
Vec_IntFill( pNtk->vLevelsR, Abc_NtkObjNumMax(pNtk), 0 );

23
src/base/abci/abcUnate.c
View File

@ -66,20 +66,22 @@ void Abc_NtkPrintUnateBdd( Abc_Ntk_t * pNtk, int fUseNaive, int fVerbose )
Abc_Obj_t * pNode;
Extra_UnateInfo_t * p;
DdManager * dd; // the BDD manager used to hold shared BDDs
DdNode ** pbGlobal; // temporary storage for global BDDs
// DdNode ** pbGlobal; // temporary storage for global BDDs
int TotalSupps = 0;
int TotalUnate = 0;
int i, clk = clock();
int clkBdd, clkUnate;
// compute the global BDDs
if ( Abc_NtkGlobalBdds(pNtk, 10000000, 0, 1, fVerbose) == NULL )
dd = Abc_NtkBuildGlobalBdds(pNtk, 10000000, 1, 1, fVerbose);
if ( dd == NULL )
return;
clkBdd = clock() - clk;
// get information about the network
dd = pNtk->pManGlob;
pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
// dd = pNtk->pManGlob;
// dd = Abc_NtkGlobalBddMan( pNtk );
// pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
// print the size of the BDDs
printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
@ -89,7 +91,8 @@ clkBdd = clock() - clk;
{
Abc_NtkForEachCo( pNtk, pNode, i )
{
p = Extra_UnateComputeSlow( dd, pbGlobal[i] );
// p = Extra_UnateComputeSlow( dd, pbGlobal[i] );
p = Extra_UnateComputeSlow( dd, Abc_ObjGlobalBdd(pNode) );
if ( fVerbose )
Extra_UnateInfoPrint( p );
TotalSupps += p->nVars;
@ -104,7 +107,8 @@ clkBdd = clock() - clk;
Cudd_zddVarsFromBddVars( dd, 2 );
Abc_NtkForEachCo( pNtk, pNode, i )
{
p = Extra_UnateComputeFast( dd, pbGlobal[i] );
// p = Extra_UnateComputeFast( dd, pbGlobal[i] );
p = Extra_UnateComputeFast( dd, Abc_ObjGlobalBdd(pNode) );
if ( fVerbose )
Extra_UnateInfoPrint( p );
TotalSupps += p->nVars;
@ -122,10 +126,11 @@ clkUnate = clock() - clk - clkBdd;
PRT( "Total ", clock() - clk );
// deref the PO functions
Abc_NtkFreeGlobalBdds( pNtk );
// Abc_NtkFreeGlobalBdds( pNtk );
// stop the global BDD manager
Extra_StopManager( pNtk->pManGlob );
pNtk->pManGlob = NULL;
// Extra_StopManager( pNtk->pManGlob );
// pNtk->pManGlob = NULL;
Abc_NtkFreeGlobalBdds( pNtk, 1 );
}
/**Function*************************************************************

10
src/base/abci/abcUnreach.c
View File

@ -58,7 +58,7 @@ int Abc_NtkExtractSequentialDcs( Abc_Ntk_t * pNtk, bool fVerbose )
}
// compute the global BDDs of the latches
dd = Abc_NtkGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );
dd = Abc_NtkBuildGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );
if ( dd == NULL )
return 0;
if ( fVerbose )
@ -92,7 +92,7 @@ int Abc_NtkExtractSequentialDcs( Abc_Ntk_t * pNtk, bool fVerbose )
pNtk->pExdc = Abc_NtkConstructExdc( dd, pNtk, bUnreach );
Cudd_RecursiveDeref( dd, bUnreach );
Extra_StopManager( dd );
pNtk->pManGlob = NULL;
// pNtk->pManGlob = NULL;
// make sure that everything is okay
if ( pNtk->pExdc && !Abc_NtkCheck( pNtk->pExdc ) )
@ -137,13 +137,15 @@ DdNode * Abc_NtkTransitionRelation( DdManager * dd, Abc_Ntk_t * pNtk, int fVerbo
Abc_NtkForEachLatch( pNtk, pNode, i )
{
bVar = Cudd_bddIthVar( dd, Abc_NtkCiNum(pNtk) + i );
bProd = Cudd_bddXnor( dd, bVar, pNtk->vFuncsGlob->pArray[i] ); Cudd_Ref( bProd );
// bProd = Cudd_bddXnor( dd, bVar, pNtk->vFuncsGlob->pArray[i] ); Cudd_Ref( bProd );
bProd = Cudd_bddXnor( dd, bVar, Abc_ObjGlobalBdd(Abc_ObjFanin0(pNode)) ); Cudd_Ref( bProd );
bRel = Cudd_bddAnd( dd, bTemp = bRel, bProd ); Cudd_Ref( bRel );
Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bProd );
}
// free the global BDDs
Abc_NtkFreeGlobalBdds( pNtk );
// Abc_NtkFreeGlobalBdds( pNtk );
Abc_NtkFreeGlobalBdds( pNtk, 0 );
// quantify the PI variables
bInputs = Extra_bddComputeRangeCube( dd, 0, Abc_NtkPiNum(pNtk) ); Cudd_Ref( bInputs );

2
src/base/abci/module.make
View File

@ -15,6 +15,7 @@ SRC += src/base/abci/abc.c \
src/base/abci/abcFraig.c \
src/base/abci/abcFxu.c \
src/base/abci/abcGen.c \
src/base/abci/abcIf.c \
src/base/abci/abcIvy.c \
src/base/abci/abcLut.c \
src/base/abci/abcMap.c \
@ -22,7 +23,6 @@ SRC += src/base/abci/abc.c \
src/base/abci/abcMiter.c \
src/base/abci/abcNtbdd.c \
src/base/abci/abcOrder.c \
src/base/abci/abcPga.c \
src/base/abci/abcPrint.c \
src/base/abci/abcProve.c \
src/base/abci/abcReconv.c \

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