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1,665 Commits 30 Branches 59 Tags
91ca83e86485ea6696cae7df502ad7d6bf5ae708
Commit Graph
899 Commits
Author SHA1 Message Date
Alan Mishchenko d21c0be44a Added slack computation to 'stime'. 2012-09-20 14:13:59 -07:00
Alan Mishchenko 266af49386 Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 13:12:51 -07:00
Alan Mishchenko bc44087bac Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 12:41:59 -07:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00
Alan Mishchenko 723f85ef1b Extending Liberty parser to handle multi-output cells. 2012-09-19 20:21:27 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 480ca14c75 Extending Liberty parser to handle multi-output cells. 2012-09-19 17:35:04 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko e0eb270324 Changes to command 'upsize'. 2012-09-18 13:23:58 -07:00
Alan Mishchenko 508b6f1b13 Fixing mismatch between declaration of the output value of Extra_CpuTime. 2012-09-18 09:58:06 -07:00
Alan Mishchenko 7e843d64a9 Added delay multipliers to 'map'. 2012-09-16 23:34:56 -07:00
Alan Mishchenko 6d05fde2dc Added delay multipliers to 'map'. 2012-09-16 22:05:15 -07:00
Alan Mishchenko ee436f9377 Changed a few things in the refinement package of &gla. 2012-09-16 13:56:10 -07:00
Alan Mishchenko 5953beb2da Restructured the code to post-process object used during refinement in &gla. 2012-09-16 09:54:19 -07:00
Alan Mishchenko fdf5ad3433 Cleaned 'abc.c' by removing useless procedures. 2012-09-15 23:52:36 -07:00
Alan Mishchenko 69bbfa9856 Created new abstraction package from the code that was all over the place. 2012-09-15 23:27:46 -07:00
Alan Mishchenko 117bc0dbcd Prepared &gla to try abstracting and proving concurrently. 2012-09-14 21:20:37 -07:00
Alan Mishchenko 3b14c7b490 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 13:31:29 -07:00
Alan Mishchenko 19c28cae94 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 10:27:48 -07:00
Alan Mishchenko a246882a5b Scalable gate-level abstraction. 2012-09-11 19:11:51 -07:00
Niklas Een 1c865bf229 Added -C to command line for running commands, then staying in interactive mode 2012-09-11 18:48:43 -07:00
Alan Mishchenko 784a3579e5 Fixing Verilog writer's way of writing module names. 2012-09-11 18:44:07 -07:00
Alan Mishchenko d40af538e2 Unified print-out of property failures produced by all engines. 2012-09-09 20:46:34 -07:00
Alan Mishchenko 56117d56e8 Added switch '-p' to '&gla -n' to use full proof for UNSAT core computation (for experiments). 2012-09-09 15:28:31 -07:00
Alan Mishchenko 4333fd24d2 Started CEX minimization procedure. 2012-09-08 18:28:13 -07:00
Alan Mishchenko 5ca4f3cf9f Updating &gla_refine to perform suffic refinement. 2012-09-07 23:26:23 -07:00
Alan Mishchenko 548e04192b Updating &gla_refine to perform suffic refinement. 2012-09-07 20:44:12 -07:00
Alan Mishchenko 39fe23f079 Integrated new fast semi-canonical form for Boolean functions up to 16 inputs. 2012-09-06 15:52:54 -07:00
Alan Mishchenko 9c8be56ccd Integrated new fast semi-canonical form for Boolean functions up to 16 inputs. 2012-09-06 15:32:07 -07:00
Alan Mishchenko cd2bd70865 Added switch 'dch -r' to skip choices with structural support redundancy. 2012-09-05 19:39:25 -07:00
Alan Mishchenko c1f4545e07 Added error message when the user is trying 'dsat' for multi-output comb miters. 2012-09-05 18:53:21 -07:00
Alan Mishchenko f6b67d7846 Added new command &gla_shrink. 2012-09-04 23:57:58 -07:00
Alan Mishchenko 8e12b60b66 Better batch mode printout. 2012-09-04 14:39:14 -07:00
Alan Mishchenko 05f51cbb2a Enabled recording the name of the file GIA is coming from. 2012-09-04 13:52:42 -07:00
Alan Mishchenko 9621ae946e Added switch &srm -A <file> for dumping SRM into a user-specified file. 2012-09-02 20:12:03 -07:00
Alan Mishchenko a49ba2d280 Fixing the way constants are written into mapped Verilog files. 2012-08-31 00:05:10 -07:00
Alan Mishchenko 3400670839 Handling constant nodes in gate sizing. 2012-08-30 13:58:26 -07:00
Alan Mishchenko 83bfe0b1fe New package to read/write a subset of Liberty for STA. 2012-08-29 16:20:39 -07:00
Alan Mishchenko 6814c48bb4 Added an API to convert a multi-output PLA into a shared AIG. 2012-08-29 12:43:55 -07:00
Alan Mishchenko 5ff49be993 Ensured that SC mapped network is always in a topo order. 2012-08-28 19:42:53 -07:00
Alan Mishchenko 9b02fe59bd Added buffering based on combinational merging. 2012-08-28 19:24:13 -07:00
Alan Mishchenko 329831bdac Bug fix: abstraction commands not properly updating status when dumping intermediate abstraction. 2012-08-28 12:12:24 -07:00
Alan Mishchenko 8a1d439cb1 Added precomputation of TFO ordering for incremental network updates. 2012-08-27 22:11:29 -07:00
Alan Mishchenko a6bfd49591 Improved printout of command history. 2012-08-27 19:57:44 -07:00
Alan Mishchenko da6838463f Added features 'map -M <float>' to control the use of large gates. 2012-08-27 14:29:32 -07:00
Alan Mishchenko 889ed19c1c Compiler warnings. 2012-08-26 09:31:43 -07:00
Alan Mishchenko 137f0347f0 Added switch '&gla -m' to dump original miter with the abstraction map. 2012-08-26 09:21:45 -07:00
Alan Mishchenko fba0552f87 Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-25 14:57:06 -07:00
Alan Mishchenko bffbd05a2f Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-25 13:43:44 -07:00
Alan Mishchenko 2a7a06b653 Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-25 12:32:44 -07:00