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mirror of https://github.com/YosysHQ/abc.git synced 2026-09-01 18:27:44 +02:00
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05f51cbb2ad3856916325a4322401fe0d8fde408
abc/src/base
T
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Alan Mishchenko 05f51cbb2a Enabled recording the name of the file GIA is coming from.
2012-09-04 13:52:42 -07:00
..
abc
Enabled recording the name of the file GIA is coming from.
2012-09-04 13:52:42 -07:00
abci
Added switch &srm -A <file> for dumping SRM into a user-specified file.
2012-09-02 20:12:03 -07:00
cmd
Improved printout of command history.
2012-08-27 19:57:44 -07:00
io
Fixing the way constants are written into mapped Verilog files.
2012-08-31 00:05:10 -07:00
main
Bug fix: abstraction commands not properly updating status when dumping intermediate abstraction.
2012-08-28 12:12:24 -07:00
test
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
ver
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
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